Previously, the RAM current address was read in the same
cycle as STB and CYC. As the default Wishbone signals are
0's, the RAM read address was 0, which its contents are 0's
for this module.

As the RAM takes one clock cycle to return the requested data,
the Wishbone data output was reading the previous RAM data, which
corresponds to the data in RAM address 0.

This was happening regardless of the Wishbone address and the
Wishbone data output was always one clock cycle too late, which
is not interpreted as valid by the Wishbone Crossbar Switch module.