Add option to use an external supplied clock (usually from
another PLL or global clock buffer inside the FPGA) to clock
the data to downstream FPGA logic. This implies the ASYNC FIFO
after the first ADC acquisition and the synchronization betweem
multiple ADC channels.

This is useful when instantiating more than one ADC module, as
we don't need two reference clocks and more than one reference
would only make things harder.