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Beam Positoning Monitor - Gateware
Commit 2d50219d authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'post-mortem-fix-20170607' into devel 

This fixes #68 github issue
parents c1ba5825 c72ce3df
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Showing with 283 additions and 96 deletions
hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd
View file @ 2d50219d
......@@ -143,6 +143,12 @@ architecture rtl of acq_ddr3_axis_write is
-- Must be power of 2
constant c_ddr_axis_max_btt : natural := 4194304; -- 2^22
constant c_ddr_axis_max_btt_uns : unsigned(c_axis_cmd_tdata_btt_width-1 downto 0) :=
to_unsigned(c_ddr_axis_max_btt, c_axis_cmd_tdata_btt_width);
constant c_ddr_axis_max_btt_uns_padded : unsigned(g_ddr_addr_width-1 downto 0) :=
unsigned(f_gen_std_logic_vector(
g_ddr_addr_width-c_axis_cmd_tdata_btt_width, '0')) &
to_unsigned(c_ddr_axis_max_btt, c_axis_cmd_tdata_btt_width);
-- Maximum words to transfer
constant c_ddr_axis_max_wtt : natural := c_ddr_axis_max_btt/c_ddr_payload_width_byte;
constant c_ddr_axis_max_wtt_width : natural := f_log2_size(c_ddr_axis_max_wtt);
......@@ -150,6 +156,7 @@ architecture rtl of acq_ddr3_axis_write is
-- Flow Control constants
constant c_pkt_size_width : natural := 32;
constant c_addr_cnt_width : natural := c_max_ddr_payload_ratio_log2;
constant c_axis_cmd_width : natural := g_ddr_addr_width + c_axis_cmd_tdata_btt_width;
-- Constants for data + keep aggregate signal
constant c_keep_low : natural := 0;
......@@ -167,6 +174,12 @@ architecture rtl of acq_ddr3_axis_write is
constant c_fc_header_top_idx : natural := g_ddr_header_width + c_ddr_payload_eop_keep_width -1;
constant c_fc_header_bot_idx : natural := c_ddr_payload_eop_keep_width;
-- Constants for addr + btt aggregate signal
constant c_ddr_btt_low : natural := 0;
constant c_ddr_btt_high : natural := c_axis_cmd_tdata_btt_width + c_ddr_btt_low -1;
constant c_ddr_addr_low : natural := c_ddr_btt_high + 1;
constant c_ddr_addr_high : natural := g_ddr_addr_width + c_ddr_addr_low -1;
-- Constants for ddr3 address bits
constant c_ddr_align_shift : natural := f_log2_size(c_addr_ddr_inc);
......@@ -208,6 +221,8 @@ architecture rtl of acq_ddr3_axis_write is
signal fc_eof_pld : std_logic;
signal fc_eop_pld : std_logic;
signal fc_addr : std_logic_vector(g_ddr_addr_width-1 downto 0);
signal fc_btt : std_logic_vector(c_axis_cmd_tdata_btt_width-1 downto 0);
signal fc_addr_btt_cmd : std_logic_vector(c_axis_cmd_width-1 downto 0);
signal fc_stall_cmd : std_logic;
signal fc_dreq_cmd : std_logic;
signal fc_stall_pld : std_logic;
......@@ -256,8 +271,21 @@ architecture rtl of acq_ddr3_axis_write is
-- DDR3 Signals
signal ddr_data_in : std_logic_vector(g_ddr_header_width+g_ddr_payload_width-1 downto 0);
signal ddr_addr_cnt_axis : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_byte_addr_cnt_axis : std_logic_vector(g_ddr_addr_width-1 downto 0);
signal ddr_addr_cnt_max_reached : std_logic;
signal ddr_addr_cnt_m1_max_reached : std_logic;
signal ddr_addr_cnt_next_will_reach_max : std_logic;
signal ddr_addr_cnt_m1_next_will_reach_max : std_logic;
signal ddr_addr_wrap_counter : std_logic;
signal ddr_addr_m1_wrap_counter : std_logic;
signal ddr_btt : unsigned(c_axis_cmd_tdata_btt_width-1 downto 0);
signal ddr_btt_full : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_btt_mem_area_full : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_btt_mem_area_rem : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_btt_slv : std_logic_vector(c_axis_cmd_tdata_btt_width-1 downto 0);
signal ddr_addr_init : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_addr_max : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_addr_max_m1 : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_recv_pkt_cnt : unsigned(c_ddr_axis_max_wtt_width-1 downto 0);
signal ddr_addr_first : std_logic;
signal ddr_reissue_trans : std_logic;
......@@ -266,6 +294,7 @@ architecture rtl of acq_ddr3_axis_write is
signal ddr_addr_in_axis : std_logic_vector(g_ddr_addr_width-1 downto 0);
signal ddr_valid_in : std_logic;
signal ddr_axis_cmd_valid_in : std_logic;
signal ddr_axis_cmd_addr_btt_in : std_logic_vector(c_axis_cmd_width-1 downto 0);
signal ddr_sent_cnt_out : unsigned(f_log2_size(g_max_burst_size)-1 downto 0);
signal ddr_valid_in_t : std_logic;
signal ddr_trigger_in : std_logic;
......@@ -287,6 +316,27 @@ architecture rtl of acq_ddr3_axis_write is
signal ddr_axis_halt : std_logic := '0';
signal hrst_state : t_hrst_state := IDLE;
function f_clip_value(val : unsigned; max_value : unsigned)
return unsigned
is
variable res : unsigned(val'length-1 downto 0);
begin
assert (val'length = max_value'length)
report "[f_clip_value] Array lengths do not match. Left is " &
Integer'image(val'length) & ", Right is " &
Integer'image(max_value'length)
severity Failure;
if val > max_value then
res := max_value;
else
res := val;
end if;
return res;
end;
begin
assert (g_ddr_payload_width = 256 or g_ddr_payload_width = 512)
......@@ -424,7 +474,20 @@ begin
-- around the maximum number of samples per AXI packet
ddr_recv_pkt_cnt <= ddr_recv_pkt_cnt + 1;
if ddr_recv_pkt_cnt = to_unsigned(c_ddr_axis_max_wtt-2, ddr_recv_pkt_cnt'length) then -- will increment to last sample
-- There are 2 cases in which we need to reset the counter and
-- hence reissue a transaction.
--
-- The first one is the obvious one. If we go over the maximum AXI SS
-- maximum number of words. In this case we just end the current transaction
-- and reissue a next one with the current address.
--
-- The second one is if we go over the current channel "ddr_addr_max"
-- signal. In this case, we also need to reissue the transaction with
-- the wrapped memory address, because we only do INCR AXI transaction.
-- And in this mode, the memory addresses are incremented automatically
-- for each word.
if ddr_recv_pkt_cnt = to_unsigned(c_ddr_axis_max_wtt-2, ddr_recv_pkt_cnt'length) or
(ddr_addr_m1_wrap_counter = '1' and ddr_addr_wrap_counter = '0') then -- will increment to last sample
ddr_eop_in <= "1";
else
ddr_eop_in <= "0";
......@@ -488,8 +551,6 @@ begin
end if;
end process;
-- First address or transaction wrapped to init address
ddr_addr_first <= '1' when ddr_addr_cnt_axis = ddr_addr_init else '0';
-- First packet of transaction (new shot - used for multishot transactions) or
-- when we make large (larger than c_ddr_axis_max_wtt words) transfers
ddr_axis_cmd_valid_in <= '1' when ddr_valid_in = '1' and (ddr_addr_first = '1' or
......@@ -517,25 +578,46 @@ begin
begin
if rising_edge(ext_clk_i) then
if ext_rst_n_i = '0' then
ddr_addr_cnt_axis <= to_unsigned(0, ddr_addr_cnt_axis'length);
-- FIXME: Reset the init/end register cause fast acquisition
-- data path to fail on hw or sw trigger acquisitions.
-- This might be related to the fact that these addresses
-- might not be properly configured.
ddr_addr_first <= '1';
-- This address must be word-aligned
ddr_addr_cnt_axis <= unsigned(wr_init_addr_alig);
ddr_addr_init <= unsigned(wr_init_addr_alig);
ddr_addr_max <= unsigned(wr_end_addr_alig);
-- FIXME. Logic on reset tree.
ddr_addr_max_m1 <= unsigned(wr_end_addr_alig)-c_addr_ddr_inc_axis;
ddr_btt_full <= to_unsigned(0, ddr_btt_full'length);
else
if wr_start_i = '1' then
-- First word in the transaction
ddr_addr_first <= '1';
-- This address must be word-aligned
ddr_addr_cnt_axis <= unsigned(wr_init_addr_alig);
ddr_addr_init <= unsigned(wr_init_addr_alig);
ddr_addr_max <= unsigned(wr_end_addr_alig);
ddr_addr_max_m1 <= unsigned(wr_end_addr_alig)-c_addr_ddr_inc_axis;
-- Transfer up to the remaining of the memory area
ddr_btt_full <= f_clip_value(ddr_btt_mem_area_full, c_ddr_axis_max_btt_uns_padded);
elsif ddr_valid_in = '1' then -- This represents a successful transfer
-- No more the first transaction. This train has departed already...
ddr_addr_first <= '0';
-- Always calculate the number of bytes to be transmitted.
-- This will only be written when a new command is issued,
-- so we need to have the correct value at all times.
ddr_btt_full <= f_clip_value(ddr_btt_mem_area_rem, c_ddr_axis_max_btt_uns_padded);
-- This case only happens when the DDR addr will wrap. So, we reset BTT to
-- the maximum allowed for the memory region
if unsigned(ddr_addr_cnt_axis) > unsigned(wr_end_addr_alig) or
ddr_addr_wrap_counter = '1' then
ddr_btt_full <= f_clip_value(ddr_btt_mem_area_full, c_ddr_axis_max_btt_uns_padded);
end if;
-- To Flow Control module
-- Get ready for the next valid transaction
ddr_addr_cnt_axis <= ddr_addr_cnt_axis + c_addr_ddr_inc_axis;
-- Wrap counters if we go over the limit
if ddr_addr_cnt_axis = ddr_addr_max then
if ddr_addr_wrap_counter = '1' then
ddr_addr_cnt_axis <= ddr_addr_init;
end if;
end if;
......@@ -543,8 +625,33 @@ begin
end if;
end process;
ddr_btt_mem_area_full <= unsigned(wr_end_addr_alig) - unsigned(wr_init_addr_alig);
ddr_btt_mem_area_rem <= unsigned(wr_end_addr_alig) - unsigned(ddr_addr_cnt_axis);
-- Crop number of bits to the maximum allowed by datamover. This only matters
-- if we have smaller (less than 2^23) quantities anyway.
ddr_btt <= ddr_btt_full(ddr_btt'left downto 0);
-- calculate if the next address will go over the limit
ddr_addr_cnt_next_will_reach_max <= '1' when ddr_addr_cnt_axis + c_addr_ddr_inc_axis > ddr_addr_max else '0';
ddr_addr_cnt_m1_next_will_reach_max <= '1' when ddr_addr_cnt_axis + c_addr_ddr_inc_axis > ddr_addr_max_m1 else '0';
-- We must compare the limit using >=, as the input wr_end_addr_alig may not
-- be multiple of "c_addr_ddr_inc_axis". Thus not allowing us to use "=" only
ddr_addr_cnt_max_reached <= '1' when ddr_addr_cnt_axis >= ddr_addr_max else '0';
ddr_addr_cnt_m1_max_reached <= '1' when ddr_addr_cnt_axis >= ddr_addr_max_m1 else '0';
-- Wrap counter flags
ddr_addr_wrap_counter <= '1' when ddr_addr_cnt_next_will_reach_max = '1' or
ddr_addr_cnt_max_reached = '1' else '0';
ddr_addr_m1_wrap_counter <= '1' when ddr_addr_cnt_m1_next_will_reach_max = '1' or
ddr_addr_cnt_m1_max_reached = '1' else '0';
-- To Flow Control module
ddr_addr_in_axis <= std_logic_vector(ddr_addr_cnt_axis);
ddr_btt_slv <= std_logic_vector(ddr_btt);
ddr_axis_cmd_addr_btt_in(c_ddr_addr_high downto c_ddr_addr_low) <= ddr_addr_in_axis;
ddr_axis_cmd_addr_btt_in(c_ddr_btt_high downto c_ddr_btt_low) <= ddr_btt_slv;
-- Debug outputs
dbg_ddr_addr_cnt_axis_o <= std_logic_vector(ddr_addr_cnt_axis);
......@@ -584,9 +691,9 @@ begin
-- Only count up to the sample when in pre_trigger or post_trigger and we haven't
-- acquire enough samples
pl_cmd_cnt_en <= '1' when (unsigned(dbg_cmd_pkt_ct_cnt) < lmt_pre_pkt_size and
pl_cmd_cnt_en <= '1' when (unsigned(dbg_cmd_pkt_ct_cnt) < lmt_pre_pkt_size_aggd and
fc_data_id_cmd = "010") or -- Pre-trigger
(unsigned(dbg_cmd_pkt_ct_cnt) < lmt_full_pkt_size and
(unsigned(dbg_cmd_pkt_ct_cnt) < lmt_full_pkt_size_aggd and
fc_data_id_cmd = "100") -- Post-trigger
else '0';
......@@ -595,9 +702,9 @@ begin
-- Only count up to the sample when in pre_trigger or post_trigger and we haven't
-- acquire enough samples
pl_pld_cnt_en <= '1' when (unsigned(dbg_pld_pkt_ct_cnt) < lmt_pre_pkt_size and
pl_pld_cnt_en <= '1' when (unsigned(dbg_pld_pkt_ct_cnt) < lmt_pre_pkt_size_aggd and
fc_data_id_cmd = "010") or -- Pre-trigger
(unsigned(dbg_pld_pkt_ct_cnt) < lmt_full_pkt_size and
(unsigned(dbg_pld_pkt_ct_cnt) < lmt_full_pkt_size_aggd and
fc_data_id_cmd = "100") -- Post-trigger
else '0';
......@@ -691,7 +798,7 @@ begin
g_header_in_width => g_ddr_header_width,
g_data_width => 0, -- Dummy value
g_pkt_size_width => c_pkt_size_width,
g_addr_width => g_ddr_addr_width,
g_addr_width => c_axis_cmd_width,
g_with_fifo_inferred => true,
g_pipe_size => g_fc_pipe_size
)
......@@ -700,7 +807,7 @@ begin
rst_n_i => ext_rst_n_i,
pl_data_i => (others => '0'),
pl_addr_i => ddr_addr_in_axis,
pl_addr_i => ddr_axis_cmd_addr_btt_in,
pl_valid_i => ddr_axis_cmd_valid_in,
pl_dreq_o => pl_dreq_cmd,
......@@ -719,7 +826,7 @@ begin
fc_dout_o => fc_header_cmd,
fc_valid_o => fc_valid_cmd,
fc_addr_o => fc_addr,
fc_addr_o => fc_addr_btt_cmd,
fc_sof_o => fc_sof_cmd,
fc_eof_o => fc_eof_cmd,
......@@ -727,6 +834,9 @@ begin
fc_dreq_i => fc_dreq_cmd
);
fc_addr <= fc_addr_btt_cmd(c_ddr_addr_high downto c_ddr_addr_low);
fc_btt <= fc_addr_btt_cmd(c_ddr_btt_high downto c_ddr_btt_low);
-----------------------------------------------------------------------------
-- DDR3 AXIS Write Interface
-----------------------------------------------------------------------------
......@@ -806,7 +916,7 @@ begin
ddr_axis_rstn <= '1';
ddr_axis_halt <= '0';
if ext_rst_n_i = '0' then
if ext_rst_n_i = '0' or wr_start_i = '1' then
hrst_state <= HALT_GEN;
end if;
......@@ -873,12 +983,12 @@ begin
axis_s2mm_cmd_tvalid_o <= fc_valid_cmd;
-- With 23 bits we can transfer up to 8MB of data. We always set the datamover
-- to transfer the maximum ammount of data. If we finish early, we can just
-- abort the transaction asserting the LTAST stream signal (typical case).
-- to transfer the maximum ammount of data up to the end of the memory region.
-- If we finish early, we can just abort the transaction asserting the TLAST
-- stream signal (typical case).
-- WARNING: the datamover MUST be set the support Indeterminate BTT!
axis_s2mm_cmd_tdata_o(c_axis_cmd_tdata_btt_top_idx downto
c_axis_cmd_tdata_btt_bot_idx) <=
std_logic_vector(to_unsigned(c_ddr_axis_max_btt, c_axis_cmd_tdata_btt_width)); -- cmd_btt (Bytes to transfer)
c_axis_cmd_tdata_btt_bot_idx) <= fc_btt; -- cmd_btt (Bytes to transfer)
axis_s2mm_cmd_tdata_o(c_axis_cmd_tdata_type_idx) <= '1'; -- cmd_type (1 = increment address)
axis_s2mm_cmd_tdata_o(c_axis_cmd_tdata_dsa_top_idx downto
c_axis_cmd_tdata_dsa_bot_idx) <= "000000"; -- cmd_dsa
......
hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
View file @ 2d50219d
......@@ -220,6 +220,8 @@ architecture rtl of wb_acq_core is
constant c_p2l_with_pulse2level : t_acq_bool_array(c_p2l_num_inputs-1 downto 0) :=
(false, true, true, false, true, true);
constant c_acq_start_fs_rst_pulse_width : natural := 16;
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
......@@ -269,6 +271,13 @@ architecture rtl of wb_acq_core is
signal acq_start : std_logic;
signal acq_start_sync_ext : std_logic;
signal acq_start_sync_fs : std_logic;
signal acq_start_rst : std_logic;
signal acq_start_pp_fs_sync : std_logic;
signal acq_start_rst_fs_sync : std_logic;
signal acq_start_rst_ext_sync : std_logic;
signal acq_start_rstn_fs_sync : std_logic;
signal acq_start_rstn_ext_sync : std_logic;
signal acq_start_safe : std_logic;
signal acq_now : std_logic;
signal acq_stop : std_logic;
signal acq_end : std_logic;
......@@ -445,8 +454,8 @@ begin
report "[wb_acq_core] Only g_acq_num_channels less or equal 24 is supported!"
severity Failure;
fs_rst_n <= fs_rst_n_i and acq_fsm_rstn_fs_sync;
ext_rst_n <= ext_rst_n_i and acq_fsm_rstn_ext_sync;
fs_rst_n <= fs_rst_n_i and acq_fsm_rstn_fs_sync and acq_start_rstn_fs_sync;
ext_rst_n <= ext_rst_n_i and acq_fsm_rstn_ext_sync and acq_start_rstn_ext_sync;
-----------------------------
-- Slave adapter for Wishbone Register Interface
......@@ -722,7 +731,7 @@ begin
acq_trig_i => acq_trig_i,
lmt_curr_chan_id_i => lmt_dtrig_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
-----------------------------
-- Output Interface.
......@@ -756,7 +765,7 @@ begin
acq_trig_i => acq_trig_i,
lmt_curr_chan_id_i => lmt_curr_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
-----------------------------
-- Output Interface.
......@@ -799,7 +808,7 @@ begin
dtrig_id_i => dtrig_id_in,
lmt_dtrig_chan_id_i => lmt_dtrig_chan_id,
lmt_dtrig_valid_i => acq_start,
lmt_dtrig_valid_i => acq_start_safe,
acq_data_i => acq_data_marsh(c_acq_data_width-1 downto 0),
acq_valid_i => acq_dvalid_in,
......@@ -807,7 +816,7 @@ begin
acq_trig_i => acq_trig_in,
lmt_curr_chan_id_i => lmt_curr_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
acq_wr_en_i => acq_fsm_accepting,
acq_data_o => acq_data,
......@@ -853,7 +862,7 @@ begin
post_trig_samples_i => post_trig_samples_c,
shots_nb_i => shots_nb_c,
lmt_curr_chan_id_i => lmt_curr_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
samples_cnt_o => samples_cnt,
-----------------------------
......@@ -976,7 +985,7 @@ begin
-- Request transaction reset as soon as possible (when all outstanding
-- transactions have been commited)
req_rst_trans_i => acq_fsm_req_rst, -- FIXME: Could this be acq_start = '1'???
req_rst_trans_i => acq_fsm_req_rst,
-- Select between multi-buffer mode and pass-through mode (data directly
-- through external module interface)
passthrough_en_i => acq_single_shot,
......@@ -994,7 +1003,7 @@ begin
-- Number of shots in this acquisition
lmt_shots_nb_i => lmt_shots_nb,
--lmt_valid_i => lmt_valid,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
fifo_fc_all_trans_done_p_o => fifo_fc_all_trans_done_p,
-- Asserted when the Acquisition FIFO is full. Data is lost when this signal is
......@@ -1022,6 +1031,64 @@ begin
dbg_shots_cnt_o => dbg_shots_cnt
);
------------------------------------------------------------------------------
-- Delayed start and modules reset
------------------------------------------------------------------------------
-- Reset all modules on each new acquisition. This is the first thing to
-- happen when we start an acquisition. After that, all modules are
-- started accordingly. This would be better described as a FSM, maybe,
-- but it works fine for now.
-- Acquisition start chain:
-- acq_start -> acq_start_safe -> acq_start_sync_ext -> acq_start_sync_fs
-- Extend acq_start to function as a reset to all modules
cmp_acq_start_rst_extended : gc_extend_pulse
generic map (
g_width => c_acq_start_fs_rst_pulse_width
)
port map(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
pulse_i => acq_start,
extended_o => acq_start_rst
);
-- Sync and pipeline reset signals
cmp_reset_fs_synch : reset_synch
port map(
clk_i => fs_clk_i,
arst_n_i => acq_start_rst,
rst_n_o => acq_start_rst_fs_sync
);
cmp_reset_ext_synch : reset_synch
port map(
clk_i => ext_clk_i,
arst_n_i => acq_start_rst,
rst_n_o => acq_start_rst_ext_sync
);
acq_start_rstn_fs_sync <= not(acq_start_rst_fs_sync);
acq_start_rstn_ext_sync <= not(acq_start_rst_ext_sync);
-- Use the negative edge of the extended pulse to trigger the acq_start
-- and start all modules.
cmp_edge_detector : gc_sync_ffs
generic map(
g_sync_edge => "positive")
port map(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
data_i => acq_start_rst_fs_sync,
synced_o => open,
npulse_o => acq_start_pp_fs_sync,
ppulse_o => open
);
acq_start_safe <= acq_start_pp_fs_sync;
------------------------------------------------------------------------------
-- Pulse to Level and Synchronizer circuits
------------------------------------------------------------------------------
......@@ -1074,7 +1141,7 @@ begin
p2l_clk_out(c_p2l_acq_start_idx) <= ext_clk_i;
p2l_rst_out_n(c_p2l_acq_start_idx) <= ext_rst_n;
p2l_pulse(c_p2l_acq_start_idx) <= acq_start;
p2l_pulse(c_p2l_acq_start_idx) <= acq_start_safe;
p2l_clr(c_p2l_acq_start_idx) <= '0'; -- not used
acq_start_sync_ext <= p2l_pulse_synched(c_p2l_acq_start_idx);
......@@ -1102,7 +1169,7 @@ begin
ddr3_all_trans_done_l <= p2l_level_synched(c_p2l_ddr3_all_trans_done_idx);
-- FIXME: We use the additional latency introduced by the conversion circuits
-- acq_start -> acq_start_sync_ext -> acq_start_sync_fs to give time to modules
-- acq_start -> acq_start_safe -> acq_start_sync_ext -> acq_start_sync_fs to give time to modules
-- downstream (acq_ddr_iface and the ones clocked by ext_clk_i) to configure
-- themselves before starting the actual acquisition. Without this, the modules
-- can misbehave as the number of samples would not be correctly set, for
......
hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd
View file @ 2d50219d
......@@ -536,9 +536,17 @@ begin -- architecture rtl
--
-- If we want to input data, we use the pins as usual: data as data and
-- direction as direction.
--
-- Notice that for FPGA output:
-- Direction pin 0 = Input to FPGA
-- Direction pin 1 = Output to FPGA
--
-- So, we must negate the data pin so, sending 1 will set the FPGA
-- to output ('0' in iobuf) and sending 0 will set the FPGA to input
-- ('1' in iobuf)
trig_dir_int(i) <= ch_regs_out(i).ch_ctl_dir;
trig_pol_int(i) <= ch_regs_out(i).ch_ctl_dir_pol;
trig_data_int(i) <= extended_transm(i);
trig_data_int(i) <= not (extended_transm(i));
-- Regular data/direction driving with polarity inversion
trig_dir_polarized(i) <= trig_dir_int(i) when trig_pol_int(i) = '0' else
......
hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave_compl.do
View file @ 2d50219d
......@@ -11,6 +11,12 @@ quietly virtual signal -install /wb_acq_core_tb/cmp0_data_checker { /wb_acq_core
quietly virtual signal -install /wb_acq_core_tb/cmp0_data_checker { /wb_acq_core_tb/cmp0_data_checker/fifo_exp_dout(286 downto 31)} data_exp
quietly virtual signal -install /wb_acq_core_tb/cmp0_data_checker { /wb_acq_core_tb/cmp0_data_checker/fifo_act_dout(286 downto 31)} data_act
quietly virtual signal -install /wb_acq_core_tb/cmp0_data_checker { /wb_acq_core_tb/cmp0_data_checker/fifo_act_dout(30 downto 0)} addr_act
quietly virtual signal -install /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface { /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o(22 downto 0)} axis_btt
quietly virtual signal -install /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface {/wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o(23) } axis_type
quietly virtual signal -install /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface { /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o(29 downto 24)} axis_dsa
quietly virtual signal -install /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface {/wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o(40) } axis_eof
quietly virtual signal -install /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface {/wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o(31) } axis_drr
quietly virtual signal -install /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface { /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o(63 downto 32)} axis_addr
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider testbench
add wave -noupdate /wb_acq_core_tb/c_data_max
......@@ -502,8 +508,6 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/lmt_valid_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_wr_en_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/lmt_dtrig_chan_id
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/lmt_dtrig_chan_id_uncoalesced
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/lmt_dtrig_chan_id_uncoalesced_id
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/lmt_dtrig_valid
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/lmt_curr_chan_id
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/lmt_valid
......@@ -515,8 +519,6 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_atoms
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_num_atoms
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_num_atoms_uncoalesced
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_num_coalesce_max
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_coalesce_cnt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_valid_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_valid_sel_out
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_trig/acq_valid_out
......@@ -624,7 +626,6 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_fsm/c_ext_fsm_pulse_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_fsm/c_num_coalesce_array
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_fsm/c_num_coalesce_log2_array
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_fsm/curr_num_coalese_log2
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_fsm/lmt_acq_full_pkt_size
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_fsm/lmt_acq_pos_pkt_size
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/cmp_acq_fsm/lmt_acq_pre_pkt_size
......@@ -916,20 +917,6 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_full_pkt_size_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_shots_nb_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_valid_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tready_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tready_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fifo_fc_dreq_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fifo_fc_stall_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_all_trans_done_p_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_ddr_trig_addr_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tvalid_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tdata_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tkeep_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tlast_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tvalid_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_pre_pkt_size
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_pre_pkt_size_s
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_pre_pkt_size_alig_s
......@@ -961,6 +948,8 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_eof_pld
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_eop_pld
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_btt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_addr_btt_cmd
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_stall_cmd
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_dreq_cmd
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fc_stall_pld
......@@ -977,8 +966,6 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/cnt_all_trans_done_cmd_l
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/cnt_all_trans_done_pld_l
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/cnt_all_trans_done_p
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/wr_init_addr_alig
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/wr_end_addr_alig
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/pl_dreq
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/pl_stall
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/pl_stall_d0
......@@ -1000,16 +987,24 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/pl_pld_cnt_en
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/acq_pld_cnt_en
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_data_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_cnt_axis
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_cnt_max_reached
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_cnt_m1_max_reached
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_cnt_next_will_reach_max
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_cnt_m1_next_will_reach_max
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_wrap_counter
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_m1_wrap_counter
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_btt_slv
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_init
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_max
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_max_m1
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_recv_pkt_cnt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_first
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_reissue_trans
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_new_shot_coming
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_in_axis
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_valid_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_axis_cmd_valid_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_axis_cmd_addr_btt_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_sent_cnt_out
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_valid_in_t
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_trigger_in
......@@ -1022,39 +1017,48 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_data_eop_keep_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_rdy_cmd
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_rdy_pld
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_payload_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_acq_channels
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_acq_chan_slice
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_fc_payload_ratio
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_fc_payload_ratio_log2
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_max_ddr_payload_ratio_log2
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_keep_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_eop_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_payload_eop_keep_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_bytes_per_word
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_bytes_per_word_log2
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_addr_ddr_inc
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_addr_ddr_inc_axis
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_payload_width_byte
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_payload_width_byte_log2
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_axis_max_btt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_axis_max_wtt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_axis_max_wtt_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_pkt_size_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_addr_cnt_width
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_keep_low
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_keep_high
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_eop_low
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_eop_high
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_data_low
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_data_high
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_header_low
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_header_high
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_header_top_idx
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_header_bot_idx
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_fc_header_top_idx
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_fc_header_bot_idx
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/c_ddr_align_shift
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_axis_rstn
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_axis_halt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/hrst_state
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_halt_cmplt_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_addr_req_posted_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_wr_xfer_cmplt_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_ld_nxt_len_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_wr_len_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fifo_fc_dreq_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/fifo_fc_stall_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_all_trans_done_p_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/lmt_ddr_trig_addr_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_axis_cmd_valid_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_btt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_btt_full
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_btt_mem_area_full
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_btt_mem_area_rem
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/wr_init_addr_alig
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/wr_end_addr_alig
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_addr_cnt_axis
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/ddr_byte_addr_cnt_axis
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_drr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_eof
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_dsa
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_type
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_btt
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tready_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tready_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tdata_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_cmd_tvalid_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tdata_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tkeep_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tlast_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_pld_tvalid_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_rstn_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_halt_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/axis_s2mm_allow_addr_req_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/dbg_ddr_addr_cnt_axis_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/dbg_ddr_addr_init_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/dbg_ddr_addr_max_o
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_axis_interface/cmp_acq_ddr3_iface/addr
add wave -noupdate -divider ddr3_axis_readback0
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ext_clk_i
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ext_rst_n_i
......@@ -1105,7 +1109,6 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/lmt_full_pkt_addr_ms
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/lmt_pre_pkt_addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/lmt_pre_full_addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/sample_size
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ddr_data_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ddr_addr_inc
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(0)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ddr_addr_cnt_out
......@@ -1186,7 +1189,6 @@ add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/lmt_pre_pkt_addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/lmt_pre_full_addr
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/lmt_pre_full_addr_m
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/sample_size
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ddr_data_in
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ddr_addr_inc
add wave -noupdate /wb_acq_core_tb/dut/cmp_wb_facq_core_mux/gen_facq_core(1)/cmp_wb_facq_core/cmp_wb_acq_core/gen_ddr3_readback/gen_ddr3_readback_axis_interface/cmp_acq_ddr3_read/ddr_addr_cnt_out
......@@ -1592,10 +1594,10 @@ add wave -noupdate /wb_acq_core_tb/cmp1_data_checker/chk_pass_o
add wave -noupdate /wb_acq_core_tb/cmp1_data_checker/exp_addr
add wave -noupdate /wb_acq_core_tb/cmp1_data_checker/act_addr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {147139918260 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 264
configure wave -valuecolwidth 313
WaveRestoreCursors {{Cursor 1} {203437500000 fs} 0} {{Cursor 2} {207107500000 fs} 0}
quietly wave cursor active 2
configure wave -namecolwidth 295
configure wave -valuecolwidth 180
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
......@@ -1608,4 +1610,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {985246678214 fs} {986488619137 fs}
WaveRestoreZoom {206941717318 fs} {207490953867 fs}
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