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Beam Positoning Monitor - Gateware
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Beam Positoning Monitor - Gateware
Commits
3a93af6c
Commit
3a93af6c
authored
Jul 21, 2017
by
Lucas Russo
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modules/*/wb_fmc250m_4ch: remove commented out lines
parent
c5483d49
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2 additions
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7 deletions
+2
-7
wb_fmc250m_4ch.vhd
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
+2
-7
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hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
View file @
3a93af6c
...
...
@@ -530,9 +530,9 @@ architecture rtl of wb_fmc250m_4ch is
end
component
;
begin
-- Reset signals and sychronization with positive edge of
-- respective clock
--sys_rst_n <= sys_rst_n_i and mmcm_adc_locked;
sys_rst_n
<=
sys_rst_n_i
;
fs_rst_n
<=
sys_rst_n
and
mmcm_adc_locked
;
...
...
@@ -545,9 +545,6 @@ begin
rst_n_o
=>
sys_rst_sync_n
);
--sys_rst_sync_n <= sys_rst_n;
-- Reset synchronization with FS clock domain (just clock 1
-- is used for now). Align the reset deassertion to the next
-- clock edge
...
...
@@ -557,7 +554,6 @@ begin
port
map
(
clk_i
=>
fs_clk
(
i
),
arst_n_i
=>
fs_rst_n
,
--rst_n_o => fs_rst_sync_n
rst_n_o
=>
fs_rst_sync_n
(
i
)
);
...
...
@@ -571,7 +567,6 @@ begin
-- Output adc sync'ed reset to downstream FPGA logic
adc_rst_n_o
(
i
)
<=
fs_rst_sync_n
(
i
);
adc_rst2x_n_o
(
i
)
<=
fs_rst2x_sync_n
(
i
);
--fs_rst_sync_n(i) <= fs_rst_n;
end
generate
;
end
generate
;
...
...
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