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Lucas Russo authored
Now, we have the possibility to clock each wb_acq_core module independently and synchronize everyone to an external memory clock (ext_clk_i). This should improve the decoupling of FMCs clock trees.
4b940b2e
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| .. | ||
| Manifest.py | ||
| wb_acq_core_2_to_1_mux.vhd | ||
| wb_acq_core_2_to_1_mux_plain.vhd | ||
| xwb_acq_core_2_to_1_mux.vhd |