This was causing a bug in that, on trigger modes,
the trigger sample was detected on a unaligned number
of atoms (DDR size / channel atom size). This causes
the FIFO module (acq_fc_fifo) to finish the previous
transaction on a undefined FIFO (0, 1, 2 or 3) number.

In that case, the next transaction would wrongly assume
that new data was already present in some FIFO and read
the FIFOs prematurely, causing either a missing sample
for the DDR3 interface module or simply data belonging
to the previous acquisition.