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Beam Positoning Monitor - Software
Commit 2935152c authored by Lucas Russo's avatar Lucas Russo
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include/chips/*: fix chips offsets' to support new protocol layer

parent 03bd570d
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Showing with 14 additions and 10 deletions
include/chips/ad9510_regs.h
View file @ 2935152c
...@@ -24,18 +24,16 @@ ...@@ -24,18 +24,16 @@
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value)) #define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif #endif
#define AD9510_TRASNS_SIZE 24 /* in bits */
/* AD9510 Instruction Header for 24-bit transfers */ /* AD9510 Instruction Header for 24-bit transfers */
/* AD9510 Transfer type field */ /* AD9510 Transfer type field */
#define AD9510_HDR_RW_SIZE 1 #define AD9510_HDR_RW_SIZE 1
#define AD9510_HDR_RW_SHIFT 23 #define AD9510_HDR_RW_SHIFT 15
#define AD9510_HDR_RW WBGEN2_GEN_MASK(AD9510_HDR_RW_SHIFT, \ #define AD9510_HDR_RW WBGEN2_GEN_MASK(AD9510_HDR_RW_SHIFT, \
AD9510_HDR_RW_SIZE) AD9510_HDR_RW_SIZE)
/* AD9510 Byte transfer field */ /* AD9510 Byte transfer field */
#define AD9510_HDR_BT_SIZE 2 #define AD9510_HDR_BT_SIZE 2
#define AD9510_HDR_BT_SHIFT 21 #define AD9510_HDR_BT_SHIFT 13
#define AD9510_HDR_BT_MASK WBGEN2_GEN_MASK(AD9510_HDR_BT_SHIFT, \ #define AD9510_HDR_BT_MASK WBGEN2_GEN_MASK(AD9510_HDR_BT_SHIFT, \
AD9510_HDR_BT_SIZE) AD9510_HDR_BT_SIZE)
#define AD9510_HDR_BT_W(value) WBGEN2_GEN_WRITE(value, AD9510_HDR_BT_SHIFT, \ #define AD9510_HDR_BT_W(value) WBGEN2_GEN_WRITE(value, AD9510_HDR_BT_SHIFT, \
...@@ -46,7 +44,7 @@ ...@@ -46,7 +44,7 @@
/* AD9510 Address field. Only the bits 0 to 6 are available. The remaining 7 to 12 /* AD9510 Address field. Only the bits 0 to 6 are available. The remaining 7 to 12
* are fixed to 0, as mandated by the AD9510 rev. B datasheet */ * are fixed to 0, as mandated by the AD9510 rev. B datasheet */
#define AD9510_HDR_ADDR_SIZE 7 #define AD9510_HDR_ADDR_SIZE 7
#define AD9510_HDR_ADDR_SHIFT 8 #define AD9510_HDR_ADDR_SHIFT 0
#define AD9510_HDR_ADDR_MASK WBGEN2_GEN_MASK(AD9510_HDR_ADDR_SHIFT, \ #define AD9510_HDR_ADDR_MASK WBGEN2_GEN_MASK(AD9510_HDR_ADDR_SHIFT, \
AD9510_HDR_ADDR_SIZE) AD9510_HDR_ADDR_SIZE)
#define AD9510_HDR_ADDR_W(value) WBGEN2_GEN_WRITE(value, AD9510_HDR_ADDR_SHIFT, \ #define AD9510_HDR_ADDR_W(value) WBGEN2_GEN_WRITE(value, AD9510_HDR_ADDR_SHIFT, \
...@@ -54,6 +52,10 @@ ...@@ -54,6 +52,10 @@
#define AD9510_HDR_ADDR_R(reg) WBGEN2_GEN_READ(reg, AD9510_HDR_ADDR_SHIFT, \ #define AD9510_HDR_ADDR_R(reg) WBGEN2_GEN_READ(reg, AD9510_HDR_ADDR_SHIFT, \
AD9510_HDR_ADDR_SIZE) AD9510_HDR_ADDR_SIZE)
#define AD9510_INSTADDR_SIZE (AD9510_HDR_RW_SIZE + \
AD9510_HDR_BT_SIZE + \
AD9510_HDR_ADDR_SIZE)
/* AD9510 Data for 24-bit transfers */ /* AD9510 Data for 24-bit transfers */
#define AD9510_DATA_SIZE 8 #define AD9510_DATA_SIZE 8
#define AD9510_DATA_SHIFT 0 #define AD9510_DATA_SHIFT 0
...@@ -64,6 +66,8 @@ ...@@ -64,6 +66,8 @@
#define AD9510_DATA_R(reg) WBGEN2_GEN_READ(reg, AD9510_DATA_SHIFT, \ #define AD9510_DATA_R(reg) WBGEN2_GEN_READ(reg, AD9510_DATA_SHIFT, \
AD9510_DATA_SIZE) AD9510_DATA_SIZE)
#define AD9510_TRANS_SIZE (AD9510_INSTADDR_SIZE+AD9510_DATA_SIZE) /* in bits */
/* AD9510 Register map, as described by the AD9510 reb. B datasheet. Not all of them /* AD9510 Register map, as described by the AD9510 reb. B datasheet. Not all of them
* are descried here, just the ones we use */ * are descried here, just the ones we use */
#define AD9510_REG_CFG_SERIAL 0x00 #define AD9510_REG_CFG_SERIAL 0x00
......
include/chips/isla216p_regs.h
View file @ 2935152c
...@@ -44,13 +44,13 @@ ...@@ -44,13 +44,13 @@
/* ISLA216P Transfer type field */ /* ISLA216P Transfer type field */
#define ISLA216P_HDR_RW_SIZE 1 #define ISLA216P_HDR_RW_SIZE 1
#define ISLA216P_HDR_RW_SHIFT 23 #define ISLA216P_HDR_RW_SHIFT 15
#define ISLA216P_HDR_RW WBGEN2_GEN_MASK(ISLA216P_HDR_RW_SHIFT, \ #define ISLA216P_HDR_RW WBGEN2_GEN_MASK(ISLA216P_HDR_RW_SHIFT, \
ISLA216P_HDR_RW_SIZE) ISLA216P_HDR_RW_SIZE)
/* ISLA216P Byte transfer field */ /* ISLA216P Byte transfer field */
#define ISLA216P_HDR_BT_SIZE 2 #define ISLA216P_HDR_BT_SIZE 2
#define ISLA216P_HDR_BT_SHIFT 21 #define ISLA216P_HDR_BT_SHIFT 13
#define ISLA216P_HDR_BT_MASK WBGEN2_GEN_MASK(ISLA216P_HDR_BT_SHIFT, \ #define ISLA216P_HDR_BT_MASK WBGEN2_GEN_MASK(ISLA216P_HDR_BT_SHIFT, \
ISLA216P_HDR_BT_SIZE) ISLA216P_HDR_BT_SIZE)
#define ISLA216P_HDR_BT_W(value) WBGEN2_GEN_WRITE(value, ISLA216P_HDR_BT_SHIFT, \ #define ISLA216P_HDR_BT_W(value) WBGEN2_GEN_WRITE(value, ISLA216P_HDR_BT_SHIFT, \
...@@ -60,7 +60,7 @@ ...@@ -60,7 +60,7 @@
/* ISLA216P Address field */ /* ISLA216P Address field */
#define ISLA216P_HDR_ADDR_SIZE 13 #define ISLA216P_HDR_ADDR_SIZE 13
#define ISLA216P_HDR_ADDR_SHIFT 8 #define ISLA216P_HDR_ADDR_SHIFT 0
#define ISLA216P_HDR_ADDR_MASK WBGEN2_GEN_MASK(ISLA216P_HDR_ADDR_SHIFT, \ #define ISLA216P_HDR_ADDR_MASK WBGEN2_GEN_MASK(ISLA216P_HDR_ADDR_SHIFT, \
ISLA216P_HDR_ADDR_SIZE) ISLA216P_HDR_ADDR_SIZE)
#define ISLA216P_HDR_ADDR_W(value) WBGEN2_GEN_WRITE(value, ISLA216P_HDR_ADDR_SHIFT, \ #define ISLA216P_HDR_ADDR_W(value) WBGEN2_GEN_WRITE(value, ISLA216P_HDR_ADDR_SHIFT, \
...@@ -275,8 +275,8 @@ ...@@ -275,8 +275,8 @@
ISLA216P_NAPSLP_SIZE) ISLA216P_NAPSLP_SIZE)
#define ISLA216P_NAPSLP_PIN_CONTROL 0 #define ISLA216P_NAPSLP_PIN_CONTROL 0
#define ISLA216P_NAPSLP_NORMAL_OPERATION (1<<0) #define ISLA216P_NAPSLP_NORMAL_OPERATION (1<<0)
#define ISLA216P_NAPSLP_NAP_MODE (1<<1) #define ISLA216P_NAPSLP_NAP_MODE (1<<1)
#define ISLA216P_NAPSLP_SLEEP_MODE (1<<2) #define ISLA216P_NAPSLP_SLEEP_MODE (1<<2)
#endif #endif
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