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Beam Positoning Monitor - Software
Commit 7590f635 authored by Lucas Russo's avatar Lucas Russo
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various: add FMC250M_4CH support (still with missing functions)

parent b442b6c3
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include/boards/afcv3/chips_addr.h
View file @ 7590f635
......@@ -16,4 +16,14 @@ extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_isla216p_addr[NUM_FMC250M_4CH_SMIOS][NUM_FMC250M_4CH_ISLA216P];
extern const uint32_t fmc250m_4ch_pca9547_addr[NUM_FMC250M_4CH_SMIOS];
#endif
include/boards/afcv3/mem_layout.h
View file @ 7590f635
......@@ -9,6 +9,7 @@
#define NUM_MAX_BPMS (NUM_MAX_SLOTS * NUM_MAX_BPM_PER_SLOT)
#define NUM_FMC130M_4CH_SMIOS 2
#define NUM_FMC250M_4CH_SMIOS 2
/*********************** Static AFCv3 FPGA layout ***********************/
/* FMC_130M Components */
......@@ -18,6 +19,14 @@
#define FMC_130M_EEPROM_RAW_I2C_OFFS 0x0300
#define FMC_130M_LM75A_RAW_I2C_OFFS 0x0400
/* FMC_250M Components */
#define FMC_250M_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_250M_AMC7823_RAW_SPI_OFFS 0x0100
#define FMC_250M_ISLA216P_RAW_SPI_OFFS 0x0200
#define FMC_250M_AD9510_RAW_SPI_OFFS 0x0300
#define FMC_250M_SI571_RAW_I2C_OFFS 0x0400
#define FMC_250M_EEPROM_RAW_I2C_OFFS 0x0500
/* DSP Components */
#define DSP_CTRL_RAW_REGS_OFFS 0x0000
#define DSP_BPM_RAW_SWAP_OFFS 0x0100
......@@ -44,6 +53,21 @@
#define FMC1_130M_LM75A_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define FMC1_250M_BASE_RAW_ADDR 0x00310000
#define FMC1_250M_CTRL_RAW_REGS (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC1_250M_AMC7823_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC1_250M_ISLA216P_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC1_250M_AD9510_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC1_250M_SI571_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC1_250M_EEPROM_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_EEPROM_RAW_I2C_OFFS)
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
......@@ -66,6 +90,21 @@
#define FMC2_130M_LM75A_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define FMC2_250M_BASE_RAW_ADDR 0x00350000
#define FMC2_250M_CTRL_RAW_REGS (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC2_250M_AMC7823_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC2_250M_ISLA216P_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC2_250M_AD9510_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC2_250M_SI571_RAW_I2C (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC2_250M_EEPROM_RAW_I2C (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_EEPROM_RAW_I2C_OFFS)
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
......@@ -113,6 +152,14 @@
#define FMC_130M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (BAR4_ADDR | FMC_130M_LM75A_RAW_I2C_OFFS)
/* FMC_250M Components */
#define FMC_250M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC_250M_AMC7823_SPI_OFFS (BAR4_ADDR | FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC_250M_ISLA216P_SPI_OFFS (BAR4_ADDR | FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC_250M_AD9510_SPI_OFFS (BAR4_ADDR | FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC_250M_SI571_I2C_OFFS (BAR4_ADDR | FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC_250M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_250M_EEPROM_RAW_I2C_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (BAR4_ADDR | DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (BAR4_ADDR | DSP_BPM_RAW_SWAP_OFFS)
......@@ -129,6 +176,15 @@
#define FMC1_130M_EEPROM_I2C (BAR4_ADDR | FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (BAR4_ADDR | FMC1_130M_LM75A_RAW_I2C)
#define FMC1_250M_BASE_ADDR (BAR4_ADDR | FMC1_250M_BASE_RAW_ADDR)
#define FMC1_250M_CTRL_REGS (BAR4_ADDR | FMC1_250M_CTRL_RAW_REGS)
#define FMC1_250M_AMC7823_SPI (BAR4_ADDR | FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (BAR4_ADDR | FMC1_250M_ISLA216P_RAW_SPI)
#define FMC1_250M_AD9510_SPI (BAR4_ADDR | FMC1_250M_AD9510_RAW_SPI)
#define FMC1_250M_SI571_I2C (BAR4_ADDR | FMC1_250M_SI571_RAW_I2C)
#define FMC1_250M_EEPROM_I2C (BAR4_ADDR | FMC1_250M_EEPROM_RAW_I2C)
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
......@@ -144,6 +200,15 @@
#define FMC2_130M_EEPROM_I2C (BAR4_ADDR | FMC2_130M_EEPROM_RAW_I2C)
#define FMC2_130M_LM75A_I2C (BAR4_ADDR | FMC2_130M_LM75A_RAW_I2C)
#define FMC2_250M_BASE_ADDR (BAR4_ADDR | FMC2_250M_BASE_RAW_ADDR)
#define FMC2_250M_CTRL_REGS (BAR4_ADDR | FMC2_250M_CTRL_RAW_REGS)
#define FMC2_250M_AMC7823_SPI (BAR4_ADDR | FMC2_250M_AMC7823_RAW_SPI)
#define FMC2_250M_ISLA216P_SPI (BAR4_ADDR | FMC2_250M_ISLA216P_RAW_SPI)
#define FMC2_250M_AD9510_SPI (BAR4_ADDR | FMC2_250M_AD9510_RAW_SPI)
#define FMC2_250M_SI571_I2C (BAR4_ADDR | FMC2_250M_SI571_RAW_I2C)
#define FMC2_250M_EEPROM_I2C (BAR4_ADDR | FMC2_250M_EEPROM_RAW_I2C)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
......@@ -174,6 +239,19 @@ extern const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A];
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
/********************* FMC250M_4CH SMIO Gateware Options ******************/
/* Chip SPI slave select lines and I2C address */
#define NUM_FMC250M_4CH_ISLA216P 4
extern const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_isla216p_addr[NUM_FMC250M_4CH_SMIOS][NUM_FMC250M_4CH_ISLA216P];
extern const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_pca9547_addr[NUM_FMC250M_4CH_SMIOS];
/*********************** SMIO ACQ Gateware Options ***********************/
/* FIXME: The Gateware does not support yet a way of reading which
* ACQ channels are valid. So, we hardcoded it here for now. This issue
......
include/boards/afcv3_1/chips_addr.h
View file @ 7590f635
......@@ -16,4 +16,14 @@ extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_isla216p_addr[NUM_FMC250M_4CH_SMIOS][NUM_FMC250M_4CH_ISLA216P];
extern const uint32_t fmc250m_4ch_pca9547_addr[NUM_FMC250M_4CH_SMIOS];
#endif
include/boards/afcv3_1/mem_layout.h
View file @ 7590f635
......@@ -9,6 +9,7 @@
#define NUM_MAX_BPMS (NUM_MAX_SLOTS * NUM_MAX_BPM_PER_SLOT)
#define NUM_FMC130M_4CH_SMIOS 2
#define NUM_FMC250M_4CH_SMIOS 2
/*********************** Static AFCv3 FPGA layout ***********************/
/* FMC_130M Components */
......@@ -18,6 +19,14 @@
#define FMC_130M_EEPROM_RAW_I2C_OFFS 0x0300
#define FMC_130M_LM75A_RAW_I2C_OFFS 0x0400
/* FMC_250M Components */
#define FMC_250M_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_250M_AMC7823_RAW_SPI_OFFS 0x0100
#define FMC_250M_ISLA216P_RAW_SPI_OFFS 0x0200
#define FMC_250M_AD9510_RAW_SPI_OFFS 0x0300
#define FMC_250M_SI571_RAW_I2C_OFFS 0x0400
#define FMC_250M_EEPROM_RAW_I2C_OFFS 0x0500
/* DSP Components */
#define DSP_CTRL_RAW_REGS_OFFS 0x0000
#define DSP_BPM_RAW_SWAP_OFFS 0x0100
......@@ -44,6 +53,21 @@
#define FMC1_130M_LM75A_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define FMC1_250M_BASE_RAW_ADDR 0x00310000
#define FMC1_250M_CTRL_RAW_REGS (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC1_250M_AMC7823_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC1_250M_ISLA216P_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC1_250M_AD9510_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC1_250M_SI571_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC1_250M_EEPROM_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_EEPROM_RAW_I2C_OFFS)
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
......@@ -66,6 +90,21 @@
#define FMC2_130M_LM75A_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define FMC2_250M_BASE_RAW_ADDR 0x00350000
#define FMC2_250M_CTRL_RAW_REGS (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC2_250M_AMC7823_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC2_250M_ISLA216P_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC2_250M_AD9510_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC2_250M_SI571_RAW_I2C (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC2_250M_EEPROM_RAW_I2C (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_EEPROM_RAW_I2C_OFFS)
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
......@@ -113,6 +152,14 @@
#define FMC_130M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (BAR4_ADDR | FMC_130M_LM75A_RAW_I2C_OFFS)
/* FMC_250M Components */
#define FMC_250M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC_250M_AMC7823_SPI_OFFS (BAR4_ADDR | FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC_250M_ISLA216P_SPI_OFFS (BAR4_ADDR | FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC_250M_AD9510_SPI_OFFS (BAR4_ADDR | FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC_250M_SI571_I2C_OFFS (BAR4_ADDR | FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC_250M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_250M_EEPROM_RAW_I2C_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (BAR4_ADDR | DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (BAR4_ADDR | DSP_BPM_RAW_SWAP_OFFS)
......@@ -129,6 +176,15 @@
#define FMC1_130M_EEPROM_I2C (BAR4_ADDR | FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (BAR4_ADDR | FMC1_130M_LM75A_RAW_I2C)
#define FMC1_250M_BASE_ADDR (BAR4_ADDR | FMC1_250M_BASE_RAW_ADDR)
#define FMC1_250M_CTRL_REGS (BAR4_ADDR | FMC1_250M_CTRL_RAW_REGS)
#define FMC1_250M_AMC7823_SPI (BAR4_ADDR | FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (BAR4_ADDR | FMC1_250M_ISLA216P_RAW_SPI)
#define FMC1_250M_AD9510_SPI (BAR4_ADDR | FMC1_250M_AD9510_RAW_SPI)
#define FMC1_250M_SI571_I2C (BAR4_ADDR | FMC1_250M_SI571_RAW_I2C)
#define FMC1_250M_EEPROM_I2C (BAR4_ADDR | FMC1_250M_EEPROM_RAW_I2C)
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
......@@ -144,6 +200,15 @@
#define FMC2_130M_EEPROM_I2C (BAR4_ADDR | FMC2_130M_EEPROM_RAW_I2C)
#define FMC2_130M_LM75A_I2C (BAR4_ADDR | FMC2_130M_LM75A_RAW_I2C)
#define FMC2_250M_BASE_ADDR (BAR4_ADDR | FMC2_250M_BASE_RAW_ADDR)
#define FMC2_250M_CTRL_REGS (BAR4_ADDR | FMC2_250M_CTRL_RAW_REGS)
#define FMC2_250M_AMC7823_SPI (BAR4_ADDR | FMC2_250M_AMC7823_RAW_SPI)
#define FMC2_250M_ISLA216P_SPI (BAR4_ADDR | FMC2_250M_ISLA216P_RAW_SPI)
#define FMC2_250M_AD9510_SPI (BAR4_ADDR | FMC2_250M_AD9510_RAW_SPI)
#define FMC2_250M_SI571_I2C (BAR4_ADDR | FMC2_250M_SI571_RAW_I2C)
#define FMC2_250M_EEPROM_I2C (BAR4_ADDR | FMC2_250M_EEPROM_RAW_I2C)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
......@@ -174,6 +239,19 @@ extern const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A];
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
/********************* FMC250M_4CH SMIO Gateware Options ******************/
/* Chip SPI slave select lines and I2C address */
#define NUM_FMC250M_4CH_ISLA216P 4
extern const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_isla216p_addr[NUM_FMC250M_4CH_SMIOS][NUM_FMC250M_4CH_ISLA216P];
extern const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_pca9547_addr[NUM_FMC250M_4CH_SMIOS];
/*********************** SMIO ACQ Gateware Options ***********************/
/* FIXME: The Gateware does not support yet a way of reading which
* ACQ channels are valid. So, we hardcoded it here for now. This issue
......
include/hw/wb_fmc250m_4ch_regs.h 0 → 100644
View file @ 7590f635
This diff is collapsed.
src/boards/afcv3/chips_addr.c
View file @ 7590f635
......@@ -7,6 +7,7 @@
#include "bpm_server.h"
/* FMC130M_4CH chip addresses */
const uint32_t fmc130m_4ch_si571_addr[NUM_FMC130M_4CH_SMIOS] = {0x49, 0x49};
const uint32_t fmc130m_4ch_ad9510_addr[NUM_FMC130M_4CH_SMIOS] = {0x01, 0x01};
......@@ -21,3 +22,19 @@ const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM7
/* This CI PCA9547 is located on the carrier, but it's controlled by the FMC130M_4CH */
const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS] = {0x70, 0x70};
/* FMC250M_4CH chip addresses */
const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS] = {0x49, 0x49};
const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS] = {0x01, 0x01};
/* The FMC EEPROM was supposed to have address 0x50 and 0x52, but GA1 and GA0
* are all grounded on hardware */
const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS] = {0x50, 0x50};
const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS] = {0x01, 0x01};
const uint32_t fmc250m_4ch_isla216p_addr[NUM_FMC250M_4CH_SMIOS][NUM_FMC250M_4CH_ISLA216P] = {
{0x01, 0x02, 0x03, 0x04},
{0x01, 0x02, 0x03, 0x04},
};
/* This CI PCA9547 is located on the carrier, but it's controlled by the FMC250M_4CH */
const uint32_t fmc250m_4ch_pca9547_addr[NUM_FMC250M_4CH_SMIOS] = {0x70, 0x70};
src/boards/afcv3_1/chips_addr.c
View file @ 7590f635
......@@ -19,3 +19,19 @@ const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM7
/* This CI PCA9547 is located on the carrier, but it's controlled by the FMC130M_4CH */
const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS] = {0x70, 0x70};
/* FMC250M_4CH chip addresses */
const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS] = {0x49, 0x49};
const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS] = {0x01, 0x01};
/* The FMC EEPROM was supposed to have address 0x50 and 0x52, but GA1 and GA0
* are all grounded on hardware */
const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS] = {0x50, 0x52};
const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS] = {0x01, 0x01};
const uint32_t fmc250m_4ch_isla216p_addr[NUM_FMC250M_4CH_SMIOS][NUM_FMC250M_4CH_ISLA216P] = {
{0x01, 0x02, 0x03, 0x04},
{0x01, 0x02, 0x03, 0x04},
};
/* This CI PCA9547 is located on the carrier, but it's controlled by the FMC250M_4CH */
const uint32_t fmc250m_4ch_pca9547_addr[NUM_FMC250M_4CH_SMIOS] = {0x70, 0x70};
src/sm_io/modules/fmc250m_4ch/fmc250m_4ch.mk 0 → 100644
View file @ 7590f635
sm_io_fmc250m_4ch_DIR = $(SRC_DIR)/sm_io/modules/fmc250m_4ch
sm_io_fmc250m_4ch_OBJS = $(sm_io_fmc250m_4ch_DIR)/sm_io_fmc250m_4ch_core.o \
$(sm_io_fmc250m_4ch_DIR)/sm_io_fmc250m_4ch_exp.o \
$(sm_io_fmc250m_4ch_DIR)/sm_io_fmc250m_4ch_exports.o \
$(sm_io_fmc250m_4ch_DIR)/sm_io_fmc250m_4ch_defaults.o
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_codes.h 0 → 100644
View file @ 7590f635
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC250M_4CH_CODES_H_
#define _SM_IO_FMC250M_4CH_CODES_H_
/* Messaging OPCODES */
#define FMC250M_4CH_OPCODE_TYPE uint32_t
#define FMC250M_4CH_OPCODE_SIZE (sizeof (FMC250M_4CH_OPCODE_TYPE))
#define FMC250M_4CH_OPCODE_LEDS 0
#define FMC250M_4CH_NAME_LEDS "fmc250m_4ch_leds"
#define FMC250M_4CH_OPCODE_SI571_OE 1
#define FMC250M_4CH_NAME_SI571_OE "fmc250m_4ch_si571_oe"
#define FMC250M_4CH_OPCODE_PLL_FUNCTION 2
#define FMC250M_4CH_NAME_PLL_FUNCTION "fmc250m_4ch_pll_function"
#define FMC250M_4CH_OPCODE_PLL_STATUS 3
#define FMC250M_4CH_NAME_PLL_STATUS "fmc250m_4ch_pll_status"
#define FMC250M_4CH_OPCODE_CLK_SEL 4
#define FMC250M_4CH_NAME_CLK_SEL "fmc250m_4ch_clk_sel"
#if 0
#define FMC250M_4CH_OPCODE_ADC_RAND 5
#define FMC250M_4CH_NAME_ADC_RAND "fmc250m_4ch_adc_rand"
#define FMC250M_4CH_OPCODE_ADC_DITH 6
#define FMC250M_4CH_NAME_ADC_DITH "fmc250m_4ch_adc_dith"
#define FMC250M_4CH_OPCODE_ADC_SHDN 7
#define FMC250M_4CH_NAME_ADC_SHDN "fmc250m_4ch_adc_shdn"
#define FMC250M_4CH_OPCODE_ADC_PGA 8
#define FMC250M_4CH_NAME_ADC_PGA "fmc250m_4ch_adc_pga"
#endif
#define FMC250M_4CH_OPCODE_ADC_DATA0 9
#define FMC250M_4CH_NAME_ADC_DATA0 "fmc250m_4ch_adc_data0"
#define FMC250M_4CH_OPCODE_ADC_DATA1 10
#define FMC250M_4CH_NAME_ADC_DATA1 "fmc250m_4ch_adc_data1"
#define FMC250M_4CH_OPCODE_ADC_DATA2 11
#define FMC250M_4CH_NAME_ADC_DATA2 "fmc250m_4ch_adc_data2"
#define FMC250M_4CH_OPCODE_ADC_DATA3 12
#define FMC250M_4CH_NAME_ADC_DATA3 "fmc250m_4ch_adc_data3"
#if 0
#define FMC250M_4CH_OPCODE_ADC_DLY_VAL0 13
#define FMC250M_4CH_NAME_ADC_DLY_VAL0 "fmc250m_4ch_adc_dly_val0"
#define FMC250M_4CH_OPCODE_ADC_DLY_VAL1 14
#define FMC250M_4CH_NAME_ADC_DLY_VAL1 "fmc250m_4ch_adc_dly_val1"
#define FMC250M_4CH_OPCODE_ADC_DLY_VAL2 15
#define FMC250M_4CH_NAME_ADC_DLY_VAL2 "fmc250m_4ch_adc_dly_val2"
#define FMC250M_4CH_OPCODE_ADC_DLY_VAL3 16
#define FMC250M_4CH_NAME_ADC_DLY_VAL3 "fmc250m_4ch_adc_dly_val3"
#define FMC250M_4CH_OPCODE_ADC_DLY_LINE0 17
#define FMC250M_4CH_NAME_ADC_DLY_LINE0 "fmc250m_4ch_adc_dly_line0"
#define FMC250M_4CH_OPCODE_ADC_DLY_LINE1 18
#define FMC250M_4CH_NAME_ADC_DLY_LINE1 "fmc250m_4ch_adc_dly_line1"
#define FMC250M_4CH_OPCODE_ADC_DLY_LINE2 19
#define FMC250M_4CH_NAME_ADC_DLY_LINE2 "fmc250m_4ch_adc_dly_line2"
#define FMC250M_4CH_OPCODE_ADC_DLY_LINE3 20
#define FMC250M_4CH_NAME_ADC_DLY_LINE3 "fmc250m_4ch_adc_dly_line3"
#define FMC250M_4CH_OPCODE_ADC_DLY_UPDT0 21
#define FMC250M_4CH_NAME_ADC_DLY_UPDT0 "fmc250m_4ch_adc_dly_updt0"
#define FMC250M_4CH_OPCODE_ADC_DLY_UPDT1 22
#define FMC250M_4CH_NAME_ADC_DLY_UPDT1 "fmc250m_4ch_adc_dly_updt1"
#define FMC250M_4CH_OPCODE_ADC_DLY_UPDT2 23
#define FMC250M_4CH_NAME_ADC_DLY_UPDT2 "fmc250m_4ch_adc_dly_updt2"
#define FMC250M_4CH_OPCODE_ADC_DLY_UPDT3 24
#define FMC250M_4CH_NAME_ADC_DLY_UPDT3 "fmc250m_4ch_adc_dly_updt3"
#define FMC250M_4CH_OPCODE_ADC_DLY0 25
#define FMC250M_4CH_NAME_ADC_DLY0 "fmc250m_4ch_adc_dly0"
#define FMC250M_4CH_OPCODE_ADC_DLY1 26
#define FMC250M_4CH_NAME_ADC_DLY1 "fmc250m_4ch_adc_dly1"
#define FMC250M_4CH_OPCODE_ADC_DLY2 27
#define FMC250M_4CH_NAME_ADC_DLY2 "fmc250m_4ch_adc_dly2"
#define FMC250M_4CH_OPCODE_ADC_DLY3 28
#define FMC250M_4CH_NAME_ADC_DLY3 "fmc250m_4ch_adc_dly3"
#endif
#define FMC250M_4CH_OPCODE_TEST_DATA_EN 29
#define FMC250M_4CH_NAME_TEST_DATA_EN "fmc250m_4ch_adc_test_data_en"
#define FMC250M_4CH_OPCODE_TRIG_DIR 30
#define FMC250M_4CH_NAME_TRIG_DIR "fmc250m_4ch_trig_dir"
#define FMC250M_4CH_OPCODE_TRIG_TERM 31
#define FMC250M_4CH_NAME_TRIG_TERM "fmc250m_4ch_trig_term"
#define FMC250M_4CH_OPCODE_TRIG_VAL 32
#define FMC250M_4CH_NAME_TRIG_VAL "fmc250m_4ch_trig_val"
#define FMC250M_4CH_OPCODE_AD9510_CFG_DEFAULTS 33
#define FMC250M_4CH_NAME_AD9510_CFG_DEFAULTS "fmc250m_4ch_ad9510_cfg_defaults"
#define FMC250M_4CH_OPCODE_AD9510_PLL_A_DIV 34
#define FMC250M_4CH_NAME_AD9510_PLL_A_DIV "fmc250m_4ch_ad9510_pll_a_div"
#define FMC250M_4CH_OPCODE_AD9510_PLL_B_DIV 35
#define FMC250M_4CH_NAME_AD9510_PLL_B_DIV "fmc250m_4ch_ad9510_pll_b_div"
#define FMC250M_4CH_OPCODE_AD9510_PLL_PRESCALER 36
#define FMC250M_4CH_NAME_AD9510_PLL_PRESCALER "fmc250m_4ch_ad9510_pll_prescaler"
#define FMC250M_4CH_OPCODE_AD9510_R_DIV 37
#define FMC250M_4CH_NAME_AD9510_R_DIV "fmc250m_4ch_ad9510_r_div"
#define FMC250M_4CH_OPCODE_AD9510_PLL_PDOWN 38
#define FMC250M_4CH_NAME_AD9510_PLL_PDOWN "fmc250m_4ch_ad9510_pll_pdown"
#define FMC250M_4CH_OPCODE_AD9510_MUX_STATUS 39
#define FMC250M_4CH_NAME_AD9510_MUX_STATUS "fmc250m_4ch_ad9510_mux_status"
#define FMC250M_4CH_OPCODE_AD9510_CP_CURRENT 40
#define FMC250M_4CH_NAME_AD9510_CP_CURRENT "fmc250m_4ch_ad9510_cp_current"
#define FMC250M_4CH_OPCODE_AD9510_OUTPUTS 41
#define FMC250M_4CH_NAME_AD9510_OUTPUTS "fmc250m_4ch_ad9510_outputs"
#define FMC250M_4CH_OPCODE_AD9510_PLL_CLK_SEL 42
#define FMC250M_4CH_NAME_AD9510_PLL_CLK_SEL "fmc250m_4ch_ad9510_pll_clk_sel"
#define FMC250M_4CH_OPCODE_SI571_SET_FREQ 43
#define FMC250M_4CH_NAME_SI571_SET_FREQ "fmc250m_4ch_si571_set_freq"
#define FMC250M_4CH_OPCODE_SI571_GET_DEFAULTS 44
#define FMC250M_4CH_NAME_SI571_GET_DEFAULTS "fmc250m_4ch_si571_get_defaults"
#define FMC250M_4CH_OPCODE_END 45
/* Messaging Reply OPCODES */
#define FMC250M_4CH_REPLY_TYPE uint32_t
#define FMC250M_4CH_REPLY_SIZE (sizeof (FMC250M_4CH_REPLY_TYPE))
#define FMC250M_4CH_OK 0 /* Operation was successful */
#define FMC250M_4CH_ERR 1 /* Could not set/get value */
#define FMC250M_4CH_UNINPL 2 /* Unimplemented function or operation */
#define FMC250M_4CH_REPLY_END 3 /* End marker */
#endif
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_core.c 0 → 100644
View file @ 7590f635
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_fmc250m_4ch_defaults.h"
#include "sm_io_fmc250m_4ch_core.h"
#include "chips_addr.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_fmc250m_4ch_core]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_fmc250m_4ch_core]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io_fmc250m_4ch_core]", \
smio_err_str (err_type))
static smio_err_e _smio_fmc250m_4ch_set_type (smio_fmc250m_4ch_t *self,
uint32_t type_code);
/* Creates a new instance of Device Information */
smio_fmc250m_4ch_t * smio_fmc250m_4ch_new (smio_t *parent)
{
assert (parent);
smio_fmc250m_4ch_t *self = (smio_fmc250m_4ch_t *) zmalloc (sizeof *self);
ASSERT_ALLOC(self, err_self_alloc);
uint32_t inst_id = smio_get_inst_id (parent);
/* Check if Instance ID is within our expected limits */
ASSERT_TEST(inst_id < NUM_FMC250M_4CH_SMIOS, "Number of FMC250M_4CH SMIOs instances exceeded",
err_num_fmc250m_4ch_smios);
/* FMC250M_4CH isntance 0 is the one controlling this CI */
/* FIXME: This breaks generality for this class */
if (inst_id == 0) {
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] PCA9547 initializing, "
" addr: 0x%08X, Inst ID: %u\n", fmc250m_4ch_pca9547_addr[inst_id],
inst_id);
/* FPGA I2C Switch */
self->smch_pca9547 = smch_pca9547_new (parent, FMC_250M_EEPROM_I2C_OFFS,
fmc250m_4ch_pca9547_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_pca9547, err_smch_pca9547_alloc);
/* Enable default I2C channel */
smch_pca9547_en_chan (self->smch_pca9547, FMC250M_4CH_DFLT_PCA9547_CFG);
}
else {
self->smch_pca9547 = NULL;
}
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] 24AA64 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc250m_4ch_24aa64_addr[inst_id],
inst_id);
/* EEPROM is on the same I2C bus as the LM75A */
self->smch_24aa64 = smch_24aa64_new (parent, FMC_250M_EEPROM_I2C_OFFS,
fmc250m_4ch_24aa64_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_24aa64, err_smch_24aa64_alloc);
uint32_t data_24aa64;
#ifdef __FMC250M_4CH_EEPROM_PROGRAM__
#if __FMC250M_4CH_EEPROM_PROGRAM__==1
data_24aa64 = FMC250M_4CH_ACTIVE_MD5;
#elif __FMC250M_4CH_EEPROM_PROGRAM__==2
data_24aa64 = FMC250M_4CH_PASSIVE_MD5;
#else
#error "Unsupported FMC250M_4CH program value. Valid values are \"1\" and\"2\""
#endif
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:fmc250m_4ch_core] Writing 0x%08X to EEPROM\n",
data_24aa64);
smch_24aa64_write_block (self->smch_24aa64, FMC250M_4CH_EEPROM_START_ADDR,
&data_24aa64, sizeof (data_24aa64));
/* Readback test */
uint32_t data_24aa64_rb;
smch_24aa64_read_block (self->smch_24aa64, FMC250M_4CH_EEPROM_START_ADDR,
&data_24aa64_rb, sizeof (data_24aa64_rb));
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO,
"[sm_io:fmc250m_4ch_core] 24AA64 readback: 0x%08X\n", data_24aa64_rb);
ASSERT_TEST(data_24aa64_rb == data_24aa64, "[sm_io:fmc250m_4ch_core] EEPROM 24AA64 readback failed",
err_smch_ad9510_alloc);
#endif
/* Read EEPROM */
data_24aa64 = 0x0;
smch_24aa64_read_block (self->smch_24aa64, FMC250M_4CH_EEPROM_START_ADDR,
&data_24aa64, sizeof (data_24aa64));
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO,
"[sm_io:fmc250m_4ch_core] EEPROM 24AA64 data: 0x%08X\n", data_24aa64);
/* Determine the type of the FMC250M_4CH board */
_smio_fmc250m_4ch_set_type (self, data_24aa64);
/* Now, initialize the FMC250M_4CH with the appropriate structures*/
if (self->type == TYPE_FMC250M_4CH_ACTIVE) {
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] AD9510 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc250m_4ch_ad9510_addr[inst_id],
inst_id);
self->smch_ad9510 = smch_ad9510_new (parent, FMC_250M_AD9510_SPI_OFFS,
fmc250m_4ch_ad9510_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_ad9510, err_smch_ad9510_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] SI571 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc250m_4ch_si571_addr[inst_id],
inst_id);
self->smch_si571 = smch_si57x_new (parent, FMC_250M_SI571_I2C_OFFS,
fmc250m_4ch_si571_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_si571, err_smch_si571_alloc);
}
else { /* PASSIVE or Unsupported*/
if (self->type != TYPE_FMC250M_4CH_PASSIVE) {
DBE_DEBUG (DBG_SM_IO | DBG_LVL_WARN,
"[sm_io:fmc250m_4ch_core] Unsupported FMC250M_4CH card (maybe EEPROM not configured?).\n"
"\t Defaulting to PASSIVE board\n");
}
self->smch_ad9510 = NULL;
self->smch_si571 = NULL;
}
return self;
err_smch_si571_alloc:
if (self->smch_ad9510 != NULL) {
smch_ad9510_destroy (&self->smch_ad9510);
}
err_smch_ad9510_alloc:
smch_24aa64_destroy (&self->smch_24aa64);
err_smch_24aa64_alloc:
if (self->smch_pca9547 != NULL) {
smch_pca9547_destroy (&self->smch_pca9547);
}
err_smch_pca9547_alloc:
err_num_fmc250m_4ch_smios:
free (self);
err_self_alloc:
return NULL;
}
/* Destroy an instance of the Device Information */
smio_err_e smio_fmc250m_4ch_destroy (smio_fmc250m_4ch_t **self_p)
{
assert (self_p);
if (*self_p) {
smio_fmc250m_4ch_t *self = *self_p;
smch_si57x_destroy (&self->smch_si571);
smch_ad9510_destroy (&self->smch_ad9510);
smch_24aa64_destroy (&self->smch_24aa64);
if (self->smch_pca9547 != NULL) {
smch_pca9547_destroy (&self->smch_pca9547);
}
free (self);
*self_p = NULL;
}
return SMIO_SUCCESS;
}
static smio_err_e _smio_fmc250m_4ch_set_type (smio_fmc250m_4ch_t *self,
uint32_t type_code)
{
assert (self);
smio_err_e err = SMIO_SUCCESS;
fmc250m_4ch_type_e type = TYPE_FMC250M_4CH_UNDEF;
switch (type_code) {
case FMC250M_4CH_ACTIVE_MD5:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO,
"[sm_io:fmc250m_4ch_core] Found Active FMC250M_4CH board\n");
type = TYPE_FMC250M_4CH_ACTIVE;
break;
case FMC250M_4CH_PASSIVE_MD5:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO,
"[sm_io:fmc250m_4ch_core] Found Passive FMC250M_4CH board\n");
type = TYPE_FMC250M_4CH_PASSIVE;
break;
default:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO,
"[sm_io:fmc250m_4ch_core] Found Undefined FMC250M_4CH board\n");
err = SMIO_ERR_WRONG_PARAM;
type = TYPE_FMC250M_4CH_UNDEF;
}
self->type = type;
return err;
}
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_core.h 0 → 100644
View file @ 7590f635
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC250M_4CH_CORE_H_
#define _SM_IO_FMC250M_4CH_CORE_H_
#define SMIO_AD9510_HANDLER(smio_handler) ((smch_ad9510_t *) smio_handler->smch_ad9510)
#define SMIO_SI57X_HANDLER(smio_handler) ((smch_si57x_t *) smio_handler->smch_si571)
/* The follosing codes were generated via the following command:
* > echo FMC250M_4CH_ACTIVE | md5sum | cut -c 1-8
* > cb04db4d
* > echo FMC250M_4CH_ACTIVE | md5sum | cut -c 1-8
* > 59da56ae
*/
#define FMC250M_4CH_ACTIVE_MD5 0x955393fc
#define FMC250M_4CH_PASSIVE_MD5 0xf9556611
/* Start writing on EEPROM address 0x0 */
#define FMC250M_4CH_EEPROM_START_ADDR 0x0
typedef enum {
TYPE_FMC250M_4CH_UNDEF=0xFF,
TYPE_FMC250M_4CH_ACTIVE=1,
TYPE_FMC250M_4CH_PASSIVE
} fmc250m_4ch_type_e;
typedef struct {
fmc250m_4ch_type_e type; /* FMC250M_4CH type */
#if 0
smch_amc7823_t *smch_amc7823; /* AMC7823 chip handler */
smch_isla216p_t *smch_isla216p; /* ISLA216P chip handler */
#endif
smch_ad9510_t *smch_ad9510; /* AD9510 chip handler */
smch_si57x_t *smch_si571; /* SI571 chip handler */
smch_24aa64_t *smch_24aa64; /* 24AA64 chip handler */
smch_pca9547_t *smch_pca9547; /* FPGA I2C Switch */
} smio_fmc250m_4ch_t;
/* FPGA FMC250M delay definitions */
#define DLY_TYPE_DATA 0x01
#define DLY_TYPE_CLK 0x02
#define DLY_TYPE_ALL (DLY_TYPE_DATA | DLY_TYPE_CLK)
typedef enum {
DLY_INIT_NO = 0,
DLY_INIT_YES,
DLY_INIT_END /* Placeholder for end of struct */
} fmc250m_4ch_delay_init_e;
/* Holds the delay value for each channel */
typedef struct {
fmc250m_4ch_delay_init_e init;
uint32_t value;
} delay_lines_t;
/***************** Our methods *****************/
/* Creates a new instance of the smio realization */
smio_fmc250m_4ch_t * smio_fmc250m_4ch_new (smio_t *parent);
/* Destroys the smio realization */
smio_err_e smio_fmc250m_4ch_destroy (smio_fmc250m_4ch_t **self_p);
#endif
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.c 0 → 100644
View file @ 7590f635
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_fmc250m_4ch_defaults.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:fmc250m_4ch_defaults]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:fmc250m_4ch_defaults]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io:fmc250m_4ch_defaults]", \
smio_err_str (err_type))
#define SMIO_FMC250M_4CH_LIBBPMCLIENT_LOG_MODE "a"
/* We use the actual libclient to send and configure our default values,
* maintaining internal consistency. So, in fact, we are sending ourselves
* a message containing the default values. Because of this approach, we
* only get to default our values when the functions are already exported
* to the broker, which happens on a late stage. This could cause a fast
* client to get an inconsistent state from our server */
/* TODO: Avoid exporting the functions before we have initialized
* our server with the default values */
smio_err_e fmc250m_4ch_config_defaults (char *broker_endp, char *service,
const char *log_file_name)
{
(void) log_file_name;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:fmc250m_4ch_defaults] Configuring SMIO "
"FMC250M_4CH with default values ...\n");
bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
smio_err_e err = SMIO_SUCCESS;
bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
log_file_name, SMIO_FMC250M_4CH_LIBBPMCLIENT_LOG_MODE);
ASSERT_ALLOC(config_client, err_alloc_client);
client_err = bpm_set_fmc_pll_function (config_client, service, FMC250M_4CH_DFLT_PLL_FUNC);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC PLL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_fmc_clk_sel (config_client, service, FMC250M_4CH_DFLT_CLK_SEL);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC CLK SEL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_trig_dir (config_client, service, FMC250M_4CH_DFLT_TRIG_DIR);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC TRIG DIR function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_ad9510_cfg_defaults (config_client, service, 0);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS ||
client_err == BPM_CLIENT_ERR_AGAIN, "Could not configure AD9510",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_defaults (config_client, service, FMC250M_4CH_DFLT_SI57X_FOUT_FACTORY);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not get Si571 defaults",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_set_freq (config_client, service, FMC250M_4CH_DFLT_SI57X_FOUT);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set Si571 frequency",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_oe (config_client, service, FMC250M_4CH_DFLT_SI571_OE);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not enable SI571 Output",
err_param_set, SMIO_ERR_CONFIG_DFLT);
err_param_set:
bpm_client_destroy (&config_client);
err_alloc_client:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:fmc250m_4ch_defaults] Exiting Config thread %s\n",
service);
return err;
}
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.h 0 → 100644
View file @ 7590f635
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _FMC250M_4CH_DEFAULTS_H_
#define _FMC250M_4CH_DEFAULTS_H_
#include "sm_io_err.h"
#include "chips/si57x_regs.h"
#include "sm_ch_pca9547.h"
#define FMC250M_4CH_DFLT_PLL_FUNC 0x1
#define FMC250M_4CH_DFLT_CLK_SEL 0x0 /* Clock from FMC front panel */
#define FMC250M_4CH_DFLT_TRIG_DIR 0x0 /* Output direction */
#define FMC250M_4CH_DFLT_PCA9547_CFG SMCH_PCA9547_NO_CHANNEL /* No channel selected */
#define FMC250M_4CH_DFLT_SI571_OE 0x1
#define FMC250M_4CH_DFLT_SI57X_FOUT_FACTORY SI57X_FOUT_FACTORY_DFLT
#define FMC250M_4CH_DFLT_SI57X_FOUT 113040445 /* 113.040445 MHz default */
smio_err_e fmc250m_4ch_config_defaults (char *broker_endp, char *service,
const char *log_file_name);
#endif
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exp.c 0 → 100644
View file @ 7590f635
This diff is collapsed.
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exp.h 0 → 100644
View file @ 7590f635
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _FMC250M_4CH_H_
#define _FMC250M_4CH_H_
/* Known modules IDs (from SDB records defined in FPGA) */
#define FMC250M_4CH_SDB_DEVID 0x68e3b1af
#define FMC250M_4CH_SDB_NAME "FMC250M_4CH"
extern const smio_bootstrap_ops_t fmc250m_4ch_bootstrap_ops;
#endif
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exports.c 0 → 100644
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This diff is collapsed.
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exports.h 0 → 100644
View file @ 7590f635
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC250M_4CH_EXPORTS_H_
#define _SM_IO_FMC250M_4CH_EXPORTS_H_
#include "disptable.h"
extern disp_op_t fmc250m_4ch_leds_exp;
extern disp_op_t fmc250m_4ch_si571_oe_exp;
extern disp_op_t fmc250m_4ch_pll_func_exp;
extern disp_op_t fmc250m_4ch_pll_status_exp;
extern disp_op_t fmc250m_4ch_clk_sel_exp;
#if 0
extern disp_op_t fmc250m_4ch_adc_rand_exp;
extern disp_op_t fmc250m_4ch_adc_dith_exp;
extern disp_op_t fmc250m_4ch_adc_shdn_exp;
extern disp_op_t fmc250m_4ch_adc_pga_exp;
#endif
extern disp_op_t fmc250m_4ch_adc_data0_exp;
extern disp_op_t fmc250m_4ch_adc_data1_exp;
extern disp_op_t fmc250m_4ch_adc_data2_exp;
extern disp_op_t fmc250m_4ch_adc_data3_exp;
#if 0
extern disp_op_t fmc250m_4ch_adc_dly_val0_exp;
extern disp_op_t fmc250m_4ch_adc_dly_val1_exp;
extern disp_op_t fmc250m_4ch_adc_dly_val2_exp;
extern disp_op_t fmc250m_4ch_adc_dly_val3_exp;
extern disp_op_t fmc250m_4ch_adc_dly_line0_exp;
extern disp_op_t fmc250m_4ch_adc_dly_line1_exp;
extern disp_op_t fmc250m_4ch_adc_dly_line2_exp;
extern disp_op_t fmc250m_4ch_adc_dly_line3_exp;
extern disp_op_t fmc250m_4ch_adc_dly_updt0_exp;
extern disp_op_t fmc250m_4ch_adc_dly_updt1_exp;
extern disp_op_t fmc250m_4ch_adc_dly_updt2_exp;
extern disp_op_t fmc250m_4ch_adc_dly_updt3_exp;
extern disp_op_t fmc250m_4ch_adc_dly0_exp;
extern disp_op_t fmc250m_4ch_adc_dly1_exp;
extern disp_op_t fmc250m_4ch_adc_dly2_exp;
extern disp_op_t fmc250m_4ch_adc_dly3_exp;
#endif
extern disp_op_t fmc250m_4ch_test_data_en_exp;
extern disp_op_t fmc250m_4ch_trig_dir_exp;
extern disp_op_t fmc250m_4ch_trig_term_exp;
extern disp_op_t fmc250m_4ch_trig_val_exp;
extern disp_op_t fmc250m_4ch_ad9510_cfg_defaults_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_a_div_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_b_div_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_prescaler_exp;
extern disp_op_t fmc250m_4ch_ad9510_r_div_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_pdown_exp;
extern disp_op_t fmc250m_4ch_ad9510_mux_status_exp;
extern disp_op_t fmc250m_4ch_ad9510_cp_current_exp;
extern disp_op_t fmc250m_4ch_ad9510_outputs_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_clk_sel_exp;
extern disp_op_t fmc250m_4ch_si571_set_freq_exp;
extern disp_op_t fmc250m_4ch_si571_get_defaults_exp;
extern const disp_op_t *fmc250m_4ch_exp_ops [];
#endif
src/sm_io/modules/modules.mk
View file @ 7590f635
include $(SRC_DIR)/sm_io/modules/fmc130m_4ch/fmc130m_4ch.mk \
$(SRC_DIR)/sm_io/modules/fmc250m_4ch/fmc250m_4ch.mk \
$(SRC_DIR)/sm_io/modules/acq/acq.mk \
$(SRC_DIR)/sm_io/modules/dsp/dsp.mk \
$(SRC_DIR)/sm_io/modules/swap/swap.mk \
......@@ -9,6 +10,7 @@ sm_io_modules_DIR = $(SRC_DIR)/sm_io/modules
sm_io_modules_OBJS = $(sm_io_modules_DIR)/sm_io_codes.o \
$(sm_io_fmc130m_4ch_OBJS) \
$(sm_io_fmc250m_4ch_OBJS) \
$(sm_io_acq_OBJS) \
$(sm_io_dsp_OBJS) \
$(sm_io_swap_OBJS) \
......
src/sm_io/modules/sm_io_codes.c
View file @ 7590f635
......@@ -11,6 +11,7 @@ const disp_op_t **smio_exp_ops [] = {
acq_exp_ops,
dsp_exp_ops,
fmc130m_4ch_exp_ops,
fmc250m_4ch_exp_ops,
swap_exp_ops,
rffe_exp_ops,
afc_diag_exp_ops,
......
src/sm_io/modules/sm_io_codes.h
View file @ 7590f635
......@@ -23,6 +23,7 @@ typedef struct _smio_rffe_version_t smio_rffe_version_t;
/* Include all module's codes */
#include "sm_io_fmc130m_4ch_codes.h"
#include "sm_io_fmc250m_4ch_codes.h"
#include "sm_io_acq_codes.h"
#include "sm_io_dsp_codes.h"
#include "sm_io_swap_codes.h"
......@@ -31,6 +32,7 @@ typedef struct _smio_rffe_version_t smio_rffe_version_t;
/* Include all function descriptors */
#include "sm_io_fmc130m_4ch_exports.h"
#include "sm_io_fmc250m_4ch_exports.h"
#include "sm_io_acq_exports.h"
#include "sm_io_dsp_exports.h"
#include "sm_io_swap_exports.h"
......
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