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Beam Positoning Monitor - Software
Commit 7a721199 authored by Lucas Russo's avatar Lucas Russo
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include/hw/wb_acq_core_regs.h: add trigger reg/fields

parent eeb4224a
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include/hw/wb_acq_core_regs.h
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......@@ -3,7 +3,7 @@
* File : wb_acq_core_regs.h
* Author : auto-generated by wbgen2 from acq_core.wb
* Created : Fri May 16 20:02:39 2014
* Created : Tue Sep 8 19:12:36 2015
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
......@@ -115,16 +115,26 @@
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Reserved in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(6, 26)
#define ACQ_CORE_TRIG_CFG_RESERVED_SHIFT 6
#define ACQ_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 26)
#define ACQ_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 26)
/* definitions for field: Threshold for internal trigger in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_SHIFT 16
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Trigger data config threshold */
/* definitions for field: Internal trigger threshold glitch filter in reg: Trigger data config threshold */
#define ACQ_CORE_TRIG_DATA_CFG_THRES_FILT_MASK WBGEN2_GEN_MASK(0, 8)
#define ACQ_CORE_TRIG_DATA_CFG_THRES_FILT_SHIFT 0
#define ACQ_CORE_TRIG_DATA_CFG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define ACQ_CORE_TRIG_DATA_CFG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Reserved in reg: Trigger data config threshold */
#define ACQ_CORE_TRIG_DATA_CFG_RESERVED_MASK WBGEN2_GEN_MASK(8, 24)
#define ACQ_CORE_TRIG_DATA_CFG_RESERVED_SHIFT 8
#define ACQ_CORE_TRIG_DATA_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define ACQ_CORE_TRIG_DATA_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: Trigger data threshold */
/* definitions for register: Trigger delay */
......@@ -154,6 +164,8 @@
/* definitions for register: DDR3 Start Address */
/* definitions for register: DDR3 End Address */
/* definitions for register: Acquisition channel control */
/* definitions for field: Acquisition channel selection in reg: Acquisition channel control */
......@@ -161,29 +173,35 @@
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_SHIFT 0
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* FIXME: The FPGA firmware is WORD addressed for now */
/* FIXME: The FPGA firmware is BYTE/WORD addressed depending on the board */
/* [0x0]: REG Control register */
#define ACQ_CORE_REG_CTL (0x00000000 >> __WR_SHIFT_FIX__)
/* [0x4]: REG Status register */
#define ACQ_CORE_REG_STA (0x00000004 >> __WR_SHIFT_FIX__)
/* [0x8]: REG Trigger configuration */
#define ACQ_CORE_REG_TRIG_CFG (0x00000008 >> __WR_SHIFT_FIX__)
/* [0xc]: REG Trigger delay */
#define ACQ_CORE_REG_TRIG_DLY (0x0000000c >> __WR_SHIFT_FIX__)
/* [0x10]: REG Software trigger */
#define ACQ_CORE_REG_SW_TRIG (0x00000010 >> __WR_SHIFT_FIX__)
/* [0x14]: REG Number of shots */
#define ACQ_CORE_REG_SHOTS (0x00000014 >> __WR_SHIFT_FIX__)
/* [0x18]: REG Trigger address register */
#define ACQ_CORE_REG_TRIG_POS (0x00000018 >> __WR_SHIFT_FIX__)
/* [0x1c]: REG Pre-trigger samples */
#define ACQ_CORE_REG_PRE_SAMPLES (0x0000001c >> __WR_SHIFT_FIX__)
/* [0x20]: REG Post-trigger samples */
#define ACQ_CORE_REG_POST_SAMPLES (0x00000020 >> __WR_SHIFT_FIX__)
/* [0x24]: REG Samples counter */
#define ACQ_CORE_REG_SAMPLES_CNT (0x00000024 >> __WR_SHIFT_FIX__)
/* [0x28]: REG DDR3 Start Address */
#define ACQ_CORE_REG_DDR3_START_ADDR (0x00000028 >> __WR_SHIFT_FIX__)
/* [0x2c]: REG Acquisition channel control */
#define ACQ_CORE_REG_ACQ_CHAN_CTL (0x0000002c >> __WR_SHIFT_FIX__)
/* [0xc]: REG Trigger data config threshold */
#define ACQ_CORE_REG_TRIG_DATA_CFG (0x0000000c >> __WR_SHIFT_FIX__)
/* [0x10]: REG Trigger data threshold */
#define ACQ_CORE_REG_TRIG_DATA_THRES (0x00000010 >> __WR_SHIFT_FIX__)
/* [0x14]: REG Trigger delay */
#define ACQ_CORE_REG_TRIG_DLY (0x00000014 >> __WR_SHIFT_FIX__)
/* [0x18]: REG Software trigger */
#define ACQ_CORE_REG_SW_TRIG (0x00000018 >> __WR_SHIFT_FIX__)
/* [0x1c]: REG Number of shots */
#define ACQ_CORE_REG_SHOTS (0x0000001c >> __WR_SHIFT_FIX__)
/* [0x20]: REG Trigger address register */
#define ACQ_CORE_REG_TRIG_POS (0x00000020 >> __WR_SHIFT_FIX__)
/* [0x24]: REG Pre-trigger samples */
#define ACQ_CORE_REG_PRE_SAMPLES (0x00000024 >> __WR_SHIFT_FIX__)
/* [0x28]: REG Post-trigger samples */
#define ACQ_CORE_REG_POST_SAMPLES (0x00000028 >> __WR_SHIFT_FIX__)
/* [0x2c]: REG Samples counter */
#define ACQ_CORE_REG_SAMPLES_CNT (0x0000002c >> __WR_SHIFT_FIX__)
/* [0x30]: REG DDR3 Start Address */
#define ACQ_CORE_REG_DDR3_START_ADDR (0x00000030 >> __WR_SHIFT_FIX__)
/* [0x34]: REG DDR3 End Address */
#define ACQ_CORE_REG_DDR3_END_ADDR (0x00000034 >> __WR_SHIFT_FIX__)
/* [0x38]: REG Acquisition channel control */
#define ACQ_CORE_REG_ACQ_CHAN_CTL (0x00000038 >> __WR_SHIFT_FIX__)
#endif
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