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Beam Positoning Monitor - Software
Commit 84b2c397 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'smio-fmcs-split' into devel 

This fixes #115 github issue

Note that this requires at least
lnls-dig/bpm-gw@27a4af84b1
parents fa4c67c1 3c94f273
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Showing with 2574 additions and 2223 deletions
Makefile
View file @ 84b2c397
......@@ -217,6 +217,7 @@ include $(SRC_DIR)/dev_io/dev_io.mk
include $(SRC_DIR)/msg/msg.mk
include $(SRC_DIR)/revision/revision.mk
include $(SRC_DIR)/boards/$(BOARD)/board.mk
include $(SRC_DIR)/boards/common/common.mk
include $(APPS_MKS)
# Project boards
......@@ -249,7 +250,8 @@ dev_mngr_OBJS += $(dev_mngr_core_OBJS) $(debug_OBJS) \
$(ll_io_utils_OBJS) $(dev_io_core_utils_OBJS)
common_app_OBJS = $(dev_io_core_OBJS) $(ll_io_OBJS) \
$(sm_io_OBJS) $(msg_OBJS) $(board_OBJS)
$(sm_io_OBJS) $(msg_OBJS) $(board_OBJS) \
$(board_common_OBJS)
apps_OBJS = $(foreach app_obj,$(APPS),$($(app_obj)_all_OBJS))
......@@ -266,6 +268,7 @@ OBJS_all = $(ll_io_OBJS) \
$(dev_mngr_OBJS) \
$(common_app_OBJS) \
$(apps_OBJS) \
$(board_common_OBJS) \
$(revision_OBJS)
# Sources
......
examples/ad9510_ctl.c
View file @ 84b2c397
......@@ -202,7 +202,7 @@ int main (int argc, char *argv [])
}
char service[50];
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC130M_4CH%u", board_number, bpm_number);
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC_ACTIVE_CLK%u", board_number, bpm_number);
bpm_client_t *bpm_client = bpm_client_new (broker_endp, verbose, NULL);
if (bpm_client == NULL) {
......
examples/leds.c
View file @ 84b2c397
......@@ -100,7 +100,7 @@ int main (int argc, char *argv [])
}
char service[50];
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC130M_4CH%u", board_number, bpm_number);
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC_ADC_COMMON%u", board_number, bpm_number);
bpm_client_t *bpm_client = bpm_client_new (broker_endp, verbose, NULL);
if (bpm_client == NULL) {
......
examples/si571_ctl.c
View file @ 84b2c397
......@@ -127,7 +127,7 @@ int main (int argc, char *argv [])
}
char service[50];
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC130M_4CH%u", board_number, bpm_number);
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC_ACTIVE_CLK%u", board_number, bpm_number);
bpm_client_t *bpm_client = bpm_client_new (broker_endp, verbose, NULL);
if (bpm_client == NULL) {
......
examples/test_data_en.c
View file @ 84b2c397
......@@ -125,7 +125,7 @@ int main (int argc, char *argv [])
fprintf (stdout, "[client:test_data_en]: test_data_en = %u\n", test_data_en);
char service[50];
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC130M_4CH%u", board_number, bpm_number);
snprintf (service, sizeof (service), "BPM%u:DEVIO:FMC_ADC_COMMON%u", board_number, bpm_number);
bpm_client_t *bpm_client = bpm_client_new (broker_endp, verbose, NULL);
if (bpm_client == NULL) {
......
include/boards/afcv3/chips_addr.h
View file @ 84b2c397
......@@ -8,17 +8,11 @@
#ifndef _CHIPS_ADDR_H_
#define _CHIPS_ADDR_H_
extern const uint32_t fmc130m_4ch_si571_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_ad9510_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A];
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS];
......
include/boards/afcv3/mem_layout.h
View file @ 84b2c397
This diff is collapsed.
include/boards/afcv3_1/chips_addr.h
View file @ 84b2c397
......@@ -8,17 +8,11 @@
#ifndef _CHIPS_ADDR_H_
#define _CHIPS_ADDR_H_
extern const uint32_t fmc130m_4ch_si571_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_ad9510_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A];
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS];
......
include/boards/afcv3_1/mem_layout.h
View file @ 84b2c397
This diff is collapsed.
include/boards/ml605/chips_addr.h
View file @ 84b2c397
......@@ -8,17 +8,11 @@
#ifndef _CHIPS_ADDR_H_
#define _CHIPS_ADDR_H_
extern const uint32_t fmc130m_4ch_si571_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_ad9510_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A];
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_si571_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_ad9510_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_24aa64_addr[NUM_FMC250M_4CH_SMIOS];
extern const uint32_t fmc250m_4ch_amc7823_addr[NUM_FMC250M_4CH_SMIOS];
......
include/boards/ml605/mem_layout.h
View file @ 84b2c397
#ifndef _MEM_LAYOUT_H_
#define _MEM_LAYOUT_H_
#include "pcie_regs.h"
#include "mem_layout_common.h"
#include "acq_chan.h"
#define NUM_MAX_SLOTS 1
......@@ -12,31 +12,17 @@
#define NUM_FMC250M_4CH_SMIOS 1
/*********************** Static ML605 FPGA layout ***********************/
/* FMC_130M Components */
#define FMC_130M_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_130M_SI571_RAW_I2C_OFFS 0x0100
#define FMC_130M_AD9510_RAW_SPI_OFFS 0x0200
#define FMC_130M_EEPROM_RAW_I2C_OFFS 0x0300
#define FMC_130M_LM75A_RAW_I2C_OFFS 0x0400
/* FMC_250M Components */
#define FMC_250M_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_250M_AMC7823_RAW_SPI_OFFS 0x0100
#define FMC_250M_ISLA216P_RAW_SPI_OFFS 0x0200
#define FMC_250M_AD9510_RAW_SPI_OFFS 0x0300
#define FMC_250M_SI571_RAW_I2C_OFFS 0x0400
#define FMC_250M_EEPROM_RAW_I2C_OFFS 0x0500
/* DSP Components */
#define DSP_CTRL_RAW_REGS_OFFS 0x0000
#define DSP_BPM_RAW_SWAP_OFFS 0x0100
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_RAW_REGS_OFFS 0x0000
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define FMC1_130M_BASE_RAW_ADDR 0x00310000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
......@@ -65,13 +51,6 @@
#define FMC1_250M_EEPROM_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_EEPROM_RAW_I2C_OFFS)
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ1_BASE_RAW_ADDR 0x00330000
/* Large Memory RAW Addresses. It lives at address 0 */
......@@ -98,56 +77,31 @@
* the correct one to read or write
*/
/* FMC_130M Components */
#define FMC_130M_CTRL_REGS_OFFS (/*BAR4_ADDR |*/ FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC_130M_SI571_I2C_OFFS (/*BAR4_ADDR |*/ FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC_130M_AD9510_SPI_OFFS (/*BAR4_ADDR |*/ FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC_130M_EEPROM_I2C_OFFS (/*BAR4_ADDR |*/ FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (/*BAR4_ADDR |*/ FMC_130M_LM75A_RAW_I2C_OFFS)
/* FMC_250M Components */
#define FMC_250M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC_250M_AMC7823_SPI_OFFS (BAR4_ADDR | FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC_250M_ISLA216P_SPI_OFFS (BAR4_ADDR | FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC_250M_AD9510_SPI_OFFS (BAR4_ADDR | FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC_250M_SI571_I2C_OFFS (BAR4_ADDR | FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC_250M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_250M_EEPROM_RAW_I2C_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (/*BAR4_ADDR |*/ DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (/*BAR4_ADDR |*/ DSP_BPM_RAW_SWAP_OFFS)
/* Wishbone Addresses */
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_REGS_OFFS (/*BAR4_ADDR |*/ WB_ACQ_CORE_CTRL_RAW_REGS_OFFS)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
/* Wishbone Addresses */
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FMC1_130M_CTRL_REGS (/*BAR4_ADDR |*/ FMC1_130M_CTRL_RAW_REGS)
#define FMC1_130M_SI571_I2C (/*BAR4_ADDR |*/ FMC1_130M_SI571_RAW_I2C)
#define FMC1_130M_AD9510_SPI (/*BAR4_ADDR |*/ FMC1_130M_AD9510_RAW_SPI)
#define FMC1_130M_EEPROM_I2C (/*BAR4_ADDR |*/ FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (/*BAR4_ADDR |*/ FMC1_130M_LM75A_RAW_I2C)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
#define FMC1_130M_FMC_ADC_COMMON (BAR4_ADDR | FMC1_130M_FMC_ADC_COMMON_RAW_REGS)
#define FMC1_130M_FMC_ACTIVE_CLK (BAR4_ADDR | FMC1_130M_FMC_ACTIVE_CLK_RAW)
#define FMC1_130M_EEPROM_I2C (BAR4_ADDR | FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (BAR4_ADDR | FMC1_130M_LM75A_RAW_I2C)
#define FMC1_250M_BASE_ADDR (BAR4_ADDR | FMC1_250M_BASE_RAW_ADDR)
#define FMC1_250M_CTRL_REGS (/*BAR4_ADDR |*/ FMC1_250M_CTRL_RAW_REGS)
#define FMC1_250M_AMC7823_SPI (/*BAR4_ADDR |*/ FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (/*BAR4_ADDR |*/ FMC1_250M_ISLA216P_RAW_SPI)
#define FMC1_250M_AD9510_SPI (/*BAR4_ADDR |*/ FMC1_250M_AD9510_RAW_SPI)
#define FMC1_250M_SI571_I2C (/*BAR4_ADDR |*/ FMC1_250M_SI571_RAW_I2C)
#define FMC1_250M_EEPROM_I2C (/*BAR4_ADDR |*/ FMC1_250M_EEPROM_RAW_I2C)
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (/*BAR4_ADDR |*/ DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (/*BAR4_ADDR |*/ DSP1_BPM_RAW_SWAP)
#define FMC1_250M_CTRL_REGS (BAR4_ADDR | FMC1_250M_CTRL_RAW_REGS)
#define FMC1_250M_FMC_ADC_COMMON (BAR4_ADDR | FMC1_250M_FMC_ADC_COMMON_RAW_REGS)
#define FMC1_250M_FMC_ACTIVE_CLK (BAR4_ADDR | FMC1_250M_FMC_ACTIVE_CLK_RAW)
#define FMC1_250M_EEPROM_I2C (BAR4_ADDR | FMC1_250M_EEPROM_RAW_I2C)
#define FMC1_250M_AMC7823_SPI (BAR4_ADDR | FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (BAR4_ADDR | FMC1_250M_ISLA216P_RAW_SPI)
#define WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ1_BASE_RAW_ADDR)
/* Large Memory Addresses */
#define LARGE_MEM_ADDR (BAR2_ADDR | LARGE_MEM_RAW_ADDR)
/************************* ML605 Gateware Options *************************/
/********************* FMC130M_4CH SMIO Gateware Options ******************/
......
include/bpm_server_classes.h
View file @ 84b2c397
......@@ -25,6 +25,8 @@
/* General dependencies */
#include "board.h"
#include "mem_layout_common.h"
#include "chips_addr_common.h"
#include "epics_mapping.h"
#include "revision.h"
#include "acq_chan_gen_defs.h"
......
include/chips_addr_common.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2015 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _CHIPS_ADDR_COMMON_H_
#define _CHIPS_ADDR_COMMON_H_
#ifdef __cplusplus
extern "C" {
#endif
extern const uint32_t fmc_active_clk_si571_addr;
extern const uint32_t fmc_active_clk_ad9510_addr;
#ifdef __cplusplus
}
#endif
#endif
include/dev_io_core.h
View file @ 84b2c397
......@@ -65,13 +65,13 @@ devio_err_e devio_destroy (devio_t **self_p);
* this is stored in the SDB structure inside the device */
devio_err_e devio_print_info (devio_t *self);
/* Register an specific sm_io module to this device */
devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id,
devio_err_e devio_register_sm (void *pipe, uint32_t smio_id,
uint64_t base, uint32_t inst_id);
/* Register all sm_io module that this device can handle,
* according to the device information stored in the SDB */
devio_err_e devio_register_all_sm (devio_t *self);
devio_err_e devio_unregister_sm (devio_t *self, const char *smio_key);
devio_err_e devio_unregister_all_sm (devio_t *self);
devio_err_e devio_register_all_sm (void *pipe);
devio_err_e devio_unregister_sm (void *pipe, const char *smio_key);
devio_err_e devio_unregister_all_sm (void *pipe);
/* Poll all PIPE sockets */
void devio_loop (zsock_t *pipe, void *args);
/* Router for all the opcodes registered for this dev_io */
......
include/hw/wb_fmc130m_4ch_regs.h
View file @ 84b2c397
/*
Register definitions for slave core: Control and status registers for FMC 130M 4CH
* File : fmc130m_4ch_regs.h
* File : wb_fmc130m_4ch_regs.h
* Author : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
* Created : Fri May 16 20:05:39 2014
* Created : Mon Apr 18 15:10:45 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
......@@ -31,40 +31,6 @@
#endif
/* definitions for register: FMC Status */
/* definitions for field: FMC Present in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_PRSNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Power Good from mezzanine in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_PG_M2C WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Clock Direction in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_CLK_DIR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Firware ID in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_SHIFT 3
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Trigger control */
/* definitions for field: DIR in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: ADC LTC2208 control register (4 chips) */
/* definitions for field: RAND in reg: ADC LTC2208 control register (4 chips) */
......@@ -85,46 +51,6 @@
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Clock distribution control register */
/* definitions for field: SI571_OE in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PLL_FUNCTION in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: PLL_STATUS in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: CLK_SEL in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: Temperate Alarm in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_TEMP_ALARM WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: FPGA control */
/* definitions for field: FMC_IDELAY_RST in reg: FPGA control */
......@@ -151,8 +77,8 @@
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 6, 2)
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 6, 2)
/* definitions for field: Enable test data in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEST_DATA_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Temperature Alarm in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEMP_ALARM WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Reserved in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_MASK WBGEN2_GEN_MASK(9, 23)
......@@ -306,34 +232,26 @@
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_SHIFT 5
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* [0x0]: REG FMC Status */
#define WB_FMC_130M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_130M_4CH_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_REG_ADC 0x00000008
/* [0xc]: REG Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_REG_CLK_DISTRIB 0x0000000c
/* [0x10]: REG Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_REG_MONITOR 0x00000010
/* [0x14]: REG FPGA control */
#define WB_FMC_130M_4CH_CSR_REG_FPGA_CTRL 0x00000014
/* [0x18]: REG IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY0_CAL 0x00000018
/* [0x1c]: REG IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY1_CAL 0x0000001c
/* [0x20]: REG IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY2_CAL 0x00000020
/* [0x24]: REG IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY3_CAL 0x00000024
/* [0x28]: REG ADC Data Channel 0 */
#define WB_FMC_130M_4CH_CSR_REG_DATA0 0x00000028
/* [0x2c]: REG ADC Data Channel 1 */
#define WB_FMC_130M_4CH_CSR_REG_DATA1 0x0000002c
/* [0x30]: REG ADC Data Channel 2 */
#define WB_FMC_130M_4CH_CSR_REG_DATA2 0x00000030
/* [0x34]: REG ADC Data Channel 3 */
#define WB_FMC_130M_4CH_CSR_REG_DATA3 0x00000034
/* [0x38]: REG ADC DCM control */
#define WB_FMC_130M_4CH_CSR_REG_DCM 0x00000038
/* [0x0]: REG ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_REG_ADC 0x00000000
/* [0x4]: REG FPGA control */
#define WB_FMC_130M_4CH_CSR_REG_FPGA_CTRL 0x00000004
/* [0x8]: REG IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY0_CAL 0x00000008
/* [0xc]: REG IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY1_CAL 0x0000000c
/* [0x10]: REG IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY2_CAL 0x00000010
/* [0x14]: REG IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY3_CAL 0x00000014
/* [0x18]: REG ADC Data Channel 0 */
#define WB_FMC_130M_4CH_CSR_REG_DATA0 0x00000018
/* [0x1c]: REG ADC Data Channel 1 */
#define WB_FMC_130M_4CH_CSR_REG_DATA1 0x0000001c
/* [0x20]: REG ADC Data Channel 2 */
#define WB_FMC_130M_4CH_CSR_REG_DATA2 0x00000020
/* [0x24]: REG ADC Data Channel 3 */
#define WB_FMC_130M_4CH_CSR_REG_DATA3 0x00000024
/* [0x28]: REG ADC DCM control */
#define WB_FMC_130M_4CH_CSR_REG_DCM 0x00000028
#endif
include/hw/wb_fmc250m_4ch_regs.h
View file @ 84b2c397
/*
Register definitions for slave core: FMC ADC 250MS/s core registers
* File : fmc250m_4ch_regs.h
* File : wb_fmc250m_4ch_regs.h
* Author : auto-generated by wbgen2 from wb_fmc250m_4ch_regs.wb
* Created : Mon Feb 22 10:48:46 2016
* Created : Mon Apr 18 15:12:15 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc250m_4ch_regs.wb
......@@ -31,86 +31,6 @@
#endif
/* definitions for register: Status register */
/* definitions for field: MMCM locked status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_MMCM_LOCKED WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC power good status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_PWR_GOOD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC board present status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_PRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_MASK WBGEN2_GEN_MASK(3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 28)
/* definitions for register: Clock distribution control register */
/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: Enable test data in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_TEST_DATA_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Monitor device in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_MASK WBGEN2_GEN_MASK(4, 1)
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_SHIFT 4
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_W(value) WBGEN2_GEN_WRITE(value, 4, 1)
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_R(reg) WBGEN2_GEN_READ(reg, 4, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_SHIFT 5
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* definitions for register: Trigger control */
/* definitions for field: Direction in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Global ADC Status register */
/* definitions for field: FMC ADC clock chains in reg: Global ADC Status register */
......@@ -525,40 +445,42 @@
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_SHIFT 10
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* [0x0]: REG Status register */
#define WB_FMC_250M_4CH_CSR_REG_FMC_STA 0x00000000
/* [0x4]: REG Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_REG_CLK_DISTRIB 0x00000004
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_REG_MONITOR 0x00000008
/* [0xc]: REG Trigger control */
#define WB_FMC_250M_4CH_CSR_REG_TRIGGER 0x0000000c
/* [0x10]: REG Global ADC Status register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_STA 0x00000010
/* [0x14]: REG Global ADC Control register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_CTL 0x00000014
/* [0x18]: REG Channel 0 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_STA 0x00000018
/* [0x1c]: REG Channel 0 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_FN_DLY 0x0000001c
/* [0x20]: REG Channel 0 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_CS_DLY 0x00000020
/* [0x24]: REG Channel 1 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_STA 0x00000024
/* [0x28]: REG Channel 1 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_FN_DLY 0x00000028
/* [0x2c]: REG Channel 1 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_CS_DLY 0x0000002c
/* [0x30]: REG Channel 2 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_STA 0x00000030
/* [0x34]: REG Channel 2 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_FN_DLY 0x00000034
/* [0x38]: REG Channel 2 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_CS_DLY 0x00000038
/* [0x3c]: REG Channel 3 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_STA 0x0000003c
/* [0x40]: REG Channel 3 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_FN_DLY 0x00000040
/* [0x44]: REG Channel 3 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_CS_DLY 0x00000044
/* definitions for register: FMC temperature monitor register */
/* definitions for field: Monitor device in reg: FMC temperature monitor register */
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_MASK WBGEN2_GEN_MASK(0, 1)
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_SHIFT 0
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* [0x0]: REG Global ADC Status register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_STA 0x00000000
/* [0x4]: REG Global ADC Control register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_CTL 0x00000004
/* [0x8]: REG Channel 0 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_STA 0x00000008
/* [0xc]: REG Channel 0 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_FN_DLY 0x0000000c
/* [0x10]: REG Channel 0 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_CS_DLY 0x00000010
/* [0x14]: REG Channel 1 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_STA 0x00000014
/* [0x18]: REG Channel 1 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_FN_DLY 0x00000018
/* [0x1c]: REG Channel 1 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_CS_DLY 0x0000001c
/* [0x20]: REG Channel 2 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_STA 0x00000020
/* [0x24]: REG Channel 2 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_FN_DLY 0x00000024
/* [0x28]: REG Channel 2 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_CS_DLY 0x00000028
/* [0x2c]: REG Channel 3 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_STA 0x0000002c
/* [0x30]: REG Channel 3 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_FN_DLY 0x00000030
/* [0x34]: REG Channel 3 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_CS_DLY 0x00000034
/* [0x38]: REG FMC temperature monitor register */
#define WB_FMC_250M_4CH_CSR_REG_TEMP 0x00000038
#endif
include/hw/wb_fmc_active_clk_regs.h 0 → 100644
View file @ 84b2c397
/*
Register definitions for slave core: FMC Active Clock registers
* File : wb_fmc_active_clk_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
* Created : Mon Apr 18 10:20:28 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Clock distribution control register */
/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Dummy */
/* definitions for field: Reserved in reg: Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_SHIFT 0
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_REG_CLK_DISTRIB 0x00000000
/* [0x4]: REG Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_REG_DUMMY 0x00000004
#endif
include/hw/wb_fmc_adc_common_regs.h 0 → 100644
View file @ 84b2c397
/*
Register definitions for slave core: FMC ADC Common registers
* File : wb_fmc_adc_common_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
* Created : Mon Apr 18 09:02:33 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_FMC_ADC_COMMON_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMC_ADC_COMMON_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status register */
/* definitions for field: MMCM locked status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_MMCM_LOCKED WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC power good status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_PWR_GOOD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC board present status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_PRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_MASK WBGEN2_GEN_MASK(3, 28)
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_SHIFT 3
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 28)
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 28)
/* definitions for register: Trigger control */
/* definitions for field: Direction in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: Enable test data in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_TEST_DATA_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* [0x0]: REG Status register */
#define WB_FMC_ADC_COMMON_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_ADC_COMMON_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_REG_MONITOR 0x00000008
#endif
include/mem_layout_common.h 0 → 100644
View file @ 84b2c397
#ifndef _MEM_LAYOUT_COMMON_
#define _MEM_LAYOUT_COMMON_
#ifdef __cplusplus
extern "C" {
#endif
#include "pcie_regs.h"
/* FMC_ACTIVE_CLK Component */
#define FMC_ACTIVE_CLK_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_ACTIVE_CLK_SI571_RAW_I2C_OFFS 0x0100
#define FMC_ACTIVE_CLK_AD9510_RAW_SPI_OFFS 0x0200
/* FMC_130M Components */
#define FMC_130M_CTRL_RAW_REGS_OFFS 0x00000
#define FMC_130M_FMC_ADC_COMMON_RAW_REGS_OFFS 0x01000
#define FMC_130M_FMC_ACTIVE_CLK_RAW_OFFS 0x02000
#define FMC_130M_EEPROM_RAW_I2C_OFFS 0x03000
#define FMC_130M_LM75A_RAW_I2C_OFFS 0x04000
/* FMC_250M Components */
#define FMC_250M_CTRL_RAW_REGS_OFFS 0x00000
#define FMC_250M_FMC_ADC_COMMON_RAW_REGS_OFFS 0x01000
#define FMC_250M_FMC_ACTIVE_CLK_RAW_OFFS 0x02000
#define FMC_250M_EEPROM_RAW_I2C_OFFS 0x03000
#define FMC_250M_AMC7823_RAW_SPI_OFFS 0x04000
#define FMC_250M_ISLA216P_RAW_SPI_OFFS 0x05000
/* DSP Components */
#define DSP_CTRL_RAW_REGS_OFFS 0x0000
#define DSP_BPM_RAW_SWAP_OFFS 0x0100
/* AFC DIAG Components */
#define WB_AFC_DIAG_CTRL_RAW_REGS_OFFS 0x0000
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_RAW_REGS_OFFS 0x0000
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
/* The following is a bit of a hack.
* We employ a generic API for talking to the hardware.
* So, our transport layer (PCIe or Ethernet, for now)
* should be invisible to the SMIO instances.
*
* However, PCI devices generally employ multiple BAR
* registers mapped to different parts of the device.
* For instance, in the bpm-gw FPGA firmware, the PCIe
* core has 3 BARs (BAR0, BAR2 and BAR4) mapped to the
* following:
*
* BAR0 -> PCIe control registers
* BAR2 -> DDR3 SDRAM
* BAR4 -> Wishbone (necessary to use pages mechanism)
*
* So, we define our addresses as the logic address plus
* the BAR number. With this, the PCIe transport layer
* can differentiate between multiple bars and select
* the correct one to read or write
*/
/* FMC_ACTIVE_CLK Component */
#define FMC_ACTIVE_CLK_CTRL_REGS_OFFS (BAR4_ADDR | FMC_ACTIVE_CLK_CTRL_RAW_REGS_OFFS)
#define FMC_ACTIVE_CLK_SI571_I2C_OFFS (BAR4_ADDR | FMC_ACTIVE_CLK_SI571_RAW_I2C_OFFS)
#define FMC_ACTIVE_CLK_AD9510_SPI_OFFS (BAR4_ADDR | FMC_ACTIVE_CLK_AD9510_RAW_SPI_OFFS)
/* FMC_130M Components */
#define FMC_130M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC_130M_FMC_ADC_COMMON_OFFS (BAR4_ADDR | FMC_130M_FMC_ADC_COMMON_RAW_REGS_OFFS)
#define FMC_130M_FMC_ACTIVE_CLK_OFFS (BAR4_ADDR | FMC_130M_FMC_ACTIVE_CLK_RAW_OFFS)
#define FMC_130M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (BAR4_ADDR | FMC_130M_LM75A_RAW_I2C_OFFS)
/* FMC_250M Components */
#define FMC_250M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC_250M_FMC_ADC_COMMON_OFFS (BAR4_ADDR | FMC_250M_FMC_ADC_COMMON_RAW_REGS_OFFS)
#define FMC_250M_FMC_ACTIVE_CLK_OFFS (BAR4_ADDR | FMC_250M_FMC_ACTIVE_CLK_RAW_OFFS)
#define FMC_250M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_250M_EEPROM_RAW_I2C_OFFS)
#define FMC_250M_AMC7823_SPI_OFFS (BAR4_ADDR | FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC_250M_ISLA216P_SPI_OFFS (BAR4_ADDR | FMC_250M_ISLA216P_RAW_SPI_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (BAR4_ADDR | DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (BAR4_ADDR | DSP_BPM_RAW_SWAP_OFFS)
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_REGS_OFFS (BAR4_ADDR | WB_ACQ_CORE_CTRL_RAW_REGS_OFFS)
/* Large Memory Addresses */
#define LARGE_MEM_ADDR (BAR2_ADDR | LARGE_MEM_RAW_ADDR)
#ifdef __cplusplus
}
#endif
#endif
include/sm_io.h
View file @ 84b2c397
......@@ -124,6 +124,9 @@ smio_t *smio_new (th_boot_args_t *args, zsock_t *pipe_mgmt, zsock_t *pipe_msg,
smio_err_e smio_destroy (smio_t **self_p);
/* Loop through all interface sockets */
smio_err_e smio_loop (smio_t *self);
/* Register SMIO */
smio_err_e smio_register_sm (smio_t *self, uint32_t smio_id, uint64_t base,
uint32_t inst_id);
smio_err_e smio_init_exp_ops (smio_t *self, disp_op_t** smio_exp_ops,
const disp_table_func_fp *func_fps);
......
include/sm_io_err.h
View file @ 84b2c397
......@@ -29,6 +29,7 @@ enum _smio_err_e {
SMIO_ERR_INTERRUPTED_POLLER, /* SMIO Poller interrupted. zeroMQ context was
terminated or received interrupt signal */
SMIO_ERR_INV_SOCKET, /* Invalid socket reference */
SMIO_ERR_REGISTER_SM, /* Could not register SMIO */
SMIO_ERR_END /* End of enum marker */
};
......
src/apps/ebpm/ebpm.c
View file @ 84b2c397
......@@ -67,10 +67,10 @@ static devio_err_e _spawn_epics_iocs (devio_t *devio, uint32_t dev_id,
char *cfg_file, char *broker_endp, char *log_prefix, zhashx_t *hints);
static char *_create_log_filename (char *log_prefix, uint32_t dev_id,
const char *devio_type, uint32_t smio_inst_id);
static devio_err_e _spawn_platform_smios (devio_t *devio, devio_type_e devio_type,
static devio_err_e _spawn_platform_smios (void *pipe, devio_type_e devio_type,
uint32_t smio_inst_id, zhashx_t *hints, uint32_t dev_id);
static devio_err_e _spawn_be_platform_smios (devio_t *devio, zhashx_t *hints, uint32_t dev_id);
static devio_err_e _spawn_fe_platform_smios (devio_t *devio, uint32_t smio_inst_id);
static devio_err_e _spawn_be_platform_smios (void *pipe, zhashx_t *hints, uint32_t dev_id);
static devio_err_e _spawn_fe_platform_smios (void *pipe, uint32_t smio_inst_id);
static struct option long_options[] =
{
......@@ -468,7 +468,7 @@ int main (int argc, char *argv[])
broker_endp = NULL;
/* Spawn platform SMIOSs */
err = _spawn_platform_smios (devio, devio_type, fe_smio_id, devio_hints,
err = _spawn_platform_smios (server, devio_type, fe_smio_id, devio_hints,
dev_id);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] _spawn_platform_smios error!\n");
......@@ -798,20 +798,20 @@ err_devio_log_alloc:
return NULL;
}
static devio_err_e _spawn_platform_smios (devio_t *devio, devio_type_e devio_type,
static devio_err_e _spawn_platform_smios (void *pipe, devio_type_e devio_type,
uint32_t smio_inst_id, zhashx_t *hints, uint32_t dev_id)
{
assert (devio);
assert (pipe);
devio_err_e err = DEVIO_SUCCESS;
switch (devio_type) {
case BE_DEVIO:
err = _spawn_be_platform_smios (devio, hints, dev_id);
err = _spawn_be_platform_smios (pipe, hints, dev_id);
break;
case FE_DEVIO:
err = _spawn_fe_platform_smios (devio, smio_inst_id);
err = _spawn_fe_platform_smios (pipe, smio_inst_id);
break;
default:
......@@ -828,7 +828,7 @@ err_register_sm:
return err;
}
static devio_err_e _spawn_be_platform_smios (devio_t *devio, zhashx_t *hints, uint32_t dev_id)
static devio_err_e _spawn_be_platform_smios (void *pipe, zhashx_t *hints, uint32_t dev_id)
{
const char *fmc_board_130m_4ch = "fmc130m_4ch";
const char *fmc_board_250m_4ch = "fmc250m_4ch";
......@@ -854,30 +854,30 @@ static devio_err_e _spawn_be_platform_smios (devio_t *devio, zhashx_t *hints, ui
streq (cfg_item->fmc_board, "") || streq (cfg_item->fmc_board,
fmc_board_130m_4ch)) {
/* Default FMC Board */
err = devio_register_sm (devio, fmc130m_4ch_id, FMC1_130M_BASE_ADDR, 0);
err = devio_register_sm (pipe, fmc130m_4ch_id, FMC1_130M_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
}
else if (streq (cfg_item->fmc_board, fmc_board_250m_4ch)) {
/* FMC250m Board */
err = devio_register_sm (devio, fmc250m_4ch_id, FMC1_250M_BASE_ADDR, 0);
err = devio_register_sm (pipe, fmc250m_4ch_id, FMC1_250M_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
}
err = devio_register_sm (devio, acq_id, WB_ACQ1_BASE_ADDR, 0);
err = devio_register_sm (pipe, acq_id, WB_ACQ1_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
err = devio_register_sm (devio, dsp_id, DSP1_BASE_ADDR, 0);
err = devio_register_sm (pipe, dsp_id, DSP1_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
err = devio_register_sm (devio, swap_id, DSP1_BASE_ADDR, 0);
err = devio_register_sm (pipe, swap_id, DSP1_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
......@@ -896,35 +896,35 @@ static devio_err_e _spawn_be_platform_smios (devio_t *devio, zhashx_t *hints, ui
streq (cfg_item->fmc_board, "") || streq (cfg_item->fmc_board,
fmc_board_130m_4ch)) {
/* Default FMC Board */
err = devio_register_sm (devio, fmc130m_4ch_id, FMC2_130M_BASE_ADDR, 1);
err = devio_register_sm (pipe, fmc130m_4ch_id, FMC2_130M_BASE_ADDR, 1);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
}
else if (streq (cfg_item->fmc_board, fmc_board_250m_4ch)) {
/* FMC250m Board */
err = devio_register_sm (devio, fmc250m_4ch_id, FMC2_250M_BASE_ADDR, 1);
err = devio_register_sm (pipe, fmc250m_4ch_id, FMC2_250M_BASE_ADDR, 1);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
}
err = devio_register_sm (devio, acq_id, WB_ACQ2_BASE_ADDR, 1);
err = devio_register_sm (pipe, acq_id, WB_ACQ2_BASE_ADDR, 1);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
err = devio_register_sm (devio, dsp_id, DSP2_BASE_ADDR, 1);
err = devio_register_sm (pipe, dsp_id, DSP2_BASE_ADDR, 1);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
err = devio_register_sm (devio, swap_id, DSP2_BASE_ADDR, 1);
err = devio_register_sm (pipe, swap_id, DSP2_BASE_ADDR, 1);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
err = devio_register_sm (devio, afc_diag_id, WB_AFC_DIAG_BASE_ADDR, 0);
err = devio_register_sm (pipe, afc_diag_id, WB_AFC_DIAG_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
......@@ -936,7 +936,7 @@ static devio_err_e _spawn_be_platform_smios (devio_t *devio, zhashx_t *hints, ui
return err;
}
static devio_err_e _spawn_fe_platform_smios (devio_t *devio, uint32_t smio_inst_id)
static devio_err_e _spawn_fe_platform_smios (void *pipe, uint32_t smio_inst_id)
{
uint32_t rffe_id = 0x7af21909;
devio_err_e err = DEVIO_SUCCESS;
......@@ -945,7 +945,7 @@ static devio_err_e _spawn_fe_platform_smios (devio_t *devio, uint32_t smio_inst_
/* #if defined (__AFE_RFFE_V1__) */
#if defined (__AFE_RFFE_V2__)
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_INFO, "[dev_io_fe] Spawning default SMIOs ...\n");
err = devio_register_sm (devio, rffe_id, 0, smio_inst_id);
err = devio_register_sm (pipe, rffe_id, 0, smio_inst_id);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io_fe] devio_register_sm error!\n");
}
......
src/apps/ebpm/ebpm_cfg.c
View file @ 84b2c397
......@@ -9,9 +9,9 @@
#define DEVIO_SERVICE_LEN 50
static devio_err_e _spawn_platform_smios (devio_t *devio, devio_type_e devio_type,
static devio_err_e _spawn_platform_smios (void *pipe, devio_type_e devio_type,
uint32_t smio_inst_id);
static devio_err_e _spawn_be_platform_smios (devio_t *devio);
static devio_err_e _spawn_be_platform_smios (void *pipe);
static struct option long_options[] =
{
......@@ -245,7 +245,7 @@ int main (int argc, char *argv[])
/* TODO: Implement and Send SPAWN messages to spawn SMIOs */
devio_err_e err = _spawn_platform_smios (devio, devio_type, 0);
devio_err_e err = _spawn_platform_smios (server, devio_type, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm_cfg] _spawn_platform_smios error!\n");
goto err_plat_devio;
......@@ -266,18 +266,18 @@ err_exit:
return 0;
}
static devio_err_e _spawn_platform_smios (devio_t *devio, devio_type_e devio_type,
static devio_err_e _spawn_platform_smios (void *pipe, devio_type_e devio_type,
uint32_t smio_inst_id)
{
(void) smio_inst_id;
assert (devio);
assert (pipe);
devio_err_e err = DEVIO_SUCCESS;
switch (devio_type) {
case BE_DEVIO:
err = _spawn_be_platform_smios (devio);
err = _spawn_be_platform_smios (pipe);
break;
default:
......@@ -294,20 +294,20 @@ err_register_sm:
return err;
}
static devio_err_e _spawn_be_platform_smios (devio_t *devio)
static devio_err_e _spawn_be_platform_smios (void *pipe)
{
devio_err_e err = DEVIO_SUCCESS;
/* ML605 specific */
#if defined (__BOARD_ML605__)
(void) devio;
(void) pipe;
/* AFCv3 spefific */
#elif defined (__BOARD_AFCV3__)
uint32_t afc_diag_id = 0x51954750;
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_INFO, "[ebpm_cfg] Spawning AFCv3 specific SMIOs ...\n");
err = devio_register_sm (devio, afc_diag_id, WB_AFC_DIAG_BASE_ADDR, 0);
err = devio_register_sm (pipe, afc_diag_id, WB_AFC_DIAG_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm_cfg] devio_register_sm error!\n");
}
......
src/boards/common/chips_addr_common.c 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* FMC ACTIVE CLOCK chip addresses */
const uint32_t fmc_active_clk_si571_addr = 0x49;
const uint32_t fmc_active_clk_ad9510_addr = 0x01;
src/boards/common/common.mk 0 → 100644
View file @ 84b2c397
board_common_DIR = $(SRC_DIR)/boards/common
board_common_OBJS = \
$(board_common_DIR)/chips_addr_common.o
src/dev_io/dev_io_core.c
View file @ 84b2c397
......@@ -108,6 +108,12 @@ static devio_err_e _devio_engine_handle_socket (devio_t *devio, void *sock,
static int _devio_handle_timer (zloop_t *loop, int timer_id, void *arg);
static int _devio_handle_pipe_backend (zloop_t *loop, zsock_t *reader, void *args);
static devio_err_e _devio_register_sm_raw (devio_t *self, uint32_t smio_id, uint64_t base,
uint32_t inst_id);
static devio_err_e _devio_register_all_sm_raw (devio_t *self);
static devio_err_e _devio_unregister_sm_raw (devio_t *self, const char *smio_key);
static devio_err_e _devio_unregister_all_sm_raw (devio_t *self);
/* Default signal handlers */
void devio_sigchld_h (int sig, siginfo_t *siginfo, void *context)
{
......@@ -529,6 +535,10 @@ err_zsock_is:
return err;
}
/************************************************************/
/********************** zloop handlers **********************/
/************************************************************/
/* zloop handler for timer */
static int _devio_handle_timer (zloop_t *loop, int timer_id, void *arg)
{
......@@ -571,6 +581,43 @@ static int _devio_handle_pipe_msg (zloop_t *loop, zsock_t *reader, void *args)
return 0;
}
static int _devio_handle_pipe_mgmt (zloop_t *loop, zsock_t *reader, void *args)
{
(void) loop;
/* We expect a devio instance e as reference */
devio_t *devio = (devio_t *) args;
/* Arguments for command */
char *command = NULL;
uint32_t smio_id;
uint64_t base;
uint32_t inst_id;
/* This command expects the following */
/* Command: (string) $REGISTER_SMIO
* Arg1: (uint32_t) smio_id
* Arg2: (uint64_t) base
* Arg3: (uint32_t) inst_id
* */
int zerr = zsock_recv (reader, "s484", &command, &smio_id, &base, &inst_id);
if (zerr == -1) {
return 0; /* Malformed message */
}
if (streq (command, "$REGISTER_SMIO")) {
/* Register new SMIO */
_devio_register_sm_raw (devio, smio_id, base, inst_id);
}
else {
/* Invalid message received. Discard message and continue normally */
DBE_DEBUG (DBG_SM_IO | DBG_LVL_WARN, "[dev_io_core:_devio_handle_pipe_mgmt] PIPE "
"received an invalid command\n");
}
free (command);
return 0;
}
/* zloop handler for CFG PIPE */
static int _devio_handle_pipe_cfg (zloop_t *loop, zsock_t *reader, void *args)
{
......@@ -628,38 +675,66 @@ err_poller_config_null_service:
return err;
}
/* zloop handler for PIPE.
*
* TODO: This does nothing for now */
/* zloop handler for PIPE. */
static int _devio_handle_pipe (zloop_t *loop, zsock_t *reader, void *args)
{
(void) loop;
char *command = NULL;
/* We expect a devio instance e as reference */
devio_t *devio = (devio_t *) args;
(void) devio;
/* Receive message */
zmsg_t *recv_msg = zmsg_recv (reader);
if (recv_msg == NULL) {
return -1; /* Interrupted */
char *command = NULL;
uint32_t smio_id;
uint64_t base;
uint32_t inst_id;
/* This command expects one of the following */
/* Command: (string) $REGISTER_SMIO
* Arg1: (uint32_t) smio_id
* Arg2: (uint64_t) base
* Arg3: (uint32_t) inst_id
*
* Command: (string) $TERM
*
* Either way, the following zsock_recv is able to handle both cases. In
* case of the received message is shorter than the first command, the
* additional pointers are zeroed.
* */
int zerr = zsock_recv (reader, "s484", &command, &smio_id, &base, &inst_id);
if (zerr == -1) {
return 0; /* Malformed message */
}
command = zmsg_popstr (recv_msg);
if (streq (command, "$TERM")) {
/* Shutdown the engine */
free (command);
zmsg_destroy (&recv_msg);
return -1;
}
else if (streq (command, "$REGISTER_SMIO_ALL")) {
/* Register all SMIOs */
_devio_register_all_sm_raw (devio);
}
else if (streq (command, "$REGISTER_SMIO")) {
/* Register new SMIO */
_devio_register_sm_raw (devio, smio_id, base, inst_id);
}
else if (streq (command, "$UNREGISTER_SMIO_ALL")) {
/* Unregister all SMIOs */
_devio_unregister_all_sm_raw (devio);
}
/* FIXME: Will not work, as the second parameter is a string and we expect
* something different */
else if (streq (command, "$UNREGISTER_SMIO")) {
/* Unregister SMIO */
_devio_unregister_sm_raw (devio, NULL);
}
else {
/* Invalid message received. Discard message and continue normally */
DBE_DEBUG (DBG_SM_IO | DBG_LVL_WARN, "[dev_io_core:_devio_handle_pipe] PIPE "
"received an invalid command\n");
}
zmsg_destroy (&recv_msg);
free (command);
return 0;
}
......@@ -698,8 +773,12 @@ static int _devio_handle_pipe_backend (zloop_t *loop, zsock_t *reader, void *arg
return 0;
}
/************************************************************/
/*********************** API methods ************************/
/************************************************************/
/* Register an specific sm_io modules to this device */
devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, uint64_t base,
static devio_err_e _devio_register_sm_raw (devio_t *self, uint32_t smio_id, uint64_t base,
uint32_t inst_id)
{
assert (self);
......@@ -781,6 +860,11 @@ devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, uint64_t base,
ASSERT_TEST (self->pipes_mgmt [pipe_mgmt_idx] != NULL, "Could not spawn SMIO thread",
err_spawn_smio_thread);
err = _devio_engine_handle_socket (self, self->pipes_mgmt [pipe_mgmt_idx],
_devio_handle_pipe_mgmt);
ASSERT_TEST (err == DEVIO_SUCCESS, "Could not register management socket handler",
err_pipes_mgmt_handle);
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_TRACE,
"[dev_io_core:register_sm] Inserting hash with key: %s\n", key);
int zerr = zhashx_insert (self->sm_io_h, key, &self->pipes_mgmt [pipe_mgmt_idx]);
......@@ -844,6 +928,8 @@ err_spawn_config_thread:
err_th_config_args_alloc:
zhashx_delete (self->sm_io_h, key);
err_pipe_hash_insert:
_devio_engine_handle_socket (self, self->pipes_mgmt [pipe_mgmt_idx], NULL);
err_pipes_mgmt_handle:
/* If we can't insert the SMIO thread key in hash,
* destroy it as we won't have a reference to it later! */
_devio_destroy_actor (self, &self->pipes_mgmt [pipe_mgmt_idx]);
......@@ -863,15 +949,43 @@ err_max_smios_reached:
return err;
}
devio_err_e devio_register_sm (void *pipe, uint32_t smio_id, uint64_t base,
uint32_t inst_id)
{
assert (pipe);
devio_err_e err = DEVIO_SUCCESS;
int zerr = zsock_send (pipe, "s484", "$REGISTER_SMIO", smio_id, base,
inst_id);
ASSERT_TEST(zerr == 0, "Could not register SMIO", err_register_sm,
DEVIO_ERR_INV_SOCKET /* TODO: improve error handling? */);
err_register_sm:
return err;
}
/* Register all sm_io module that this device can handle,
* according to the device information stored in the SDB */
devio_err_e devio_register_all_sm (devio_t *self)
static devio_err_e _devio_register_all_sm_raw (devio_t *self)
{
(void) self;
return DEVIO_ERR_FUNC_NOT_IMPL;
}
devio_err_e devio_unregister_sm (devio_t *self, const char *smio_key)
devio_err_e devio_register_all_sm (void *pipe)
{
assert (pipe);
devio_err_e err = DEVIO_SUCCESS;
int zerr = zsock_send (pipe, "s", "$REGISTER_SMIO_ALL");
ASSERT_TEST(zerr == 0, "Could not register all SMIOs", err_register_sm_all,
DEVIO_ERR_INV_SOCKET /* TODO: improve error handling? */);
err_register_sm_all:
return err;
}
static devio_err_e _devio_unregister_sm_raw (devio_t *self, const char *smio_key)
{
/* Don't care for errors here, as the Config actor is probably already
* gone */
......@@ -884,7 +998,20 @@ err_destroy_smio:
return err;
}
devio_err_e devio_unregister_all_sm (devio_t *self)
devio_err_e devio_unregister_sm (void *pipe, const char *smio_key)
{
assert (pipe);
devio_err_e err = DEVIO_SUCCESS;
int zerr = zsock_send (pipe, "ss", "$UNREGISTER_SMIO", smio_key);
ASSERT_TEST(zerr == 0, "Could not unregister SMIOs", err_unregister_sm,
DEVIO_ERR_INV_SOCKET /* TODO: improve error handling? */);
err_unregister_sm:
return err;
}
static devio_err_e _devio_unregister_all_sm_raw (devio_t *self)
{
devio_err_e err = _devio_destroy_smio_all (self, self->sm_io_cfg_h);
ASSERT_TEST(err == DEVIO_SUCCESS, "Could not destroy Config SMIOs",
......@@ -898,6 +1025,19 @@ err_destroy_smios:
return err;
}
devio_err_e devio_unregister_all_sm (void *pipe)
{
assert (pipe);
devio_err_e err = DEVIO_SUCCESS;
int zerr = zsock_send (pipe, "s", "$UNREGISTER_SMIO_ALL");
ASSERT_TEST(zerr == 0, "Could not unregister all SMIOs", err_unregister_sm_all,
DEVIO_ERR_INV_SOCKET /* TODO: improve error handling? */);
err_unregister_sm_all:
return err;
}
/* Main devio loop implemented as actor */
void devio_loop (zsock_t *pipe, void *args)
{
......
src/libs/libbpmclient/Makefile
View file @ 84b2c397
......@@ -100,6 +100,8 @@ OBJS_EXTERNAL = ../../sm_io/modules/sm_io_codes.o \
../../sm_io/modules/dsp/sm_io_dsp_exports.o \
../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exports.o \
../../sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exports.o \
../../sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_exports.o \
../../sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_exports.o \
../../sm_io/modules/swap/sm_io_swap_exports.o \
../../sm_io/modules/rffe/sm_io_rffe_exports.o \
../../sm_io/modules/afc_diag/sm_io_afc_diag_exports.o
......@@ -114,6 +116,8 @@ INCLUDE_DIRS = -I. -Iinclude \
-I../../sm_io/modules \
-I../../sm_io/modules/fmc130m_4ch \
-I../../sm_io/modules/fmc250m_4ch \
-I../../sm_io/modules/fmc_adc_common \
-I../../sm_io/modules/fmc_active_clk \
-I../../sm_io/modules/acq \
-I../../sm_io/modules/swap \
-I../../sm_io/modules/dsp \
......@@ -145,6 +149,8 @@ $(LIBNAME)_CODE_HEADERS = \
$(LIBNAME)_SMIO_CODES = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_codes.h \
../../sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_codes.h \
../../sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_codes.h \
../../sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_codes.h \
../../sm_io/modules/acq/sm_io_acq_codes.h \
../../sm_io/modules/dsp/sm_io_dsp_codes.h \
../../sm_io/modules/swap/sm_io_swap_codes.h \
......@@ -154,6 +160,8 @@ $(LIBNAME)_SMIO_CODES = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_codes.
$(LIBNAME)_SMIO_EXPORTS = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exports.h \
../../sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exports.h \
../../sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_exports.h \
../../sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_exports.h \
../../sm_io/modules/acq/sm_io_acq_exports.h \
../../sm_io/modules/dsp/sm_io_dsp_exports.h \
../../sm_io/modules/swap/sm_io_swap_exports.h \
......
src/libs/libbpmclient/src/bpm_client_core.c
View file @ 84b2c397
This diff is collapsed.
src/sm_io/chips/sm_ch_si57x.c
View file @ 84b2c397
......@@ -169,6 +169,8 @@ smch_err_e smch_si57x_set_freq (smch_si57x_t *self, double frequency)
assert (self);
smch_err_e err = SMCH_SUCCESS;
ASSERT_TEST(frequency > 0, "Invalid frequency (0 Hz)", err_exit);
DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE, "[sm_ch:si57x_set_freq] Configuring "
"frequency to %f Hz\n", frequency);
......
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_codes.h
View file @ 84b2c397
......@@ -12,16 +12,6 @@
#define FMC130M_4CH_OPCODE_TYPE uint32_t
#define FMC130M_4CH_OPCODE_SIZE (sizeof (FMC130M_4CH_OPCODE_TYPE))
#define FMC130M_4CH_OPCODE_LEDS 0
#define FMC130M_4CH_NAME_LEDS "fmc130m_4ch_leds"
#define FMC130M_4CH_OPCODE_SI571_OE 1
#define FMC130M_4CH_NAME_SI571_OE "fmc130m_4ch_si571_oe"
#define FMC130M_4CH_OPCODE_PLL_FUNCTION 2
#define FMC130M_4CH_NAME_PLL_FUNCTION "fmc130m_4ch_pll_function"
#define FMC130M_4CH_OPCODE_PLL_STATUS 3
#define FMC130M_4CH_NAME_PLL_STATUS "fmc130m_4ch_pll_status"
#define FMC130M_4CH_OPCODE_CLK_SEL 4
#define FMC130M_4CH_NAME_CLK_SEL "fmc130m_4ch_clk_sel"
#define FMC130M_4CH_OPCODE_ADC_RAND 5
#define FMC130M_4CH_NAME_ADC_RAND "fmc130m_4ch_adc_rand"
#define FMC130M_4CH_OPCODE_ADC_DITH 6
......@@ -70,39 +60,7 @@
#define FMC130M_4CH_NAME_ADC_DLY2 "fmc130m_4ch_adc_dly2"
#define FMC130M_4CH_OPCODE_ADC_DLY3 28
#define FMC130M_4CH_NAME_ADC_DLY3 "fmc130m_4ch_adc_dly3"
#define FMC130M_4CH_OPCODE_TEST_DATA_EN 29
#define FMC130M_4CH_NAME_TEST_DATA_EN "fmc130m_4ch_adc_test_data_en"
#define FMC130M_4CH_OPCODE_TRIG_DIR 30
#define FMC130M_4CH_NAME_TRIG_DIR "fmc130m_4ch_trig_dir"
#define FMC130M_4CH_OPCODE_TRIG_TERM 31
#define FMC130M_4CH_NAME_TRIG_TERM "fmc130m_4ch_trig_term"
#define FMC130M_4CH_OPCODE_TRIG_VAL 32
#define FMC130M_4CH_NAME_TRIG_VAL "fmc130m_4ch_trig_val"
#define FMC130M_4CH_OPCODE_AD9510_CFG_DEFAULTS 33
#define FMC130M_4CH_NAME_AD9510_CFG_DEFAULTS "fmc130m_4ch_ad9510_cfg_defaults"
#define FMC130M_4CH_OPCODE_AD9510_PLL_A_DIV 34
#define FMC130M_4CH_NAME_AD9510_PLL_A_DIV "fmc130m_4ch_ad9510_pll_a_div"
#define FMC130M_4CH_OPCODE_AD9510_PLL_B_DIV 35
#define FMC130M_4CH_NAME_AD9510_PLL_B_DIV "fmc130m_4ch_ad9510_pll_b_div"
#define FMC130M_4CH_OPCODE_AD9510_PLL_PRESCALER 36
#define FMC130M_4CH_NAME_AD9510_PLL_PRESCALER "fmc130m_4ch_ad9510_pll_prescaler"
#define FMC130M_4CH_OPCODE_AD9510_R_DIV 37
#define FMC130M_4CH_NAME_AD9510_R_DIV "fmc130m_4ch_ad9510_r_div"
#define FMC130M_4CH_OPCODE_AD9510_PLL_PDOWN 38
#define FMC130M_4CH_NAME_AD9510_PLL_PDOWN "fmc130m_4ch_ad9510_pll_pdown"
#define FMC130M_4CH_OPCODE_AD9510_MUX_STATUS 39
#define FMC130M_4CH_NAME_AD9510_MUX_STATUS "fmc130m_4ch_ad9510_mux_status"
#define FMC130M_4CH_OPCODE_AD9510_CP_CURRENT 40
#define FMC130M_4CH_NAME_AD9510_CP_CURRENT "fmc130m_4ch_ad9510_cp_current"
#define FMC130M_4CH_OPCODE_AD9510_OUTPUTS 41
#define FMC130M_4CH_NAME_AD9510_OUTPUTS "fmc130m_4ch_ad9510_outputs"
#define FMC130M_4CH_OPCODE_AD9510_PLL_CLK_SEL 42
#define FMC130M_4CH_NAME_AD9510_PLL_CLK_SEL "fmc130m_4ch_ad9510_pll_clk_sel"
#define FMC130M_4CH_OPCODE_SI571_SET_FREQ 43
#define FMC130M_4CH_NAME_SI571_SET_FREQ "fmc130m_4ch_si571_set_freq"
#define FMC130M_4CH_OPCODE_SI571_GET_DEFAULTS 44
#define FMC130M_4CH_NAME_SI571_GET_DEFAULTS "fmc130m_4ch_si571_get_defaults"
#define FMC130M_4CH_OPCODE_END 45
#define FMC130M_4CH_OPCODE_END 29
/* Messaging Reply OPCODES */
#define FMC130M_4CH_REPLY_TYPE uint32_t
......
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_core.c
View file @ 84b2c397
......@@ -44,6 +44,7 @@ smio_fmc130m_4ch_t * smio_fmc130m_4ch_new (smio_t *parent)
smio_fmc130m_4ch_t *self = (smio_fmc130m_4ch_t *) zmalloc (sizeof *self);
ASSERT_ALLOC(self, err_self_alloc);
uint32_t inst_id = smio_get_inst_id (parent);
uint64_t base = smio_get_base (parent);
/* Check if Instance ID is within our expected limits */
ASSERT_TEST(inst_id < NUM_FMC130M_4CH_SMIOS, "Number of FMC130M_4CH SMIOs instances exceeded",
......@@ -109,42 +110,25 @@ smio_fmc130m_4ch_t * smio_fmc130m_4ch_new (smio_t *parent)
/* Determine the type of the FMC130M_4CH board */
_smio_fmc130m_4ch_set_type (self, data_24aa64);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc130m_4ch_core] Registering FMC_ADC_COMMON SMIO\n");
smio_register_sm (parent, 0x2403f569, base | FMC_130M_FMC_ADC_COMMON_OFFS, inst_id);
/* Now, initialize the FMC130M_4CH with the appropriate structures*/
if (self->type == TYPE_FMC130M_4CH_ACTIVE) {
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc130m_4ch_core] AD9510 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc130m_4ch_ad9510_addr[inst_id],
inst_id);
self->smch_ad9510 = smch_ad9510_new (parent, FMC_130M_AD9510_SPI_OFFS,
fmc130m_4ch_ad9510_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_ad9510, err_smch_ad9510_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc130m_4ch_core] SI571 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc130m_4ch_si571_addr[inst_id],
inst_id);
self->smch_si571 = smch_si57x_new (parent, FMC_130M_SI571_I2C_OFFS,
fmc130m_4ch_si571_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_si571, err_smch_si571_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc130m_4ch_core] Active Board detected. "
"Registering FMC_ADC_ACTIVE SMIO\n");
smio_register_sm (parent, 0x88c67d9c, base | FMC_130M_FMC_ACTIVE_CLK_OFFS, inst_id);
}
else { /* PASSIVE or Unsupported*/
if (self->type != TYPE_FMC130M_4CH_PASSIVE) {
DBE_DEBUG (DBG_SM_IO | DBG_LVL_WARN,
"[sm_io:fmc130m_4ch_core] Unsupported FMC130M_4CH card (maybe EEPROM not configured?).\n"
"\t Defaulting to PASSIVE board\n");
}
self->smch_ad9510 = NULL;
self->smch_si571 = NULL;
}
return self;
err_smch_si571_alloc:
if (self->smch_ad9510 != NULL) {
smch_ad9510_destroy (&self->smch_ad9510);
}
err_smch_ad9510_alloc:
smch_24aa64_destroy (&self->smch_24aa64);
err_smch_24aa64_alloc:
if (self->smch_pca9547 != NULL) {
smch_pca9547_destroy (&self->smch_pca9547);
......@@ -164,8 +148,6 @@ smio_err_e smio_fmc130m_4ch_destroy (smio_fmc130m_4ch_t **self_p)
if (*self_p) {
smio_fmc130m_4ch_t *self = *self_p;
smch_si57x_destroy (&self->smch_si571);
smch_ad9510_destroy (&self->smch_ad9510);
smch_24aa64_destroy (&self->smch_24aa64);
if (self->smch_pca9547 != NULL) {
......
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_core.h
View file @ 84b2c397
......@@ -8,9 +8,6 @@
#ifndef _SM_IO_FMC130M_4CH_CORE_H_
#define _SM_IO_FMC130M_4CH_CORE_H_
#define SMIO_AD9510_HANDLER(smio_handler) ((smch_ad9510_t *) smio_handler->smch_ad9510)
#define SMIO_SI57X_HANDLER(smio_handler) ((smch_si57x_t *) smio_handler->smch_si571)
/* The follosing codes were generated via the following command:
* > echo FMC130M_4CH_ACTIVE | md5sum | cut -c 1-8
* > cb04db4d
......@@ -31,8 +28,6 @@ typedef enum {
typedef struct {
fmc130m_4ch_type_e type; /* FMC130M_4CH type */
smch_ad9510_t *smch_ad9510; /* AD9510 chip handler */
smch_si57x_t *smch_si571; /* SI571 chip handler */
smch_24aa64_t *smch_24aa64; /* 24AA64 chip handler */
smch_pca9547_t *smch_pca9547; /* FPGA I2C Switch */
} smio_fmc130m_4ch_t;
......
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_defaults.c
View file @ 84b2c397
......@@ -48,43 +48,14 @@ smio_err_e fmc130m_4ch_config_defaults (char *broker_endp, char *service,
(void) log_file_name;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:fmc130m_4ch_defaults] Configuring SMIO "
"FMC130M_4CH with default values ...\n");
bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
smio_err_e err = SMIO_SUCCESS;
bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
log_file_name, SMIO_FMC130M_4CH_LIBBPMCLIENT_LOG_MODE);
ASSERT_ALLOC(config_client, err_alloc_client);
client_err = bpm_set_fmc_pll_function (config_client, service, FMC130M_4CH_DFLT_PLL_FUNC);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC PLL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
/* Configure defaults here */
client_err = bpm_set_fmc_clk_sel (config_client, service, FMC130M_4CH_DFLT_CLK_SEL);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC CLK SEL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_trig_dir (config_client, service, FMC130M_4CH_DFLT_TRIG_DIR);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC TRIG DIR function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_ad9510_cfg_defaults (config_client, service, 0);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS ||
client_err == BPM_CLIENT_ERR_AGAIN, "Could not configure AD9510",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_defaults (config_client, service, FMC130M_4CH_DFLT_SI57X_FOUT_FACTORY);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not get Si571 defaults",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_set_freq (config_client, service, FMC130M_4CH_DFLT_SI57X_FOUT);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set Si571 frequency",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_oe (config_client, service, FMC130M_4CH_DFLT_SI571_OE);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not enable SI571 Output",
err_param_set, SMIO_ERR_CONFIG_DFLT);
err_param_set:
bpm_client_destroy (&config_client);
err_alloc_client:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:fmc130m_4ch_defaults] Exiting Config thread %s\n",
......
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_defaults.h
View file @ 84b2c397
......@@ -9,17 +9,9 @@
#define _FMC130M_4CH_DEFAULTS_H_
#include "sm_io_err.h"
#include "chips/si57x_regs.h"
#include "sm_ch_pca9547.h"
#define FMC130M_4CH_DFLT_PLL_FUNC 0x1
#define FMC130M_4CH_DFLT_CLK_SEL 0x0 /* Clock from FMC front panel */
#define FMC130M_4CH_DFLT_TRIG_DIR 0x0 /* Output direction */
#define FMC130M_4CH_DFLT_PCA9547_CFG SMCH_PCA9547_NO_CHANNEL /* No channel selected */
#define FMC130M_4CH_DFLT_SI571_OE 0x1
#define FMC130M_4CH_DFLT_SI57X_FOUT_FACTORY SI57X_FOUT_FACTORY_DFLT
#define FMC130M_4CH_DFLT_SI57X_FOUT 113040445 /* 113.040445 MHz default */
smio_err_e fmc130m_4ch_config_defaults (char *broker_endp, char *service,
const char *log_file_name);
......
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exp.c 100755 → 100644
View file @ 84b2c397
This diff is collapsed.
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exports.c
View file @ 84b2c397
......@@ -10,67 +10,6 @@
/* Description SMIO FMC130M_4CH functions */
disp_op_t fmc130m_4ch_leds_exp = {
.name = FMC130M_4CH_NAME_LEDS,
.opcode = FMC130M_4CH_OPCODE_LEDS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_si571_oe_exp = {
.name = FMC130M_4CH_NAME_SI571_OE,
.opcode = FMC130M_4CH_OPCODE_SI571_OE,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_pll_func_exp = {
.name = FMC130M_4CH_NAME_PLL_FUNCTION,
.opcode = FMC130M_4CH_OPCODE_PLL_FUNCTION,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_pll_status_exp = {
.name = FMC130M_4CH_NAME_PLL_STATUS,
.opcode = FMC130M_4CH_OPCODE_PLL_STATUS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_clk_sel_exp = {
.name = FMC130M_4CH_NAME_CLK_SEL,
.opcode = FMC130M_4CH_OPCODE_CLK_SEL,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_adc_rand_exp = {
.name = FMC130M_4CH_NAME_ADC_RAND,
.opcode = FMC130M_4CH_OPCODE_ADC_RAND,
......@@ -360,205 +299,8 @@ disp_op_t fmc130m_4ch_adc_dly3_exp = {
}
};
disp_op_t fmc130m_4ch_test_data_en_exp = {
.name = FMC130M_4CH_NAME_TEST_DATA_EN,
.opcode = FMC130M_4CH_OPCODE_TEST_DATA_EN,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_trig_dir_exp = {
.name = FMC130M_4CH_NAME_TRIG_DIR,
.opcode = FMC130M_4CH_OPCODE_TRIG_DIR,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_trig_term_exp = {
.name = FMC130M_4CH_NAME_TRIG_TERM,
.opcode = FMC130M_4CH_OPCODE_TRIG_TERM,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_trig_val_exp = {
.name = FMC130M_4CH_NAME_TRIG_VAL,
.opcode = FMC130M_4CH_OPCODE_TRIG_VAL,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_cfg_defaults_exp = {
.name = FMC130M_4CH_NAME_AD9510_CFG_DEFAULTS,
.opcode = FMC130M_4CH_OPCODE_AD9510_CFG_DEFAULTS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_pll_a_div_exp = {
.name = FMC130M_4CH_NAME_AD9510_PLL_A_DIV,
.opcode = FMC130M_4CH_OPCODE_AD9510_PLL_A_DIV,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_pll_b_div_exp = {
.name = FMC130M_4CH_NAME_AD9510_PLL_B_DIV,
.opcode = FMC130M_4CH_OPCODE_AD9510_PLL_B_DIV,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_pll_prescaler_exp = {
.name = FMC130M_4CH_NAME_AD9510_PLL_PRESCALER,
.opcode = FMC130M_4CH_OPCODE_AD9510_PLL_PRESCALER,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_r_div_exp = {
.name = FMC130M_4CH_NAME_AD9510_R_DIV,
.opcode = FMC130M_4CH_OPCODE_AD9510_R_DIV,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_pll_pdown_exp = {
.name = FMC130M_4CH_NAME_AD9510_PLL_PDOWN,
.opcode = FMC130M_4CH_OPCODE_AD9510_PLL_PDOWN,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_mux_status_exp = {
.name = FMC130M_4CH_NAME_AD9510_MUX_STATUS,
.opcode = FMC130M_4CH_OPCODE_AD9510_MUX_STATUS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_cp_current_exp = {
.name = FMC130M_4CH_NAME_AD9510_CP_CURRENT,
.opcode = FMC130M_4CH_OPCODE_AD9510_CP_CURRENT,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_outputs_exp = {
.name = FMC130M_4CH_NAME_AD9510_OUTPUTS,
.opcode = FMC130M_4CH_OPCODE_AD9510_OUTPUTS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_ad9510_pll_clk_sel_exp = {
.name = FMC130M_4CH_NAME_AD9510_PLL_CLK_SEL,
.opcode = FMC130M_4CH_OPCODE_AD9510_PLL_CLK_SEL,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_si571_set_freq_exp = {
.name = FMC130M_4CH_NAME_SI571_SET_FREQ,
.opcode = FMC130M_4CH_OPCODE_SI571_SET_FREQ,
.retval = DISP_ARG_END,
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_DOUBLE, double),
DISP_ARG_END
}
};
disp_op_t fmc130m_4ch_si571_get_defaults_exp = {
.name = FMC130M_4CH_NAME_SI571_GET_DEFAULTS,
.opcode = FMC130M_4CH_OPCODE_SI571_GET_DEFAULTS,
.retval = DISP_ARG_END,
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_DOUBLE, double),
DISP_ARG_END
}
};
/* Exported function description */
const disp_op_t *fmc130m_4ch_exp_ops [] = {
&fmc130m_4ch_leds_exp,
&fmc130m_4ch_si571_oe_exp,
&fmc130m_4ch_pll_func_exp,
&fmc130m_4ch_pll_status_exp,
&fmc130m_4ch_clk_sel_exp,
&fmc130m_4ch_adc_rand_exp,
&fmc130m_4ch_adc_dith_exp,
&fmc130m_4ch_adc_shdn_exp,
......@@ -583,22 +325,6 @@ const disp_op_t *fmc130m_4ch_exp_ops [] = {
&fmc130m_4ch_adc_dly1_exp,
&fmc130m_4ch_adc_dly2_exp,
&fmc130m_4ch_adc_dly3_exp,
&fmc130m_4ch_test_data_en_exp,
&fmc130m_4ch_trig_dir_exp,
&fmc130m_4ch_trig_term_exp,
&fmc130m_4ch_trig_val_exp,
&fmc130m_4ch_ad9510_cfg_defaults_exp,
&fmc130m_4ch_ad9510_pll_a_div_exp,
&fmc130m_4ch_ad9510_pll_b_div_exp,
&fmc130m_4ch_ad9510_pll_prescaler_exp,
&fmc130m_4ch_ad9510_r_div_exp,
&fmc130m_4ch_ad9510_pll_pdown_exp,
&fmc130m_4ch_ad9510_mux_status_exp,
&fmc130m_4ch_ad9510_cp_current_exp,
&fmc130m_4ch_ad9510_outputs_exp,
&fmc130m_4ch_ad9510_pll_clk_sel_exp,
&fmc130m_4ch_si571_set_freq_exp,
&fmc130m_4ch_si571_get_defaults_exp,
NULL
};
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exports.h
View file @ 84b2c397
......@@ -10,11 +10,6 @@
#include "disptable.h"
extern disp_op_t fmc130m_4ch_leds_exp;
extern disp_op_t fmc130m_4ch_si571_oe_exp;
extern disp_op_t fmc130m_4ch_pll_func_exp;
extern disp_op_t fmc130m_4ch_pll_status_exp;
extern disp_op_t fmc130m_4ch_clk_sel_exp;
extern disp_op_t fmc130m_4ch_adc_rand_exp;
extern disp_op_t fmc130m_4ch_adc_dith_exp;
extern disp_op_t fmc130m_4ch_adc_shdn_exp;
......@@ -39,22 +34,6 @@ extern disp_op_t fmc130m_4ch_adc_dly0_exp;
extern disp_op_t fmc130m_4ch_adc_dly1_exp;
extern disp_op_t fmc130m_4ch_adc_dly2_exp;
extern disp_op_t fmc130m_4ch_adc_dly3_exp;
extern disp_op_t fmc130m_4ch_test_data_en_exp;
extern disp_op_t fmc130m_4ch_trig_dir_exp;
extern disp_op_t fmc130m_4ch_trig_term_exp;
extern disp_op_t fmc130m_4ch_trig_val_exp;
extern disp_op_t fmc130m_4ch_ad9510_cfg_defaults_exp;
extern disp_op_t fmc130m_4ch_ad9510_pll_a_div_exp;
extern disp_op_t fmc130m_4ch_ad9510_pll_b_div_exp;
extern disp_op_t fmc130m_4ch_ad9510_pll_prescaler_exp;
extern disp_op_t fmc130m_4ch_ad9510_r_div_exp;
extern disp_op_t fmc130m_4ch_ad9510_pll_pdown_exp;
extern disp_op_t fmc130m_4ch_ad9510_mux_status_exp;
extern disp_op_t fmc130m_4ch_ad9510_cp_current_exp;
extern disp_op_t fmc130m_4ch_ad9510_outputs_exp;
extern disp_op_t fmc130m_4ch_ad9510_pll_clk_sel_exp;
extern disp_op_t fmc130m_4ch_si571_set_freq_exp;
extern disp_op_t fmc130m_4ch_si571_get_defaults_exp;
extern const disp_op_t *fmc130m_4ch_exp_ops [];
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_codes.h
View file @ 84b2c397
......@@ -12,16 +12,6 @@
#define FMC250M_4CH_OPCODE_TYPE uint32_t
#define FMC250M_4CH_OPCODE_SIZE (sizeof (FMC250M_4CH_OPCODE_TYPE))
#define FMC250M_4CH_OPCODE_LEDS 0
#define FMC250M_4CH_NAME_LEDS "fmc250m_4ch_leds"
#define FMC250M_4CH_OPCODE_SI571_OE 1
#define FMC250M_4CH_NAME_SI571_OE "fmc250m_4ch_si571_oe"
#define FMC250M_4CH_OPCODE_PLL_FUNCTION 2
#define FMC250M_4CH_NAME_PLL_FUNCTION "fmc250m_4ch_pll_function"
#define FMC250M_4CH_OPCODE_PLL_STATUS 3
#define FMC250M_4CH_NAME_PLL_STATUS "fmc250m_4ch_pll_status"
#define FMC250M_4CH_OPCODE_CLK_SEL 4
#define FMC250M_4CH_NAME_CLK_SEL "fmc250m_4ch_clk_sel"
#if 0
#define FMC250M_4CH_OPCODE_ADC_RAND 5
#define FMC250M_4CH_NAME_ADC_RAND "fmc250m_4ch_adc_rand"
......@@ -74,38 +64,6 @@
#define FMC250M_4CH_OPCODE_ADC_DLY3 28
#define FMC250M_4CH_NAME_ADC_DLY3 "fmc250m_4ch_adc_dly3"
#endif
#define FMC250M_4CH_OPCODE_TEST_DATA_EN 29
#define FMC250M_4CH_NAME_TEST_DATA_EN "fmc250m_4ch_adc_test_data_en"
#define FMC250M_4CH_OPCODE_TRIG_DIR 30
#define FMC250M_4CH_NAME_TRIG_DIR "fmc250m_4ch_trig_dir"
#define FMC250M_4CH_OPCODE_TRIG_TERM 31
#define FMC250M_4CH_NAME_TRIG_TERM "fmc250m_4ch_trig_term"
#define FMC250M_4CH_OPCODE_TRIG_VAL 32
#define FMC250M_4CH_NAME_TRIG_VAL "fmc250m_4ch_trig_val"
#define FMC250M_4CH_OPCODE_AD9510_CFG_DEFAULTS 33
#define FMC250M_4CH_NAME_AD9510_CFG_DEFAULTS "fmc250m_4ch_ad9510_cfg_defaults"
#define FMC250M_4CH_OPCODE_AD9510_PLL_A_DIV 34
#define FMC250M_4CH_NAME_AD9510_PLL_A_DIV "fmc250m_4ch_ad9510_pll_a_div"
#define FMC250M_4CH_OPCODE_AD9510_PLL_B_DIV 35
#define FMC250M_4CH_NAME_AD9510_PLL_B_DIV "fmc250m_4ch_ad9510_pll_b_div"
#define FMC250M_4CH_OPCODE_AD9510_PLL_PRESCALER 36
#define FMC250M_4CH_NAME_AD9510_PLL_PRESCALER "fmc250m_4ch_ad9510_pll_prescaler"
#define FMC250M_4CH_OPCODE_AD9510_R_DIV 37
#define FMC250M_4CH_NAME_AD9510_R_DIV "fmc250m_4ch_ad9510_r_div"
#define FMC250M_4CH_OPCODE_AD9510_PLL_PDOWN 38
#define FMC250M_4CH_NAME_AD9510_PLL_PDOWN "fmc250m_4ch_ad9510_pll_pdown"
#define FMC250M_4CH_OPCODE_AD9510_MUX_STATUS 39
#define FMC250M_4CH_NAME_AD9510_MUX_STATUS "fmc250m_4ch_ad9510_mux_status"
#define FMC250M_4CH_OPCODE_AD9510_CP_CURRENT 40
#define FMC250M_4CH_NAME_AD9510_CP_CURRENT "fmc250m_4ch_ad9510_cp_current"
#define FMC250M_4CH_OPCODE_AD9510_OUTPUTS 41
#define FMC250M_4CH_NAME_AD9510_OUTPUTS "fmc250m_4ch_ad9510_outputs"
#define FMC250M_4CH_OPCODE_AD9510_PLL_CLK_SEL 42
#define FMC250M_4CH_NAME_AD9510_PLL_CLK_SEL "fmc250m_4ch_ad9510_pll_clk_sel"
#define FMC250M_4CH_OPCODE_SI571_SET_FREQ 43
#define FMC250M_4CH_NAME_SI571_SET_FREQ "fmc250m_4ch_si571_set_freq"
#define FMC250M_4CH_OPCODE_SI571_GET_DEFAULTS 44
#define FMC250M_4CH_NAME_SI571_GET_DEFAULTS "fmc250m_4ch_si571_get_defaults"
#define FMC250M_4CH_OPCODE_RST_ADCS 45
#define FMC250M_4CH_NAME_RST_ADCS "fmc250m_4ch_rst_adcs"
#define FMC250M_4CH_OPCODE_RST_DIV_ADCS 46
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_core.c
View file @ 84b2c397
......@@ -44,6 +44,7 @@ smio_fmc250m_4ch_t * smio_fmc250m_4ch_new (smio_t *parent)
smio_fmc250m_4ch_t *self = (smio_fmc250m_4ch_t *) zmalloc (sizeof *self);
ASSERT_ALLOC(self, err_self_alloc);
uint32_t inst_id = smio_get_inst_id (parent);
uint64_t base = smio_get_base (parent);
/* Check if Instance ID is within our expected limits */
ASSERT_TEST(inst_id < NUM_FMC250M_4CH_SMIOS, "Number of FMC250M_4CH SMIOs instances exceeded",
......@@ -138,48 +139,31 @@ smio_fmc250m_4ch_t * smio_fmc250m_4ch_new (smio_t *parent)
#endif
_smio_fmc250m_4ch_set_type (self, 0x0);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] Registering FMC_ADC_COMMON SMIO\n");
smio_register_sm (parent, 0x2403f569, base | FMC_250M_FMC_ADC_COMMON_OFFS, inst_id);
/* Now, initialize the FMC250M_4CH with the appropriate structures*/
if (self->type == TYPE_FMC250M_4CH_ACTIVE) {
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] AD9510 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc250m_4ch_ad9510_addr[inst_id],
inst_id);
self->smch_ad9510 = smch_ad9510_new (parent, FMC_250M_AD9510_SPI_OFFS,
fmc250m_4ch_ad9510_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_ad9510, err_smch_ad9510_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] SI571 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc250m_4ch_si571_addr[inst_id],
inst_id);
self->smch_si571 = smch_si57x_new (parent, FMC_250M_SI571_I2C_OFFS,
fmc250m_4ch_si571_addr[inst_id], 0);
ASSERT_ALLOC(self->smch_si571, err_smch_si571_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc250m_4ch_core] Active Board detected. "
"Registering FMC_ADC_ACTIVE SMIO\n");
smio_register_sm (parent, 0x88c67d9c, base | FMC_250M_FMC_ACTIVE_CLK_OFFS, inst_id);
}
else { /* PASSIVE or Unsupported*/
if (self->type != TYPE_FMC250M_4CH_PASSIVE) {
DBE_DEBUG (DBG_SM_IO | DBG_LVL_WARN,
"[sm_io:fmc250m_4ch_core] Unsupported FMC250M_4CH card (maybe EEPROM not configured?).\n"
"\t Defaulting to PASSIVE board\n");
}
self->smch_ad9510 = NULL;
self->smch_si571 = NULL;
}
return self;
err_smch_si571_alloc:
if (self->smch_ad9510 != NULL) {
smch_ad9510_destroy (&self->smch_ad9510);
}
err_smch_ad9510_alloc:
smch_24aa64_destroy (&self->smch_24aa64);
#if 0
err_smch_24aa64_alloc:
#endif
if (self->smch_pca9547 != NULL) {
smch_pca9547_destroy (&self->smch_pca9547);
}
#endif
#if 0
err_smch_pca9547_alloc:
#endif
......@@ -201,8 +185,6 @@ smio_err_e smio_fmc250m_4ch_destroy (smio_fmc250m_4ch_t **self_p)
if (*self_p) {
smio_fmc250m_4ch_t *self = *self_p;
smch_si57x_destroy (&self->smch_si571);
smch_ad9510_destroy (&self->smch_ad9510);
smch_24aa64_destroy (&self->smch_24aa64);
if (self->smch_pca9547 != NULL) {
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_core.h
View file @ 84b2c397
......@@ -8,8 +8,6 @@
#ifndef _SM_IO_FMC250M_4CH_CORE_H_
#define _SM_IO_FMC250M_4CH_CORE_H_
#define SMIO_AD9510_HANDLER(smio_handler) ((smch_ad9510_t *) smio_handler->smch_ad9510)
#define SMIO_SI57X_HANDLER(smio_handler) ((smch_si57x_t *) smio_handler->smch_si571)
#define SMIO_ISLA216P_HANDLER(smio_handler, inst) ((smch_isla216p_t *) smio_handler->smch_isla216p_adc[inst])
/* The follosing codes were generated via the following command:
......@@ -36,8 +34,6 @@ typedef struct {
smch_amc7823_t *smch_amc7823; /* AMC7823 chip handler */
#endif
smch_isla216p_t *smch_isla216p_adc[NUM_FMC250M_4CH_ISLA216P]; /* ISLA216P chip handlers */
smch_ad9510_t *smch_ad9510; /* AD9510 chip handler */
smch_si57x_t *smch_si571; /* SI571 chip handler */
smch_24aa64_t *smch_24aa64; /* 24AA64 chip handler */
smch_pca9547_t *smch_pca9547; /* FPGA I2C Switch */
} smio_fmc250m_4ch_t;
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.c
View file @ 84b2c397
......@@ -55,35 +55,6 @@ smio_err_e fmc250m_4ch_config_defaults (char *broker_endp, char *service,
log_file_name, SMIO_FMC250M_4CH_LIBBPMCLIENT_LOG_MODE);
ASSERT_ALLOC(config_client, err_alloc_client);
client_err = bpm_set_fmc_pll_function (config_client, service, FMC250M_4CH_DFLT_PLL_FUNC);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC PLL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_fmc_clk_sel (config_client, service, FMC250M_4CH_DFLT_CLK_SEL);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC CLK SEL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_trig_dir (config_client, service, FMC250M_4CH_DFLT_TRIG_DIR);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC TRIG DIR function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_ad9510_cfg_defaults (config_client, service, 0);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS ||
client_err == BPM_CLIENT_ERR_AGAIN, "Could not configure AD9510",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_defaults (config_client, service, FMC250M_4CH_DFLT_SI57X_FOUT_FACTORY);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not get Si571 defaults",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_set_freq (config_client, service, FMC250M_4CH_DFLT_SI57X_FOUT);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set Si571 frequency",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_oe (config_client, service, FMC250M_4CH_DFLT_SI571_OE);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not enable SI571 Output",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_rst_adcs (config_client, service, FMC250M_4CH_DFLT_RST_ADCS);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not reset ADCs",
err_param_set, SMIO_ERR_CONFIG_DFLT);
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.h
View file @ 84b2c397
......@@ -9,18 +9,8 @@
#define _FMC250M_4CH_DEFAULTS_H_
#include "sm_io_err.h"
#include "chips/si57x_regs.h"
#include "sm_ch_pca9547.h"
#define FMC250M_4CH_DFLT_PLL_FUNC 0x1
#define FMC250M_4CH_DFLT_CLK_SEL 0x0 /* Clock from FMC front panel */
#define FMC250M_4CH_DFLT_TRIG_DIR 0x0 /* Output direction */
#define FMC250M_4CH_DFLT_PCA9547_CFG SMCH_PCA9547_NO_CHANNEL /* No channel selected */
#define FMC250M_4CH_DFLT_SI571_OE 0x1
#define FMC250M_4CH_DFLT_SI57X_FOUT_FACTORY SI57X_FOUT_FACTORY_DFLT
#define FMC250M_4CH_DFLT_SI57X_FOUT 113040445 /* 113.040445 MHz default */
#define FMC250M_4CH_DFLT_RST_ADCS 0x1
#define FMC250M_4CH_DFLT_RST_DIV_ADCS 0x1
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exports.c
View file @ 84b2c397
......@@ -10,67 +10,6 @@
/* Description SMIO FMC250M_4CH functions */
disp_op_t fmc250m_4ch_leds_exp = {
.name = FMC250M_4CH_NAME_LEDS,
.opcode = FMC250M_4CH_OPCODE_LEDS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_si571_oe_exp = {
.name = FMC250M_4CH_NAME_SI571_OE,
.opcode = FMC250M_4CH_OPCODE_SI571_OE,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_pll_func_exp = {
.name = FMC250M_4CH_NAME_PLL_FUNCTION,
.opcode = FMC250M_4CH_OPCODE_PLL_FUNCTION,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_pll_status_exp = {
.name = FMC250M_4CH_NAME_PLL_STATUS,
.opcode = FMC250M_4CH_OPCODE_PLL_STATUS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_clk_sel_exp = {
.name = FMC250M_4CH_NAME_CLK_SEL,
.opcode = FMC250M_4CH_OPCODE_CLK_SEL,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_rst_adcs_exp = {
.name = FMC250M_4CH_NAME_RST_ADCS,
.opcode = FMC250M_4CH_OPCODE_RST_ADCS,
......@@ -388,198 +327,6 @@ disp_op_t fmc250m_4ch_adc_dly3_exp = {
};
#endif
disp_op_t fmc250m_4ch_test_data_en_exp = {
.name = FMC250M_4CH_NAME_TEST_DATA_EN,
.opcode = FMC250M_4CH_OPCODE_TEST_DATA_EN,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_trig_dir_exp = {
.name = FMC250M_4CH_NAME_TRIG_DIR,
.opcode = FMC250M_4CH_OPCODE_TRIG_DIR,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_trig_term_exp = {
.name = FMC250M_4CH_NAME_TRIG_TERM,
.opcode = FMC250M_4CH_OPCODE_TRIG_TERM,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_trig_val_exp = {
.name = FMC250M_4CH_NAME_TRIG_VAL,
.opcode = FMC250M_4CH_OPCODE_TRIG_VAL,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_cfg_defaults_exp = {
.name = FMC250M_4CH_NAME_AD9510_CFG_DEFAULTS,
.opcode = FMC250M_4CH_OPCODE_AD9510_CFG_DEFAULTS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_pll_a_div_exp = {
.name = FMC250M_4CH_NAME_AD9510_PLL_A_DIV,
.opcode = FMC250M_4CH_OPCODE_AD9510_PLL_A_DIV,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_pll_b_div_exp = {
.name = FMC250M_4CH_NAME_AD9510_PLL_B_DIV,
.opcode = FMC250M_4CH_OPCODE_AD9510_PLL_B_DIV,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_pll_prescaler_exp = {
.name = FMC250M_4CH_NAME_AD9510_PLL_PRESCALER,
.opcode = FMC250M_4CH_OPCODE_AD9510_PLL_PRESCALER,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_r_div_exp = {
.name = FMC250M_4CH_NAME_AD9510_R_DIV,
.opcode = FMC250M_4CH_OPCODE_AD9510_R_DIV,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_pll_pdown_exp = {
.name = FMC250M_4CH_NAME_AD9510_PLL_PDOWN,
.opcode = FMC250M_4CH_OPCODE_AD9510_PLL_PDOWN,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_mux_status_exp = {
.name = FMC250M_4CH_NAME_AD9510_MUX_STATUS,
.opcode = FMC250M_4CH_OPCODE_AD9510_MUX_STATUS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_cp_current_exp = {
.name = FMC250M_4CH_NAME_AD9510_CP_CURRENT,
.opcode = FMC250M_4CH_OPCODE_AD9510_CP_CURRENT,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_outputs_exp = {
.name = FMC250M_4CH_NAME_AD9510_OUTPUTS,
.opcode = FMC250M_4CH_OPCODE_AD9510_OUTPUTS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_ad9510_pll_clk_sel_exp = {
.name = FMC250M_4CH_NAME_AD9510_PLL_CLK_SEL,
.opcode = FMC250M_4CH_OPCODE_AD9510_PLL_CLK_SEL,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_si571_set_freq_exp = {
.name = FMC250M_4CH_NAME_SI571_SET_FREQ,
.opcode = FMC250M_4CH_OPCODE_SI571_SET_FREQ,
.retval = DISP_ARG_END,
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_DOUBLE, double),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_si571_get_defaults_exp = {
.name = FMC250M_4CH_NAME_SI571_GET_DEFAULTS,
.opcode = FMC250M_4CH_OPCODE_SI571_GET_DEFAULTS,
.retval = DISP_ARG_END,
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_DOUBLE, double),
DISP_ARG_END
}
};
disp_op_t fmc250m_4ch_test_mode0_exp = {
.name = FMC250M_4CH_NAME_TESTMODE0,
.opcode = FMC250M_4CH_OPCODE_TESTMODE0,
......@@ -630,11 +377,6 @@ disp_op_t fmc250m_4ch_test_mode3_exp = {
/* Exported function description */
const disp_op_t *fmc250m_4ch_exp_ops [] = {
&fmc250m_4ch_leds_exp,
&fmc250m_4ch_si571_oe_exp,
&fmc250m_4ch_pll_func_exp,
&fmc250m_4ch_pll_status_exp,
&fmc250m_4ch_clk_sel_exp,
#if 0
&fmc250m_4ch_adc_rand_exp,
&fmc250m_4ch_adc_dith_exp,
......@@ -663,22 +405,6 @@ const disp_op_t *fmc250m_4ch_exp_ops [] = {
&fmc250m_4ch_adc_dly2_exp,
&fmc250m_4ch_adc_dly3_exp,
#endif
&fmc250m_4ch_test_data_en_exp,
&fmc250m_4ch_trig_dir_exp,
&fmc250m_4ch_trig_term_exp,
&fmc250m_4ch_trig_val_exp,
&fmc250m_4ch_ad9510_cfg_defaults_exp,
&fmc250m_4ch_ad9510_pll_a_div_exp,
&fmc250m_4ch_ad9510_pll_b_div_exp,
&fmc250m_4ch_ad9510_pll_prescaler_exp,
&fmc250m_4ch_ad9510_r_div_exp,
&fmc250m_4ch_ad9510_pll_pdown_exp,
&fmc250m_4ch_ad9510_mux_status_exp,
&fmc250m_4ch_ad9510_cp_current_exp,
&fmc250m_4ch_ad9510_outputs_exp,
&fmc250m_4ch_ad9510_pll_clk_sel_exp,
&fmc250m_4ch_si571_set_freq_exp,
&fmc250m_4ch_si571_get_defaults_exp,
&fmc250m_4ch_rst_adcs_exp,
&fmc250m_4ch_rst_div_adcs_exp,
&fmc250m_4ch_test_mode0_exp,
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exports.h
View file @ 84b2c397
......@@ -10,11 +10,6 @@
#include "disptable.h"
extern disp_op_t fmc250m_4ch_leds_exp;
extern disp_op_t fmc250m_4ch_si571_oe_exp;
extern disp_op_t fmc250m_4ch_pll_func_exp;
extern disp_op_t fmc250m_4ch_pll_status_exp;
extern disp_op_t fmc250m_4ch_clk_sel_exp;
#if 0
extern disp_op_t fmc250m_4ch_adc_rand_exp;
extern disp_op_t fmc250m_4ch_adc_dith_exp;
......@@ -43,22 +38,6 @@ extern disp_op_t fmc250m_4ch_adc_dly1_exp;
extern disp_op_t fmc250m_4ch_adc_dly2_exp;
extern disp_op_t fmc250m_4ch_adc_dly3_exp;
#endif
extern disp_op_t fmc250m_4ch_test_data_en_exp;
extern disp_op_t fmc250m_4ch_trig_dir_exp;
extern disp_op_t fmc250m_4ch_trig_term_exp;
extern disp_op_t fmc250m_4ch_trig_val_exp;
extern disp_op_t fmc250m_4ch_ad9510_cfg_defaults_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_a_div_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_b_div_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_prescaler_exp;
extern disp_op_t fmc250m_4ch_ad9510_r_div_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_pdown_exp;
extern disp_op_t fmc250m_4ch_ad9510_mux_status_exp;
extern disp_op_t fmc250m_4ch_ad9510_cp_current_exp;
extern disp_op_t fmc250m_4ch_ad9510_outputs_exp;
extern disp_op_t fmc250m_4ch_ad9510_pll_clk_sel_exp;
extern disp_op_t fmc250m_4ch_si571_set_freq_exp;
extern disp_op_t fmc250m_4ch_si571_get_defaults_exp;
extern disp_op_t fmc250m_4ch_rst_adcs_exp;
extern disp_op_t fmc250m_4ch_rst_div_adcs_exp;
extern disp_op_t fmc250m_4ch_test_mode0_exp;
......
src/sm_io/modules/fmc_active_clk/fmc_active_clk.mk 0 → 100644
View file @ 84b2c397
sm_io_fmc_active_clk_DIR = $(SRC_DIR)/sm_io/modules/fmc_active_clk
sm_io_fmc_active_clk_OBJS = $(sm_io_fmc_active_clk_DIR)/sm_io_fmc_active_clk_core.o \
$(sm_io_fmc_active_clk_DIR)/sm_io_fmc_active_clk_exp.o \
$(sm_io_fmc_active_clk_DIR)/sm_io_fmc_active_clk_exports.o \
$(sm_io_fmc_active_clk_DIR)/sm_io_fmc_active_clk_defaults.o
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_codes.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC_ACTIVE_CLK_CODES_H_
#define _SM_IO_FMC_ACTIVE_CLK_CODES_H_
/* Messaging OPCODES */
#define FMC_ACTIVE_CLK_OPCODE_TYPE uint32_t
#define FMC_ACTIVE_CLK_OPCODE_SIZE (sizeof (FMC_ACTIVE_CLK_OPCODE_TYPE))
#define FMC_ACTIVE_CLK_OPCODE_SI571_OE 0
#define FMC_ACTIVE_CLK_NAME_SI571_OE "fmc_active_clk_si571_oe"
#define FMC_ACTIVE_CLK_OPCODE_PLL_FUNCTION 1
#define FMC_ACTIVE_CLK_NAME_PLL_FUNCTION "fmc_active_clk_pll_function"
#define FMC_ACTIVE_CLK_OPCODE_PLL_STATUS 2
#define FMC_ACTIVE_CLK_NAME_PLL_STATUS "fmc_active_clk_pll_status"
#define FMC_ACTIVE_CLK_OPCODE_CLK_SEL 3
#define FMC_ACTIVE_CLK_NAME_CLK_SEL "fmc_active_clk_clk_sel"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_CFG_DEFAULTS 4
#define FMC_ACTIVE_CLK_NAME_AD9510_CFG_DEFAULTS "fmc_active_clk_ad9510_cfg_defaults"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_PLL_A_DIV 5
#define FMC_ACTIVE_CLK_NAME_AD9510_PLL_A_DIV "fmc_active_clk_ad9510_pll_a_div"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_PLL_B_DIV 6
#define FMC_ACTIVE_CLK_NAME_AD9510_PLL_B_DIV "fmc_active_clk_ad9510_pll_b_div"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_PLL_PRESCALER 7
#define FMC_ACTIVE_CLK_NAME_AD9510_PLL_PRESCALER "fmc_active_clk_ad9510_pll_prescaler"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_R_DIV 8
#define FMC_ACTIVE_CLK_NAME_AD9510_R_DIV "fmc_active_clk_ad9510_r_div"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_PLL_PDOWN 9
#define FMC_ACTIVE_CLK_NAME_AD9510_PLL_PDOWN "fmc_active_clk_ad9510_pll_pdown"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_MUX_STATUS 10
#define FMC_ACTIVE_CLK_NAME_AD9510_MUX_STATUS "fmc_active_clk_ad9510_mux_status"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_CP_CURRENT 11
#define FMC_ACTIVE_CLK_NAME_AD9510_CP_CURRENT "fmc_active_clk_ad9510_cp_current"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_OUTPUTS 12
#define FMC_ACTIVE_CLK_NAME_AD9510_OUTPUTS "fmc_active_clk_ad9510_outputs"
#define FMC_ACTIVE_CLK_OPCODE_AD9510_PLL_CLK_SEL 13
#define FMC_ACTIVE_CLK_NAME_AD9510_PLL_CLK_SEL "fmc_active_clk_ad9510_pll_clk_sel"
#define FMC_ACTIVE_CLK_OPCODE_SI571_SET_FREQ 14
#define FMC_ACTIVE_CLK_NAME_SI571_SET_FREQ "fmc_active_clk_si571_set_freq"
#define FMC_ACTIVE_CLK_OPCODE_SI571_GET_DEFAULTS 15
#define FMC_ACTIVE_CLK_NAME_SI571_GET_DEFAULTS "fmc_active_clk_si571_get_defaults"
#define FMC_ACTIVE_CLK_OPCODE_END 16
/* Messaging Reply OPCODES */
#define FMC_ACTIVE_CLK_REPLY_TYPE uint32_t
#define FMC_ACTIVE_CLK_REPLY_SIZE (sizeof (FMC_ACTIVE_CLK_REPLY_TYPE))
#define FMC_ACTIVE_CLK_OK 0 /* Operation was successful */
#define FMC_ACTIVE_CLK_ERR 1 /* Could not set/get value */
#define FMC_ACTIVE_CLK_UNINPL 2 /* Unimplemented function or operation */
#define FMC_ACTIVE_CLK_REPLY_END 3 /* End marker */
#endif
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_core.c 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_fmc_active_clk_defaults.h"
#include "sm_io_fmc_active_clk_core.h"
#include "chips_addr.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_fmc_active_clk_core]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_fmc_active_clk_core]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io_fmc_active_clk_core]", \
smio_err_str (err_type))
/* Creates a new instance of Device Information */
smio_fmc_active_clk_t * smio_fmc_active_clk_new (smio_t *parent)
{
assert (parent);
smio_fmc_active_clk_t *self = (smio_fmc_active_clk_t *) zmalloc (sizeof *self);
ASSERT_ALLOC(self, err_self_alloc);
uint32_t inst_id = smio_get_inst_id (parent);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc_active_clk_core] AD9510 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc_active_clk_ad9510_addr,
inst_id);
self->smch_ad9510 = smch_ad9510_new (parent, FMC_ACTIVE_CLK_AD9510_SPI_OFFS,
fmc_active_clk_ad9510_addr, 0);
ASSERT_ALLOC(self->smch_ad9510, err_smch_ad9510_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc_active_clk_core] SI571 initializing, "
"addr: 0x%08X, Inst ID: %u\n", fmc_active_clk_si571_addr,
inst_id);
self->smch_si571 = smch_si57x_new (parent, FMC_ACTIVE_CLK_SI571_I2C_OFFS,
fmc_active_clk_si571_addr, 0);
ASSERT_ALLOC(self->smch_si571, err_smch_si571_alloc);
return self;
err_smch_si571_alloc:
if (self->smch_ad9510 != NULL) {
smch_ad9510_destroy (&self->smch_ad9510);
}
err_smch_ad9510_alloc:
free (self);
err_self_alloc:
return NULL;
}
/* Destroy an instance of the Device Information */
smio_err_e smio_fmc_active_clk_destroy (smio_fmc_active_clk_t **self_p)
{
assert (self_p);
if (*self_p) {
smio_fmc_active_clk_t *self = *self_p;
smch_si57x_destroy (&self->smch_si571);
smch_ad9510_destroy (&self->smch_ad9510);
free (self);
*self_p = NULL;
}
return SMIO_SUCCESS;
}
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_core.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC_ACTIVE_CLK_CORE_H_
#define _SM_IO_FMC_ACTIVE_CLK_CORE_H_
#define SMIO_AD9510_HANDLER(smio_handler) ((smch_ad9510_t *) smio_handler->smch_ad9510)
#define SMIO_SI57X_HANDLER(smio_handler) ((smch_si57x_t *) smio_handler->smch_si571)
typedef struct {
smch_ad9510_t *smch_ad9510; /* AD9510 chip handler */
smch_si57x_t *smch_si571; /* SI571 chip handler */
} smio_fmc_active_clk_t;
/***************** Our methods *****************/
/* Creates a new instance of the smio realization */
smio_fmc_active_clk_t * smio_fmc_active_clk_new (smio_t *parent);
/* Destroys the smio realization */
smio_err_e smio_fmc_active_clk_destroy (smio_fmc_active_clk_t **self_p);
#endif
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_defaults.c 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_fmc_active_clk_defaults.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:fmc_active_clk_defaults]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:fmc_active_clk_defaults]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io:fmc_active_clk_defaults]", \
smio_err_str (err_type))
#define SMIO_FMC_ACTIVE_CLK_LIBBPMCLIENT_LOG_MODE "a"
/* We use the actual libclient to send and configure our default values,
* maintaining internal consistency. So, in fact, we are sending ourselves
* a message containing the default values. Because of this approach, we
* only get to default our values when the functions are already exported
* to the broker, which happens on a late stage. This could cause a fast
* client to get an inconsistent state from our server */
/* TODO: Avoid exporting the functions before we have initialized
* our server with the default values */
smio_err_e fmc_active_clk_config_defaults (char *broker_endp, char *service,
const char *log_file_name)
{
(void) log_file_name;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:fmc_active_clk_defaults] Configuring SMIO "
"FMC_ACTIVE_CLK with default values ...\n");
bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
smio_err_e err = SMIO_SUCCESS;
bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
log_file_name, SMIO_FMC_ACTIVE_CLK_LIBBPMCLIENT_LOG_MODE);
ASSERT_ALLOC(config_client, err_alloc_client);
client_err = bpm_set_fmc_pll_function (config_client, service, FMC_ACTIVE_CLK_DFLT_PLL_FUNC);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC PLL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_fmc_clk_sel (config_client, service, FMC_ACTIVE_CLK_DFLT_CLK_SEL);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set FMC CLK SEL function",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_ad9510_cfg_defaults (config_client, service, 0);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS ||
client_err == BPM_CLIENT_ERR_AGAIN, "Could not configure AD9510",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_defaults (config_client, service, FMC_ACTIVE_CLK_DFLT_SI57X_FOUT_FACTORY);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not get Si571 defaults",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_set_freq (config_client, service, FMC_ACTIVE_CLK_DFLT_SI57X_FOUT);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set Si571 frequency",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = bpm_set_si571_oe (config_client, service, FMC_ACTIVE_CLK_DFLT_SI571_OE);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not enable SI571 Output",
err_param_set, SMIO_ERR_CONFIG_DFLT);
err_param_set:
bpm_client_destroy (&config_client);
err_alloc_client:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:fmc_active_clk_defaults] Exiting Config thread %s\n",
service);
return err;
}
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_defaults.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _FMC_ACTIVE_CLK_DEFAULTS_H_
#define _FMC_ACTIVE_CLK_DEFAULTS_H_
#include "sm_io_err.h"
#include "chips/si57x_regs.h"
#define FMC_ACTIVE_CLK_DFLT_PLL_FUNC 0x1
#define FMC_ACTIVE_CLK_DFLT_CLK_SEL 0x0 /* Clock from FMC front panel */
#define FMC_ACTIVE_CLK_DFLT_SI571_OE 0x1
#define FMC_ACTIVE_CLK_DFLT_SI57X_FOUT_FACTORY SI57X_FOUT_FACTORY_DFLT
#define FMC_ACTIVE_CLK_DFLT_SI57X_FOUT 113040445 /* 113.040445 MHz default */
smio_err_e fmc_active_clk_config_defaults (char *broker_endp, char *service,
const char *log_file_name);
#endif
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_exp.c 0 → 100644
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src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_exp.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _FMC_ACTIVE_CLK_H_
#define _FMC_ACTIVE_CLK_H_
/* Known modules IDs (from SDB records defined in FPGA) */
#define FMC_ACTIVE_CLK_SDB_DEVID 0x88c67d9c
#define FMC_ACTIVE_CLK_SDB_NAME "FMC_ACTIVE_CLK"
extern const smio_bootstrap_ops_t fmc_active_clk_bootstrap_ops;
#endif
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_exports.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC_ACTIVE_CLK_EXPORTS_H_
#define _SM_IO_FMC_ACTIVE_CLK_EXPORTS_H_
#include "disptable.h"
extern disp_op_t fmc_active_clk_si571_oe_exp;
extern disp_op_t fmc_active_clk_pll_func_exp;
extern disp_op_t fmc_active_clk_pll_status_exp;
extern disp_op_t fmc_active_clk_clk_sel_exp;
extern disp_op_t fmc_active_clk_ad9510_cfg_defaults_exp;
extern disp_op_t fmc_active_clk_ad9510_pll_a_div_exp;
extern disp_op_t fmc_active_clk_ad9510_pll_b_div_exp;
extern disp_op_t fmc_active_clk_ad9510_pll_prescaler_exp;
extern disp_op_t fmc_active_clk_ad9510_r_div_exp;
extern disp_op_t fmc_active_clk_ad9510_pll_pdown_exp;
extern disp_op_t fmc_active_clk_ad9510_mux_status_exp;
extern disp_op_t fmc_active_clk_ad9510_cp_current_exp;
extern disp_op_t fmc_active_clk_ad9510_outputs_exp;
extern disp_op_t fmc_active_clk_ad9510_pll_clk_sel_exp;
extern disp_op_t fmc_active_clk_si571_set_freq_exp;
extern disp_op_t fmc_active_clk_si571_get_defaults_exp;
extern const disp_op_t *fmc_active_clk_exp_ops [];
#endif
src/sm_io/modules/fmc_adc_common/fmc_adc_common.mk 0 → 100644
View file @ 84b2c397
sm_io_fmc_adc_common_DIR = $(SRC_DIR)/sm_io/modules/fmc_adc_common
sm_io_fmc_adc_common_OBJS = $(sm_io_fmc_adc_common_DIR)/sm_io_fmc_adc_common_core.o \
$(sm_io_fmc_adc_common_DIR)/sm_io_fmc_adc_common_exp.o \
$(sm_io_fmc_adc_common_DIR)/sm_io_fmc_adc_common_exports.o \
$(sm_io_fmc_adc_common_DIR)/sm_io_fmc_adc_common_defaults.o
src/sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_codes.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC_ADC_COMMON_CODES_H_
#define _SM_IO_FMC_ADC_COMMON_CODES_H_
/* Messaging OPCODES */
#define FMC_ADC_COMMON_OPCODE_TYPE uint32_t
#define FMC_ADC_COMMON_OPCODE_SIZE (sizeof (FMC_ADC_COMMON_OPCODE_TYPE))
#define FMC_ADC_COMMON_OPCODE_LEDS 0
#define FMC_ADC_COMMON_NAME_LEDS "fmc_adc_common_leds"
#define FMC_ADC_COMMON_OPCODE_TEST_DATA_EN 1
#define FMC_ADC_COMMON_NAME_TEST_DATA_EN "fmc_adc_common_adc_test_data_en"
#define FMC_ADC_COMMON_OPCODE_TRIG_DIR 2
#define FMC_ADC_COMMON_NAME_TRIG_DIR "fmc_adc_common_trig_dir"
#define FMC_ADC_COMMON_OPCODE_TRIG_TERM 3
#define FMC_ADC_COMMON_NAME_TRIG_TERM "fmc_adc_common_trig_term"
#define FMC_ADC_COMMON_OPCODE_TRIG_VAL 4
#define FMC_ADC_COMMON_NAME_TRIG_VAL "fmc_adc_common_trig_val"
#define FMC_ADC_COMMON_OPCODE_END 5
/* Messaging Reply OPCODES */
#define FMC_ADC_COMMON_REPLY_TYPE uint32_t
#define FMC_ADC_COMMON_REPLY_SIZE (sizeof (FMC_ADC_COMMON_REPLY_TYPE))
#define FMC_ADC_COMMON_OK 0 /* Operation was successful */
#define FMC_ADC_COMMON_ERR 1 /* Could not set/get value */
#define FMC_ADC_COMMON_UNINPL 2 /* Unimplemented function or operation */
#define FMC_ADC_COMMON_REPLY_END 3 /* End marker */
#endif
src/sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_core.c 0 → 100644
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src/sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_core.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_FMC_ADC_COMMON_CORE_H_
#define _SM_IO_FMC_ADC_COMMON_CORE_H_
typedef struct {
const uint32_t example;
} smio_fmc_adc_common_t;
/***************** Our methods *****************/
/* Creates a new instance of the smio realization */
smio_fmc_adc_common_t * smio_fmc_adc_common_new (smio_t *parent);
/* Destroys the smio realization */
smio_err_e smio_fmc_adc_common_destroy (smio_fmc_adc_common_t **self_p);
#endif
src/sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_defaults.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _FMC_ADC_COMMON_DEFAULTS_H_
#define _FMC_ADC_COMMON_DEFAULTS_H_
#include "sm_io_err.h"
#define FMC_ADC_COMMON_DFLT_TRIG_DIR 0x0 /* Output direction */
smio_err_e fmc_adc_common_config_defaults (char *broker_endp, char *service,
const char *log_file_name);
#endif
src/sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_exp.c 0 → 100644
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This diff is collapsed.
src/sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_exp.h 0 → 100644
View file @ 84b2c397
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _FMC_ADC_COMMON_H_
#define _FMC_ADC_COMMON_H_
/* Known modules IDs (from SDB records defined in FPGA) */
#define FMC_ADC_COMMON_SDB_DEVID 0x2403f569
#define FMC_ADC_COMMON_SDB_NAME "FMC_ADC_COMMON"
extern const smio_bootstrap_ops_t fmc_adc_common_bootstrap_ops;
#endif
src/sm_io/modules/modules.mk
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src/sm_io/modules/sm_io_codes.c
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src/sm_io/modules/sm_io_codes.h
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src/sm_io/sm_io.c
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src/sm_io/sm_io_bootstrap.c
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src/sm_io/sm_io_err.c
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