Skip to content

B
Beam Positoning Monitor - Software
Commit 9b00c780 authored by João Brito's avatar João Brito
Browse files
Options

sm_io/*/afc_timing: add new SMIO module for LNLS timing board

parent 81cf88a2
Hide whitespace changes
Inline Side-by-side
Showing with 2090 additions and 5 deletions
include/hw/wb_slave_afc_timing_regs.h 0 → 100644
View file @ 9b00c780
/*
Register definitions for slave core: AFC Timing Sirius
* File : wb_slave_afc_timing_regs.h
* Author : auto-generated by wbgen2 from wb_slave_afc_timing_sirius.wb
* Created : Wed Aug 10 10:53:04 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_afc_timing_sirius.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_SLAVE_AFC_TIMING_SIRIUS_WB
#define __WBGEN2_REGDEFS_WB_SLAVE_AFC_TIMING_SIRIUS_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: DDMTD average exponent */
/* definitions for field: DDMTD average exponent in reg: DDMTD average exponent */
#define TIMING_DDMTD_AVG_EXP_MASK WBGEN2_GEN_MASK(0, 4)
#define TIMING_DDMTD_AVG_EXP_SHIFT 0
#define TIMING_DDMTD_AVG_EXP_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define TIMING_DDMTD_AVG_EXP_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for register: Status */
/* definitions for field: Fiber link in reg: Status */
#define TIMING_STAT_LINK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX enable in reg: Status */
#define TIMING_STAT_RXEN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Ref clk locked in reg: Status */
#define TIMING_STAT_REFCLKLOCK WBGEN2_GEN_MASK(2, 1)
/* definitions for register: RTM Si570 RFREQ */
/* definitions for register: RTM Si570 RFREQ */
/* definitions for register: RTM Si570 N1 */
/* definitions for field: RTM Si570 N1 in reg: RTM Si570 N1 */
#define TIMING_RTM_N1_MASK WBGEN2_GEN_MASK(0, 7)
#define TIMING_RTM_N1_SHIFT 0
#define TIMING_RTM_N1_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define TIMING_RTM_N1_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: RTM Si570 HS_DIV in reg: RTM Si570 N1 */
#define TIMING_RTM_HS_DIV_MASK WBGEN2_GEN_MASK(7, 3)
#define TIMING_RTM_HS_DIV_SHIFT 7
#define TIMING_RTM_HS_DIV_W(value) WBGEN2_GEN_WRITE(value, 7, 3)
#define TIMING_RTM_HS_DIV_R(reg) WBGEN2_GEN_READ(reg, 7, 3)
/* definitions for register: AFC Si570 RFREQ */
/* definitions for register: AFC Si570 RFREQ */
/* definitions for register: AFC Si570 N1 */
/* definitions for field: AFC Si570 N1 in reg: AFC Si570 N1 */
#define TIMING_AFC_N1_MASK WBGEN2_GEN_MASK(0, 7)
#define TIMING_AFC_N1_SHIFT 0
#define TIMING_AFC_N1_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define TIMING_AFC_N1_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: AFC Si570 HS_DIV in reg: AFC Si570 N1 */
#define TIMING_AFC_HS_DIV_MASK WBGEN2_GEN_MASK(7, 3)
#define TIMING_AFC_HS_DIV_SHIFT 7
#define TIMING_AFC_HS_DIV_W(value) WBGEN2_GEN_WRITE(value, 7, 3)
#define TIMING_AFC_HS_DIV_R(reg) WBGEN2_GEN_READ(reg, 7, 3)
/* definitions for register: Proportional gain frequency register */
/* definitions for field: Proportional gain frequency in reg: Proportional gain frequency register */
#define TIMING_FREQ_KP_MASK WBGEN2_GEN_MASK(0, 8)
#define TIMING_FREQ_KP_SHIFT 0
#define TIMING_FREQ_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define TIMING_FREQ_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Integral gain frequency in reg: Proportional gain frequency register */
#define TIMING_FREQ_KI_MASK WBGEN2_GEN_MASK(8, 8)
#define TIMING_FREQ_KI_SHIFT 8
#define TIMING_FREQ_KI_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define TIMING_FREQ_KI_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: Phase feedback gain register */
/* definitions for field: Proportional gain phase in reg: Phase feedback gain register */
#define TIMING_PHASE_KP_MASK WBGEN2_GEN_MASK(0, 8)
#define TIMING_PHASE_KP_SHIFT 0
#define TIMING_PHASE_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define TIMING_PHASE_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Integral gain phase in reg: Phase feedback gain register */
#define TIMING_PHASE_KI_MASK WBGEN2_GEN_MASK(8, 8)
#define TIMING_PHASE_KI_SHIFT 8
#define TIMING_PHASE_KI_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define TIMING_PHASE_KI_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: Phase feedback bias register */
/* definitions for register: Event code 0 */
/* definitions for register: Event code 1 */
/* definitions for register: Event code 2 */
/* definitions for register: Event code 3 */
/* definitions for register: Event code 4 */
/* definitions for register: Event code 5 */
/* definitions for register: Event code 6 */
/* definitions for register: Event delay 0 */
/* definitions for register: Event delay 1 */
/* definitions for register: Event delay 2 */
/* definitions for register: Event delay 3 */
/* definitions for register: Event delay 4 */
/* definitions for register: Event delay 5 */
/* definitions for register: Event delay 6 */
/* definitions for register: Event width 0 */
/* definitions for register: Event width 1 */
/* definitions for register: Event width 2 */
/* definitions for register: Event width 3 */
/* definitions for register: Event width 4 */
/* definitions for register: Event width 5 */
/* definitions for register: Event width 6 */
/* [0x0]: REG DDMTD average exponent */
#define TIMING_REG_DDMTD 0x00000000
/* [0x4]: REG Status */
#define TIMING_REG_STAT 0x00000004
/* [0x8]: REG RTM Si570 RFREQ */
#define TIMING_REG_RTM_RFREQ_HI 0x00000008
/* [0xc]: REG RTM Si570 RFREQ */
#define TIMING_REG_RTM_RFREQ_LO 0x0000000c
/* [0x10]: REG RTM Si570 N1 */
#define TIMING_REG_RTM 0x00000010
/* [0x14]: REG AFC Si570 RFREQ */
#define TIMING_REG_AFC_RFREQ_HI 0x00000014
/* [0x18]: REG AFC Si570 RFREQ */
#define TIMING_REG_AFC_RFREQ_LO 0x00000018
/* [0x1c]: REG AFC Si570 N1 */
#define TIMING_REG_AFC 0x0000001c
/* [0x20]: REG Proportional gain frequency register */
#define TIMING_REG_FREQ 0x00000020
/* [0x24]: REG Phase feedback gain register */
#define TIMING_REG_PHASE 0x00000024
/* [0x28]: REG Phase feedback bias register */
#define TIMING_REG_PHASE_BIAS 0x00000028
/* [0x2c]: REG Event code 0 */
#define TIMING_REG_EVT_IN0 0x0000002c
/* [0x30]: REG Event code 1 */
#define TIMING_REG_EVT_IN1 0x00000030
/* [0x34]: REG Event code 2 */
#define TIMING_REG_EVT_IN2 0x00000034
/* [0x38]: REG Event code 3 */
#define TIMING_REG_EVT_IN3 0x00000038
/* [0x3c]: REG Event code 4 */
#define TIMING_REG_EVT_IN4 0x0000003c
/* [0x40]: REG Event code 5 */
#define TIMING_REG_EVT_IN5 0x00000040
/* [0x44]: REG Event code 6 */
#define TIMING_REG_EVT_IN6 0x00000044
/* [0x48]: REG Event delay 0 */
#define TIMING_REG_EVT_DLY0 0x00000048
/* [0x4c]: REG Event delay 1 */
#define TIMING_REG_EVT_DLY1 0x0000004c
/* [0x50]: REG Event delay 2 */
#define TIMING_REG_EVT_DLY2 0x00000050
/* [0x54]: REG Event delay 3 */
#define TIMING_REG_EVT_DLY3 0x00000054
/* [0x58]: REG Event delay 4 */
#define TIMING_REG_EVT_DLY4 0x00000058
/* [0x5c]: REG Event delay 5 */
#define TIMING_REG_EVT_DLY5 0x0000005c
/* [0x60]: REG Event delay 6 */
#define TIMING_REG_EVT_DLY6 0x00000060
/* [0x64]: REG Event width 0 */
#define TIMING_REG_EVT_WDT0 0x00000064
/* [0x68]: REG Event width 1 */
#define TIMING_REG_EVT_WDT1 0x00000068
/* [0x6c]: REG Event width 2 */
#define TIMING_REG_EVT_WDT2 0x0000006c
/* [0x70]: REG Event width 3 */
#define TIMING_REG_EVT_WDT3 0x00000070
/* [0x74]: REG Event width 4 */
#define TIMING_REG_EVT_WDT4 0x00000074
/* [0x78]: REG Event width 5 */
#define TIMING_REG_EVT_WDT5 0x00000078
/* [0x7c]: REG Event width 6 */
#define TIMING_REG_EVT_WDT6 0x0000007c
#endif
src/libs/libbpmclient/Makefile
View file @ 9b00c780
......@@ -106,7 +106,8 @@ OBJS_EXTERNAL = ../../sm_io/modules/sm_io_codes.o \
../../sm_io/modules/rffe/sm_io_rffe_exports.o \
../../sm_io/modules/afc_diag/sm_io_afc_diag_exports.o \
../../sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.o \
../../sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.o
../../sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.o \
../../sm_io/modules/afc_timing/sm_io_afc_timing_exports.o
# Project boards
boards_INCLUDE_DIRS = -I../../../include/boards/$(BOARD)
......@@ -127,6 +128,7 @@ INCLUDE_DIRS = -I. -Iinclude \
-I../../sm_io/modules/afc_diag \
-I../../sm_io/modules/trigger_iface \
-I../../sm_io/modules/trigger_mux \
-I../../sm_io/modules/afc_timing \
-I${PREFIX}/include
# Merge all flags. We expect tghese variables to be appended to the possible
......@@ -162,6 +164,7 @@ $(LIBNAME)_SMIO_CODES = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_codes.
../../sm_io/modules/afc_diag/sm_io_afc_diag_codes.h \
../../sm_io/modules/trigger_iface/sm_io_trigger_iface_codes.h \
../../sm_io/modules/trigger_mux/sm_io_trigger_mux_codes.h \
../../sm_io/modules/afc_timing/sm_io_afc_timing_codes.h \
../../sm_io/modules/sm_io_codes.h
$(LIBNAME)_SMIO_EXPORTS = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exports.h \
......@@ -174,7 +177,8 @@ $(LIBNAME)_SMIO_EXPORTS = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_expo
../../sm_io/modules/rffe/sm_io_rffe_exports.h \
../../sm_io/modules/afc_diag/sm_io_afc_diag_exports.h \
../../sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.h \
../../sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.h
../../sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.h \
../../sm_io/modules/afc_timing/sm_io_afc_timing_exports.h
# Copy specific acq_chan.h defintions according to the BOARD MACRO
$(LIBNAME)_ACQ_HEADERS_BASENAME = acq_chan
......
src/libs/libbpmclient/include/bpm_client_core.h
View file @ 9b00c780
......@@ -1034,6 +1034,178 @@ bpm_client_err_e bpm_get_trigger_transm_out_sel (bpm_client_t *self, char *servi
bpm_client_err_e func_polling (bpm_client_t *self, char *name,
char *service, uint32_t *input, uint32_t *output, int timeout);
/********************** AFC Timing Functions ********************/
/* Status functions */
bpm_client_err_e afc_timing_get_link_status (bpm_client_t *self, char *service,
uint32_t *link_status);
bpm_client_err_e afc_timing_get_rxen_status (bpm_client_t *self, char *service,
uint32_t *rxen_status);
bpm_client_err_e afc_timing_get_ref_clk_locked (bpm_client_t *self, char *service,
uint32_t *ref_clk_locked);
/* Event code channel 0 functions */
bpm_client_err_e afc_timing_set_evt_code_0 (bpm_client_t *self, char *service,
uint32_t evt_code_0);
bpm_client_err_e afc_timing_get_evt_code_0 (bpm_client_t *self, char *service,
uint32_t *evt_code_0);
/* Event code channel 1 functions */
bpm_client_err_e afc_timing_set_evt_code_1 (bpm_client_t *self, char *service,
uint32_t evt_code_1);
bpm_client_err_e afc_timing_get_evt_code_1 (bpm_client_t *self, char *service,
uint32_t *evt_code_1);
/* Event code channel 2 functions */
bpm_client_err_e afc_timing_set_evt_code_2 (bpm_client_t *self, char *service,
uint32_t evt_code_2);
bpm_client_err_e afc_timing_get_evt_code_2 (bpm_client_t *self, char *service,
uint32_t *evt_code_2);
/* Event code channel 3 functions */
bpm_client_err_e afc_timing_set_evt_code_3 (bpm_client_t *self, char *service,
uint32_t evt_code_3);
bpm_client_err_e afc_timing_get_evt_code_3 (bpm_client_t *self, char *service,
uint32_t *evt_code_3);
/* Event code channel 4 functions */
bpm_client_err_e afc_timing_set_evt_code_4 (bpm_client_t *self, char *service,
uint32_t evt_code_4);
bpm_client_err_e afc_timing_get_evt_code_4 (bpm_client_t *self, char *service,
uint32_t *evt_code_4);
/* Event code channel 5 functions */
bpm_client_err_e afc_timing_set_evt_code_5 (bpm_client_t *self, char *service,
uint32_t evt_code_5);
bpm_client_err_e afc_timing_get_evt_code_5 (bpm_client_t *self, char *service,
uint32_t *evt_code_5);
/* Event code channel 6 functions */
bpm_client_err_e afc_timing_set_evt_code_6 (bpm_client_t *self, char *service,
uint32_t evt_code_6);
bpm_client_err_e afc_timing_get_evt_code_6 (bpm_client_t *self, char *service,
uint32_t *evt_code_6);
/* Event delay channel 0 functions */
bpm_client_err_e afc_timing_set_evt_delay_0 (bpm_client_t *self, char *service,
uint32_t evt_delay_0);
bpm_client_err_e afc_timing_get_evt_delay_0 (bpm_client_t *self, char *service,
uint32_t *evt_delay_0);
/* Event delay channel 1 functions */
bpm_client_err_e afc_timing_set_evt_delay_1 (bpm_client_t *self, char *service,
uint32_t evt_delay_1);
bpm_client_err_e afc_timing_get_evt_delay_1 (bpm_client_t *self, char *service,
uint32_t *evt_delay_1);
/* Event delay channel 2 functions */
bpm_client_err_e afc_timing_set_evt_delay_2 (bpm_client_t *self, char *service,
uint32_t evt_delay_2);
bpm_client_err_e afc_timing_get_evt_delay_2 (bpm_client_t *self, char *service,
uint32_t *evt_delay_2);
/* Event delay channel 3 functions */
bpm_client_err_e afc_timing_set_evt_delay_3 (bpm_client_t *self, char *service,
uint32_t evt_delay_3);
bpm_client_err_e afc_timing_get_evt_delay_3 (bpm_client_t *self, char *service,
uint32_t *evt_delay_3);
/* Event delay channel 4 functions */
bpm_client_err_e afc_timing_set_evt_delay_4 (bpm_client_t *self, char *service,
uint32_t evt_delay_4);
bpm_client_err_e afc_timing_get_evt_delay_4 (bpm_client_t *self, char *service,
uint32_t *evt_delay_4);
/* Event delay channel 5 functions */
bpm_client_err_e afc_timing_set_evt_delay_5 (bpm_client_t *self, char *service,
uint32_t evt_delay_5);
bpm_client_err_e afc_timing_get_evt_delay_5 (bpm_client_t *self, char *service,
uint32_t *evt_delay_5);
/* Event delay channel 6 functions */
bpm_client_err_e afc_timing_set_evt_delay_6 (bpm_client_t *self, char *service,
uint32_t evt_delay_6);
bpm_client_err_e afc_timing_get_evt_delay_6 (bpm_client_t *self, char *service,
uint32_t *evt_delay_6);
/* Event width channel 0 functions */
bpm_client_err_e afc_timing_set_evt_width_0 (bpm_client_t *self, char *service,
uint32_t evt_width_0);
bpm_client_err_e afc_timing_get_evt_width_0 (bpm_client_t *self, char *service,
uint32_t *evt_width_0);
/* Event width channel 1 functions */
bpm_client_err_e afc_timing_set_evt_width_1 (bpm_client_t *self, char *service,
uint32_t evt_width_1);
bpm_client_err_e afc_timing_get_evt_width_1 (bpm_client_t *self, char *service,
uint32_t *evt_width_1);
/* Event width channel 2 functions */
bpm_client_err_e afc_timing_set_evt_width_2 (bpm_client_t *self, char *service,
uint32_t evt_width_2);
bpm_client_err_e afc_timing_get_evt_width_2 (bpm_client_t *self, char *service,
uint32_t *evt_width_2);
/* Event width channel 3 functions */
bpm_client_err_e afc_timing_set_evt_width_3 (bpm_client_t *self, char *service,
uint32_t evt_width_3);
bpm_client_err_e afc_timing_get_evt_width_3 (bpm_client_t *self, char *service,
uint32_t *evt_width_3);
/* Event width channel 4 functions */
bpm_client_err_e afc_timing_set_evt_width_4 (bpm_client_t *self, char *service,
uint32_t evt_width_4);
bpm_client_err_e afc_timing_get_evt_width_4 (bpm_client_t *self, char *service,
uint32_t *evt_width_4);
/* Event width channel 5 functions */
bpm_client_err_e afc_timing_set_evt_width_5 (bpm_client_t *self, char *service,
uint32_t evt_width_5);
bpm_client_err_e afc_timing_get_evt_width_5 (bpm_client_t *self, char *service,
uint32_t *evt_width_5);
/* Event width channel 6 functions */
bpm_client_err_e afc_timing_set_evt_width_6 (bpm_client_t *self, char *service,
uint32_t evt_width_6);
bpm_client_err_e afc_timing_get_evt_width_6 (bpm_client_t *self, char *service,
uint32_t *evt_width_6);
/* Proportional Gain of Frequency feedback functions */
bpm_client_err_e afc_timing_set_freq_kp (bpm_client_t *self, char *service,
uint32_t freq_kp);
bpm_client_err_e afc_timing_get_freq_kp (bpm_client_t *self, char *service,
uint32_t *freq_kp);
/* Integral Gain of Frequency feedback functions */
bpm_client_err_e afc_timing_set_freq_ki (bpm_client_t *self, char *service,
uint32_t freq_ki);
bpm_client_err_e afc_timing_get_freq_ki (bpm_client_t *self, char *service,
uint32_t *freq_ki);
/* Proportional Gain of Phase feedback functions */
bpm_client_err_e afc_timing_set_phase_kp (bpm_client_t *self, char *service,
uint32_t phase_kp);
bpm_client_err_e afc_timing_get_phase_kp (bpm_client_t *self, char *service,
uint32_t *phase_kp);
/* Integral Gain of Phase feedback functions */
bpm_client_err_e afc_timing_set_phase_ki (bpm_client_t *self, char *service,
uint32_t phase_ki);
bpm_client_err_e afc_timing_get_phase_ki (bpm_client_t *self, char *service,
uint32_t *phase_ki);
/* Phase Bias functions */
bpm_client_err_e afc_timing_set_phase_bias (bpm_client_t *self, char *service,
uint32_t phase_bias);
bpm_client_err_e afc_timing_get_phase_bias (bpm_client_t *self, char *service,
uint32_t *phase_bias);
/* Average Exponent funcrions */
bpm_client_err_e afc_timing_set_avg_exponent (bpm_client_t *self, char *service,
uint32_t avg_exponent);
bpm_client_err_e afc_timing_get_avg_exponent (bpm_client_t *self, char *service,
uint32_t *avg_exponent);
#ifdef __cplusplus
}
#endif
......
src/libs/libbpmclient/include/bpm_client_rw_param.h
View file @ 9b00c780
......@@ -25,12 +25,24 @@ extern "C" {
/* Read function name */
#define PARAM_FUNC_CLIENT_NAME_READ(reg) \
bpm_get ## _ ## reg
/* Write function name */
#define PARAM_FUNC_CLIENT_NAME_WRITE_MOD(module, reg) \
module ## _ ## set ## _ ## reg
/* Read function name */
#define PARAM_FUNC_CLIENT_NAME_READ_MOD(module, reg) \
module ## _ ## get ## _ ## reg
/* Write function declaration */
#define PARAM_FUNC_CLIENT_WRITE(reg) \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_WRITE(reg) (bpm_client_t *self, \
char *service, uint32_t reg)
#define PARAM_FUNC_CLIENT_WRITE_MOD(module, reg) \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_WRITE_MOD(module, reg) (bpm_client_t *self, \
char *service, uint32_t reg)
#define PARAM_FUNC_CLIENT_WRITE_BYTE(reg) \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_WRITE(reg) (bpm_client_t *self, \
char *service, uint8_t reg)
......@@ -44,7 +56,7 @@ extern "C" {
char *service, uint32_t param1, uint32_t param2)
#define PARAM_FUNC_CLIENT_WRITE_GEN(param) \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_WRITE(param) (bpm_client_t *self, \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_WRITE(param) (bpm_client_t *self, \
char *service, void *param, size_t size)
/* Read function declaration */
......@@ -52,6 +64,10 @@ extern "C" {
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_READ(reg) (bpm_client_t *self, \
char *service, uint32_t *reg)
#define PARAM_FUNC_CLIENT_READ_MOD(module, reg) \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_READ_MOD(module, reg) (bpm_client_t *self, \
char *service, uint32_t *reg)
#define PARAM_FUNC_CLIENT_READ_BYTE(reg) \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_READ(reg) (bpm_client_t *self, \
char *service, uint8_t *reg)
......
src/libs/libbpmclient/src/bpm_client_core.c
View file @ 9b00c780
......@@ -2132,3 +2132,321 @@ bpm_zsys_interrupted:
exit:
return err;
}
/**************** AFC Timing SMIO Functions ****************/
/* Fiber link status function */
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, link_status)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_LINK_STATUS, link_status);
}
/* RX enabled function */
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, rxen_status)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_RXEN_STATUS, rxen_status);
}
/* Reference Clock output locked */
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, ref_clk_locked)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_REF_CLK_LOCKED, ref_clk_locked);
}
/* Event Code Channel 0 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_code_0)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN0, evt_code_0);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_code_0)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN0, evt_code_0);
}
/* Event Code Channel 1 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_code_1)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN1, evt_code_1);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_code_1)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN1, evt_code_1);
}
/* Event Code Channel 2 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_code_2)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN2, evt_code_2);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_code_2)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN2, evt_code_2);
}
/* Event Code Channel 3 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_code_3)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN3, evt_code_3);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_code_3)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN3, evt_code_3);
}
/* Event Code Channel 4 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_code_4)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN4, evt_code_4);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_code_4)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN4, evt_code_4);
}
/* Event Code Channel 5 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_code_5)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN5, evt_code_5);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_code_5)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN5, evt_code_5);
}
/* Event Code Channel 6 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_code_6)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN6, evt_code_6);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_code_6)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_IN6, evt_code_6);
}
/* Event Delay Channel 0 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_delay_0)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY0, evt_delay_0);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_delay_0)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY0, evt_delay_0);
}
/* Event Delay Channel 1 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_delay_1)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY1, evt_delay_1);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_delay_1)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY1, evt_delay_1);
}
/* Event Delay Channel 2 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_delay_2)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY2, evt_delay_2);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_delay_2)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY2, evt_delay_2);
}
/* Event Delay Channel 3 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_delay_3)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY3, evt_delay_3);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_delay_3)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY3, evt_delay_3);
}
/* Event Delay Channel 4 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_delay_4)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY4, evt_delay_4);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_delay_4)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY4, evt_delay_4);
}
/* Event Delay Channel 5 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_delay_5)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY5, evt_delay_5);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_delay_5)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY5, evt_delay_5);
}
/* Event Delay Channel 6 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_delay_6)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY6, evt_delay_6);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_delay_6)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_DLY6, evt_delay_6);
}
/* Event Width Channel 0 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_width_0)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT0, evt_width_0);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_width_0)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT0, evt_width_0);
}
/* Event Width Channel 1 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_width_1)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT1, evt_width_1);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_width_1)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT1, evt_width_1);
}
/* Event Width Channel 2 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_width_2)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT2, evt_width_2);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_width_2)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT2, evt_width_2);
}
/* Event Width Channel 3 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_width_3)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT3, evt_width_3);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_width_3)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT3, evt_width_3);
}
/* Event Width Channel 4 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_width_4)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT4, evt_width_4);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_width_4)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT4, evt_width_4);
}
/* Event Width Channel 5 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_width_5)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT5, evt_width_5);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_width_5)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT5, evt_width_5);
}
/* Event Width Channel 6 functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, evt_width_6)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT6, evt_width_6);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, evt_width_6)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_EVT_WDT6, evt_width_6);
}
/* Proportional Gain of Frequency feedback functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, freq_kp)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_FREQ_KP, freq_kp);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, freq_kp)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_FREQ_KP, freq_kp);
}
/* Integral Gain of Frequency feedback functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, freq_ki)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_FREQ_KI, freq_ki);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, freq_ki)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_FREQ_KI, freq_ki);
}
/* Proportional Gain of Phase feedback functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, phase_kp)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_PHASE_KP, phase_kp);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, phase_kp)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_PHASE_KP, phase_kp);
}
/* Integral Gain of Phase feedback functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, phase_ki)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_PHASE_KI, phase_ki);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, phase_ki)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_PHASE_KI, phase_ki);
}
/* Phase Bias functions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, phase_bias)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_PHASE_BIAS, phase_bias);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, phase_bias)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_PHASE_BIAS, phase_bias);
}
/* Average Exponent funcrions */
PARAM_FUNC_CLIENT_WRITE_MOD(afc_timing, avg_exponent)
{
return param_client_write (self, service, AFC_TIMING_OPCODE_SET_GET_AVG_EXPONENT, avg_exponent);
}
PARAM_FUNC_CLIENT_READ_MOD(afc_timing, avg_exponent)
{
return param_client_read (self, service, AFC_TIMING_OPCODE_SET_GET_AVG_EXPONENT, avg_exponent);
}
src/sm_io/modules/afc_timing/afc_timing.mk 0 → 100644
View file @ 9b00c780
sm_io_afc_timing_DIR = $(SRC_DIR)/sm_io/modules/afc_timing
sm_io_afc_timing_OBJS = $(sm_io_afc_timing_DIR)/sm_io_afc_timing_core.o \
$(sm_io_afc_timing_DIR)/sm_io_afc_timing_exp.o \
$(sm_io_afc_timing_DIR)/sm_io_afc_timing_exports.o \
$(sm_io_afc_timing_DIR)/sm_io_afc_timing_defaults.o
src/sm_io/modules/afc_timing/sm_io_afc_timing_codes.h 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Joao Brito <joao.brito@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_AFC_TIMING_CODES_H_
#define _SM_IO_AFC_TIMING_CODES_H_
#include <inttypes.h>
/* Messaging OPCODES */
#define AFC_TIMING_OPCODE_TYPE uint32_t
#define AFC_TIMING_OPCODE_SIZE (sizeof (AFC_TIMING_OPCODE_TYPE))
#define AFC_TIMING_OPCODE_SET_GET_LINK_STATUS 0
#define AFC_TIMING_NAME_SET_GET_LINK_STATUS "afc_timing_set_get_link_status"
#define AFC_TIMING_OPCODE_SET_GET_RXEN_STATUS 1
#define AFC_TIMING_NAME_SET_GET_RXEN_STATUS "afc_timing_set_get_rxen_status"
#define AFC_TIMING_OPCODE_SET_GET_REF_CLK_LOCKED 2
#define AFC_TIMING_NAME_SET_GET_REF_CLK_LOCKED "afc_timing_set_get_ref_clk_locked"
#define AFC_TIMING_OPCODE_SET_GET_EVT_IN0 3
#define AFC_TIMING_NAME_SET_GET_EVT_IN0 "afc_timing_set_get_evt_code_0"
#define AFC_TIMING_OPCODE_SET_GET_EVT_IN1 4
#define AFC_TIMING_NAME_SET_GET_EVT_IN1 "afc_timing_set_get_evt_code_1"
#define AFC_TIMING_OPCODE_SET_GET_EVT_IN2 5
#define AFC_TIMING_NAME_SET_GET_EVT_IN2 "afc_timing_set_get_evt_code_2"
#define AFC_TIMING_OPCODE_SET_GET_EVT_IN3 6
#define AFC_TIMING_NAME_SET_GET_EVT_IN3 "afc_timing_set_get_evt_code_3"
#define AFC_TIMING_OPCODE_SET_GET_EVT_IN4 7
#define AFC_TIMING_NAME_SET_GET_EVT_IN4 "afc_timing_set_get_evt_code_4"
#define AFC_TIMING_OPCODE_SET_GET_EVT_IN5 8
#define AFC_TIMING_NAME_SET_GET_EVT_IN5 "afc_timing_set_get_evt_code_5"
#define AFC_TIMING_OPCODE_SET_GET_EVT_IN6 9
#define AFC_TIMING_NAME_SET_GET_EVT_IN6 "afc_timing_set_get_evt_code_6"
#define AFC_TIMING_OPCODE_SET_GET_EVT_DLY0 10
#define AFC_TIMING_NAME_SET_GET_EVT_DLY0 "afc_timing_set_get_evt_delay_0"
#define AFC_TIMING_OPCODE_SET_GET_EVT_DLY1 11
#define AFC_TIMING_NAME_SET_GET_EVT_DLY1 "afc_timing_set_get_evt_delay_1"
#define AFC_TIMING_OPCODE_SET_GET_EVT_DLY2 12
#define AFC_TIMING_NAME_SET_GET_EVT_DLY2 "afc_timing_set_get_evt_delay_2"
#define AFC_TIMING_OPCODE_SET_GET_EVT_DLY3 13
#define AFC_TIMING_NAME_SET_GET_EVT_DLY3 "afc_timing_set_get_evt_delay_3"
#define AFC_TIMING_OPCODE_SET_GET_EVT_DLY4 14
#define AFC_TIMING_NAME_SET_GET_EVT_DLY4 "afc_timing_set_get_evt_delay_4"
#define AFC_TIMING_OPCODE_SET_GET_EVT_DLY5 15
#define AFC_TIMING_NAME_SET_GET_EVT_DLY5 "afc_timing_set_get_evt_delay_5"
#define AFC_TIMING_OPCODE_SET_GET_EVT_DLY6 16
#define AFC_TIMING_NAME_SET_GET_EVT_DLY6 "afc_timing_set_get_evt_delay_6"
#define AFC_TIMING_OPCODE_SET_GET_EVT_WDT0 17
#define AFC_TIMING_NAME_SET_GET_EVT_WDT0 "afc_timing_set_get_evt_width_0"
#define AFC_TIMING_OPCODE_SET_GET_EVT_WDT1 18
#define AFC_TIMING_NAME_SET_GET_EVT_WDT1 "afc_timing_set_get_evt_width_1"
#define AFC_TIMING_OPCODE_SET_GET_EVT_WDT2 19
#define AFC_TIMING_NAME_SET_GET_EVT_WDT2 "afc_timing_set_get_evt_width_2"
#define AFC_TIMING_OPCODE_SET_GET_EVT_WDT3 20
#define AFC_TIMING_NAME_SET_GET_EVT_WDT3 "afc_timing_set_get_evt_width_3"
#define AFC_TIMING_OPCODE_SET_GET_EVT_WDT4 21
#define AFC_TIMING_NAME_SET_GET_EVT_WDT4 "afc_timing_set_get_evt_width_4"
#define AFC_TIMING_OPCODE_SET_GET_EVT_WDT5 22
#define AFC_TIMING_NAME_SET_GET_EVT_WDT5 "afc_timing_set_get_evt_width_5"
#define AFC_TIMING_OPCODE_SET_GET_EVT_WDT6 23
#define AFC_TIMING_NAME_SET_GET_EVT_WDT6 "afc_timing_set_get_evt_width_6"
#define AFC_TIMING_OPCODE_SET_GET_FREQ_KP 24
#define AFC_TIMING_NAME_SET_GET_FREQ_KP "afc_timing_set_get_freq_kp"
#define AFC_TIMING_OPCODE_SET_GET_FREQ_KI 25
#define AFC_TIMING_NAME_SET_GET_FREQ_KI "afc_timing_set_get_freq_ki"
#define AFC_TIMING_OPCODE_SET_GET_PHASE_KP 26
#define AFC_TIMING_NAME_SET_GET_PHASE_KP "afc_timing_set_get_phase_kp"
#define AFC_TIMING_OPCODE_SET_GET_PHASE_KI 27
#define AFC_TIMING_NAME_SET_GET_PHASE_KI "afc_timing_set_get_phase_ki"
#define AFC_TIMING_OPCODE_SET_GET_PHASE_BIAS 28
#define AFC_TIMING_NAME_SET_GET_PHASE_BIAS "afc_timing_set_get_phase_bias"
#define AFC_TIMING_OPCODE_SET_GET_AVG_EXPONENT 29
#define AFC_TIMING_NAME_SET_GET_AVG_EXPONENT "afc_timing_set_get_avg_exponent"
#define AFC_TIMING_OPCODE_END 30
#endif
src/sm_io/modules/afc_timing/sm_io_afc_timing_core.c 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_afc_timing_core.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_afc_timing_core]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_afc_timing_core]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io_afc_timing_core]", \
smio_err_str (err_type))
/* Creates a new instance of Device Information */
smio_afc_timing_t * smio_afc_timing_new (smio_t *parent)
{
(void) parent;
smio_afc_timing_t *self = (smio_afc_timing_t *) zmalloc (sizeof *self);
ASSERT_ALLOC(self, err_self_alloc);
return self;
err_self_alloc:
return NULL;
}
/* Destroy an instance of the Device Information */
smio_err_e smio_afc_timing_destroy (smio_afc_timing_t **self_p)
{
assert (self_p);
if (*self_p) {
smio_afc_timing_t *self = *self_p;
free (self);
*self_p = NULL;
}
return SMIO_SUCCESS;
}
src/sm_io/modules/afc_timing/sm_io_afc_timing_core.h 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_AFC_TIMING_CORE_H_
#define _SM_IO_AFC_TIMING_CORE_H_
typedef struct {
const uint32_t example;
} smio_afc_timing_t;
/***************** Our methods *****************/
/* Creates a new instance of the smio realization */
smio_afc_timing_t * smio_afc_timing_new (smio_t *parent);
/* Destroys the smio realization */
smio_err_e smio_afc_timing_destroy (smio_afc_timing_t **self_p);
#endif
src/sm_io/modules/afc_timing/sm_io_afc_timing_defaults.c 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_afc_timing_defaults.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:afc_timing_defaults]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:afc_timing_defaults]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io:afc_timing_defaults]", \
smio_err_str (err_type))
#define SMIO_AFC_TIMING_LIBBPMCLIENT_LOG_MODE "a"
/* We use the actual libclient to send and configure our default values,
* maintaining internal consistency. So, in fact, we are sending ourselves
* a message containing the default values. Because of this approach, we
* only get to default our values when the functions are already exported
* to the broker, which happens on a late stage. This could cause a fast
* client to get an inconsistent state from our server */
/* TODO: Avoid exporting the functions before we have initialized
* our server with the default values */
smio_err_e afc_timing_config_defaults (char *broker_endp, char *service,
const char *log_file_name)
{
(void) log_file_name;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:afc_timing_defaults] Configuring SMIO "
"AFC_TIMING with default values ...\n");
bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
smio_err_e err = SMIO_SUCCESS;
bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
log_file_name, SMIO_AFC_TIMING_LIBBPMCLIENT_LOG_MODE);
ASSERT_ALLOC(config_client, err_alloc_client);
client_err = afc_timing_set_evt_code_0 (config_client, service, AFC_TIMING_DFLT_EVT_IN0);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 0 event code",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_code_1 (config_client, service, AFC_TIMING_DFLT_EVT_IN1);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 1 event code",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_code_2 (config_client, service, AFC_TIMING_DFLT_EVT_IN2);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 2 event code",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_code_3 (config_client, service, AFC_TIMING_DFLT_EVT_IN3);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 3 event code",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_code_4 (config_client, service, AFC_TIMING_DFLT_EVT_IN4);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 4 event code",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_code_5 (config_client, service, AFC_TIMING_DFLT_EVT_IN5);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 5 event code",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_code_6 (config_client, service, AFC_TIMING_DFLT_EVT_IN6);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 6 event code",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_delay_0 (config_client, service, AFC_TIMING_DFLT_EVT_DLY0);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 0 event delay",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_delay_1 (config_client, service, AFC_TIMING_DFLT_EVT_DLY1);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 1 event delay",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_delay_2 (config_client, service, AFC_TIMING_DFLT_EVT_DLY2);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 2 event delay",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_delay_3 (config_client, service, AFC_TIMING_DFLT_EVT_DLY3);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 3 event delay",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_delay_4 (config_client, service, AFC_TIMING_DFLT_EVT_DLY4);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 4 event delay",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_delay_5 (config_client, service, AFC_TIMING_DFLT_EVT_DLY5);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 5 event delay",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_delay_6 (config_client, service, AFC_TIMING_DFLT_EVT_DLY6);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 6 event delay",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_width_0 (config_client, service, AFC_TIMING_DFLT_EVT_WDT0);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 0 event width",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_width_1 (config_client, service, AFC_TIMING_DFLT_EVT_WDT1);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 1 event width",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_width_2 (config_client, service, AFC_TIMING_DFLT_EVT_WDT2);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 2 event width",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_width_3 (config_client, service, AFC_TIMING_DFLT_EVT_WDT3);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 3 event width",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_width_4 (config_client, service, AFC_TIMING_DFLT_EVT_WDT4);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 4 event width",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_width_5 (config_client, service, AFC_TIMING_DFLT_EVT_WDT5);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 5 event width",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_evt_width_6 (config_client, service, AFC_TIMING_DFLT_EVT_WDT6);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set channel 6 event width",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_freq_kp (config_client, service, AFC_TIMING_DFLT_FREQ_KP);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set proportional gain of frequency feedback",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_freq_ki (config_client, service, AFC_TIMING_DFLT_FREQ_KI);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set integral gain of frequency feedback",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_phase_kp (config_client, service, AFC_TIMING_DFLT_PHASE_KP);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set proportional gain of phase feedback",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_phase_ki (config_client, service, AFC_TIMING_DFLT_PHASE_KI);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set integral gain of phase feedback",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_phase_bias (config_client, service, AFC_TIMING_DFLT_PHASE_BIAS);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set bias of phase feedback",
err_param_set, SMIO_ERR_CONFIG_DFLT);
client_err = afc_timing_set_avg_exponent (config_client, service, AFC_TIMING_DFLT_DDMTD_AVG_EXP);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could not set average exponent number of phase feedback",
err_param_set, SMIO_ERR_CONFIG_DFLT);
err_param_set:
bpm_client_destroy (&config_client);
err_alloc_client:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:afc_timing_defaults] Exiting Config thread %s\n",
service);
return err;
}
src/sm_io/modules/afc_timing/sm_io_afc_timing_defaults.h 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _AFC_TIMING_DEFAULTS_H_
#define _AFC_TIMING_DEFAULTS_H_
#define AFC_TIMING_DFLT_PHASE_BIAS 0x5b
#define AFC_TIMING_DFLT_DDMTD_AVG_EXP 0x8
#define AFC_TIMING_DFLT_RTM_RFREQ_HI 0x57d2
#define AFC_TIMING_DFLT_RTM_RFREQ_LO 0x184ea
#define AFC_TIMING_DFLT_RTM_N1 0x5
#define AFC_TIMING_DFLT_RTM_HS_DIV 0x3
#define AFC_TIMING_DFLT_AFC_RFREQ_HI 0x57d2
#define AFC_TIMING_DFLT_AFC_RFREQ_LO 0x184ea
#define AFC_TIMING_DFLT_AFC_N1 0xb
#define AFC_TIMING_DFLT_AFC_HS_DIV 0x3
#define AFC_TIMING_DFLT_FREQ_KP 0x1
#define AFC_TIMING_DFLT_FREQ_KI 0x64
#define AFC_TIMING_DFLT_PHASE_KP 0x10
#define AFC_TIMING_DFLT_PHASE_KI 0x6
#define AFC_TIMING_DFLT_EVT_IN0 0x1
#define AFC_TIMING_DFLT_EVT_IN1 0x1
#define AFC_TIMING_DFLT_EVT_IN2 0x1
#define AFC_TIMING_DFLT_EVT_IN3 0x1
#define AFC_TIMING_DFLT_EVT_IN4 0x1
#define AFC_TIMING_DFLT_EVT_IN5 0x1
#define AFC_TIMING_DFLT_EVT_IN6 0x1
#define AFC_TIMING_DFLT_EVT_DLY0 0x0
#define AFC_TIMING_DFLT_EVT_DLY1 0x0
#define AFC_TIMING_DFLT_EVT_DLY2 0x0
#define AFC_TIMING_DFLT_EVT_DLY3 0x0
#define AFC_TIMING_DFLT_EVT_DLY4 0x0
#define AFC_TIMING_DFLT_EVT_DLY5 0x0
#define AFC_TIMING_DFLT_EVT_DLY6 0x0
#define AFC_TIMING_DFLT_EVT_WDT0 0x5
#define AFC_TIMING_DFLT_EVT_WDT1 0x5
#define AFC_TIMING_DFLT_EVT_WDT2 0x5
#define AFC_TIMING_DFLT_EVT_WDT3 0x5
#define AFC_TIMING_DFLT_EVT_WDT4 0x5
#define AFC_TIMING_DFLT_EVT_WDT5 0x5
#define AFC_TIMING_DFLT_EVT_WDT6 0x5
smio_err_e afc_timing_config_defaults (char *broker_endp, char *service,
const char *log_file_name);
#endif
src/sm_io/modules/afc_timing/sm_io_afc_timing_exp.c 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Joao Brito <joao.brito@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_afc_timing_codes.h"
#include "sm_io_afc_timing_defaults.h"
//#include "sm_io_afc_timing_useful_macros.h"
#include "sm_io_afc_timing_exports.h"
#include "sm_io_afc_timing_core.h"
#include "sm_io_afc_timing_exp.h"
#include "hw/wb_slave_afc_timing_regs.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:afc_timing_exp]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:afc_timing_exp]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io:afc_timing_exp]", \
smio_err_str (err_type))
/************************************************************/
/************* Specific TIMING operations **************/
/************************************************************/
RW_PARAM_FUNC(afc_timing, link_status) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, STAT, LINK, SINGLE_BIT_PARAM,
/*read only*/,/*read only*/ , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(afc_timing, rxen_status) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, STAT, RXEN, SINGLE_BIT_PARAM,
/*read only*/,/*read only*/ , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(afc_timing, ref_clk_locked) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, STAT, REFCLKLOCK, SINGLE_BIT_PARAM,
/*read only*/,/*read only*/ , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
/****************** Event receiver configuration ******************/
/* Custom parameter check */
static int _rw_afc_timing_evt_code_chk (uint32_t evt_code)
{
if (evt_code==0x7F || evt_code==0x7E || evt_code==0x70) {
return PARAM_ERR;
}
return PARAM_OK;
}
rw_param_check_fp rw_afc_timing_evt_code_chk_fp = _rw_afc_timing_evt_code_chk;
/* Event code monitored by each channel */
#define TIMING_EVT_IN0_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_IN0_GLOBAL_W(val) (val)
#define TIMING_EVT_IN0_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_code_0) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_IN0, GLOBAL, MULT_BIT_PARAM,
, , rw_afc_timing_evt_code_chk_fp, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_IN1_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_IN1_GLOBAL_W(val) (val)
#define TIMING_EVT_IN1_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_code_1) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_IN1, GLOBAL, MULT_BIT_PARAM,
, , rw_afc_timing_evt_code_chk_fp, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_IN2_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_IN2_GLOBAL_W(val) (val)
#define TIMING_EVT_IN2_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_code_2) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_IN2, GLOBAL, MULT_BIT_PARAM,
, , rw_afc_timing_evt_code_chk_fp, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_IN3_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_IN3_GLOBAL_W(val) (val)
#define TIMING_EVT_IN3_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_code_3) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_IN3, GLOBAL, MULT_BIT_PARAM,
, , rw_afc_timing_evt_code_chk_fp, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_IN4_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_IN4_GLOBAL_W(val) (val)
#define TIMING_EVT_IN4_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_code_4) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_IN4, GLOBAL, MULT_BIT_PARAM,
, , rw_afc_timing_evt_code_chk_fp, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_IN5_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_IN5_GLOBAL_W(val) (val)
#define TIMING_EVT_IN5_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_code_5) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_IN5, GLOBAL, MULT_BIT_PARAM,
, , rw_afc_timing_evt_code_chk_fp, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_IN6_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_IN6_GLOBAL_W(val) (val)
#define TIMING_EVT_IN6_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_code_6) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_IN6, GLOBAL, MULT_BIT_PARAM,
, , rw_afc_timing_evt_code_chk_fp, NO_FMT_FUNC, SET_FIELD);
}
/* Delay to tigger generation after event receive */
#define TIMING_EVT_DLY0_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_DLY0_GLOBAL_W(val) (val)
#define TIMING_EVT_DLY0_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_delay_0) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_DLY0, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_DLY1_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_DLY1_GLOBAL_W(val) (val)
#define TIMING_EVT_DLY1_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_delay_1) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_DLY1, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_DLY2_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_DLY2_GLOBAL_W(val) (val)
#define TIMING_EVT_DLY2_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_delay_2) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_DLY2, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_DLY3_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_DLY3_GLOBAL_W(val) (val)
#define TIMING_EVT_DLY3_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_delay_3) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_DLY3, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_DLY4_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_DLY4_GLOBAL_W(val) (val)
#define TIMING_EVT_DLY4_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_delay_4) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_DLY4, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_DLY5_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_DLY5_GLOBAL_W(val) (val)
#define TIMING_EVT_DLY5_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_delay_5) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_DLY5, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_DLY6_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_DLY6_GLOBAL_W(val) (val)
#define TIMING_EVT_DLY6_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_delay_6) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_DLY6, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
/* Width of the trigger generated by an event receive */
#define TIMING_EVT_WDT0_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_WDT0_GLOBAL_W(val) (val)
#define TIMING_EVT_WDT0_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_width_0) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_WDT0, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_WDT1_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_WDT1_GLOBAL_W(val) (val)
#define TIMING_EVT_WDT1_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_width_1) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_WDT1, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_WDT2_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_WDT2_GLOBAL_W(val) (val)
#define TIMING_EVT_WDT2_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_width_2) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_WDT2, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_WDT3_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_WDT3_GLOBAL_W(val) (val)
#define TIMING_EVT_WDT3_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_width_3) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_WDT3, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_WDT4_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_WDT4_GLOBAL_W(val) (val)
#define TIMING_EVT_WDT4_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_width_4) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_WDT4, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_WDT5_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_WDT5_GLOBAL_W(val) (val)
#define TIMING_EVT_WDT5_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_width_5) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_WDT5, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_EVT_WDT6_GLOBAL_MASK (0xffffffff)
#define TIMING_EVT_WDT6_GLOBAL_W(val) (val)
#define TIMING_EVT_WDT6_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, evt_width_6) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, EVT_WDT6, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
/* Phase and frequency control feedback gains */
#define TIMING_CONTROL_GAIN_MIN 1
#define TIMING_CONTROL_GAIN_MAX 0xFF
RW_PARAM_FUNC(afc_timing, freq_kp) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, FREQ, KP, MULT_BIT_PARAM,
TIMING_CONTROL_GAIN_MIN, TIMING_CONTROL_GAIN_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(afc_timing, freq_ki) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, FREQ, KI, MULT_BIT_PARAM,
TIMING_CONTROL_GAIN_MIN, TIMING_CONTROL_GAIN_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(afc_timing, phase_kp) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, PHASE, KP, MULT_BIT_PARAM,
TIMING_CONTROL_GAIN_MIN, TIMING_CONTROL_GAIN_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(afc_timing, phase_ki) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, PHASE, KI, MULT_BIT_PARAM,
TIMING_CONTROL_GAIN_MIN, TIMING_CONTROL_GAIN_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_PHASE_BIAS_GLOBAL_MASK (0xffffffff)
#define TIMING_PHASE_BIAS_GLOBAL_W(val) (val)
#define TIMING_PHASE_BIAS_GLOBAL_R(val) (val)
RW_PARAM_FUNC(afc_timing, phase_bias) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, PHASE_BIAS, GLOBAL, MULT_BIT_PARAM,
, , NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define TIMING_AVG_EXP_MIN 1
#define TIMING_AVG_EXP_MAX 0xF
RW_PARAM_FUNC(afc_timing, avg_exponent) {
SET_GET_PARAM(afc_timing, 0x0, TIMING, DDMTD, AVG_EXP, MULT_BIT_PARAM,
TIMING_AVG_EXP_MIN, TIMING_AVG_EXP_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
/* Exported function pointers */
const disp_table_func_fp afc_timing_exp_fp [] = {
RW_PARAM_FUNC_NAME(afc_timing, link_status),
RW_PARAM_FUNC_NAME(afc_timing, rxen_status),
RW_PARAM_FUNC_NAME(afc_timing, ref_clk_locked),
RW_PARAM_FUNC_NAME(afc_timing, evt_code_0),
RW_PARAM_FUNC_NAME(afc_timing, evt_code_1),
RW_PARAM_FUNC_NAME(afc_timing, evt_code_2),
RW_PARAM_FUNC_NAME(afc_timing, evt_code_3),
RW_PARAM_FUNC_NAME(afc_timing, evt_code_4),
RW_PARAM_FUNC_NAME(afc_timing, evt_code_5),
RW_PARAM_FUNC_NAME(afc_timing, evt_code_6),
RW_PARAM_FUNC_NAME(afc_timing, evt_delay_0),
RW_PARAM_FUNC_NAME(afc_timing, evt_delay_1),
RW_PARAM_FUNC_NAME(afc_timing, evt_delay_2),
RW_PARAM_FUNC_NAME(afc_timing, evt_delay_3),
RW_PARAM_FUNC_NAME(afc_timing, evt_delay_4),
RW_PARAM_FUNC_NAME(afc_timing, evt_delay_5),
RW_PARAM_FUNC_NAME(afc_timing, evt_delay_6),
RW_PARAM_FUNC_NAME(afc_timing, evt_width_0),
RW_PARAM_FUNC_NAME(afc_timing, evt_width_1),
RW_PARAM_FUNC_NAME(afc_timing, evt_width_2),
RW_PARAM_FUNC_NAME(afc_timing, evt_width_3),
RW_PARAM_FUNC_NAME(afc_timing, evt_width_4),
RW_PARAM_FUNC_NAME(afc_timing, evt_width_5),
RW_PARAM_FUNC_NAME(afc_timing, evt_width_6),
RW_PARAM_FUNC_NAME(afc_timing, freq_kp),
RW_PARAM_FUNC_NAME(afc_timing, freq_ki),
RW_PARAM_FUNC_NAME(afc_timing, phase_kp),
RW_PARAM_FUNC_NAME(afc_timing, phase_ki),
RW_PARAM_FUNC_NAME(afc_timing, phase_bias),
RW_PARAM_FUNC_NAME(afc_timing, avg_exponent),
NULL
};
/************************************************************/
/***************** Export methods functions *****************/
/************************************************************/
static smio_err_e _afc_timing_do_op (void *owner, void *msg);
/* Attach an instance of sm_io to dev_io function pointer */
smio_err_e afc_timing_attach (smio_t *self, devio_t *parent)
{
(void) self;
(void) parent;
return SMIO_ERR_FUNC_NOT_IMPL;
}
/* Deattach an instance of sm_io to dev_io function pointer */
smio_err_e afc_timing_deattach (smio_t *self)
{
(void) self;
return SMIO_ERR_FUNC_NOT_IMPL;
}
/* Export (register) sm_io to handle operations function pointer */
smio_err_e afc_timing_export_ops (smio_t *self,
const disp_op_t **smio_exp_ops)
{
(void) self;
(void) smio_exp_ops;
return SMIO_ERR_FUNC_NOT_IMPL;
}
/* Unexport (unregister) sm_io to handle operations function pointer */
smio_err_e afc_timing_unexport_ops (smio_t *self)
{
(void) self;
return SMIO_ERR_FUNC_NOT_IMPL;
}
/* Generic wrapper for receiving opcodes and arguments to specific funtions function pointer */
/* FIXME: Code repetition! _devio_do_smio_op () function does almost the same!!! */
smio_err_e _afc_timing_do_op (void *owner, void *msg)
{
(void) owner;
(void) msg;
return SMIO_ERR_FUNC_NOT_IMPL;
}
smio_err_e afc_timing_do_op (void *self, void *msg)
{
return _afc_timing_do_op (self, msg);
}
const smio_ops_t afc_timing_ops = {
.attach = afc_timing_attach, /* Attach sm_io instance to dev_io */
.deattach = afc_timing_deattach, /* Deattach sm_io instance to dev_io */
.export_ops = afc_timing_export_ops, /* Export sm_io operations to dev_io */
.unexport_ops = afc_timing_unexport_ops, /* Unexport sm_io operations to dev_io */
.do_op = afc_timing_do_op /* Generic wrapper for handling specific operations */
};
/************************************************************/
/****************** Bootstrap Operations ********************/
/************************************************************/
smio_err_e afc_timing_init (smio_t * self)
{
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:afc_timing_exp] Initializing afc_timing\n");
smio_err_e err = SMIO_SUCCESS;
err = smio_set_id (self, AFC_TIMING_SDB_DEVID);
ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO id", err_set_id);
err = smio_set_name (self, AFC_TIMING_SDB_NAME);
ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO name", err_set_name);
/* Set SMIO ops pointers */
err = smio_set_ops (self, &afc_timing_ops);
ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO operations",
err_smio_set_ops);
err = smio_set_thsafe_client_ops (self, &smio_thsafe_client_zmq_ops);
ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO thsafe operations",
err_smio_set_thsafe_ops);
/* Fill the disp_op_t description structure with the callbacks. */
/* disp_op_t structure is const and all of the functions performing on it
* obviously receives a const argument, but here (and only on the SMIO
* initialization) we need to make an exception if we want to keep the
* functions' description and the function pointers separate */
err = smio_init_exp_ops (self, (disp_op_t **) afc_timing_exp_ops, afc_timing_exp_fp);
ASSERT_TEST(err == SMIO_SUCCESS, "Could not fill SMIO "
"function descriptors with the callbacks", err_fill_desc);
err = smio_set_exp_ops (self, afc_timing_exp_ops);
ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO exported operations",
err_smio_set_exp_ops);
/* Initialize specific structure */
smio_afc_timing_t *smio_handler = smio_afc_timing_new (self);
ASSERT_ALLOC(smio_handler, err_smio_handler_alloc, SMIO_ERR_ALLOC);
err = smio_set_handler (self, smio_handler);
ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO handler",
err_smio_set_handler);
return err;
err_smio_set_handler:
smio_afc_timing_destroy (&smio_handler);
err_smio_handler_alloc:
smio_set_exp_ops (self, NULL);
err_smio_set_exp_ops:
err_fill_desc:
smio_set_thsafe_client_ops (self, NULL);
err_smio_set_thsafe_ops:
smio_set_ops (self, NULL);
err_smio_set_ops:
err_set_name:
err_set_id:
return err;
}
/* Destroy sm_io instance of afc_timing */
smio_err_e afc_timing_shutdown (smio_t *self)
{
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:afc_timing_exp] Shutting down afc_timing\n");
smio_err_e err = SMIO_SUCCESS;
smio_afc_timing_t *afc_timing = smio_get_handler (self);
ASSERT_TEST(afc_timing != NULL, "Could not get AFC Timing handler",
err_afc_timing_handler, SMIO_ERR_ALLOC /* FIXME: improve return code */);
/* Destroy SMIO instance */
smio_afc_timing_destroy (&afc_timing);
/* Nullify operation pointers */
smio_set_exp_ops (self, NULL);
smio_set_thsafe_client_ops (self, NULL);
smio_set_ops (self, NULL);
err_afc_timing_handler:
return err;
}
const smio_bootstrap_ops_t afc_timing_bootstrap_ops = {
.init = afc_timing_init,
.shutdown = afc_timing_shutdown,
.config_defaults = afc_timing_config_defaults
};
SMIO_MOD_DECLARE(AFC_TIMING_SDB_DEVID, AFC_TIMING_SDB_NAME, afc_timing_bootstrap_ops)
src/sm_io/modules/afc_timing/sm_io_afc_timing_exp.h 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _TIMING_H_
#define _TIMING_H_
#include "sm_io_bootstrap.h"
#include "smio_thsafe_zmq_client.h"
#include "exp_ops_codes.h"
#include "sm_io_afc_timing_core.h"
/* Known modules IDs (from SDB records defined in FPGA) */
#define AFC_TIMING_SDB_DEVID 0xbe10be10
#define AFC_TIMING_SDB_NAME "LNLS_AFC_TIMING"
extern const smio_bootstrap_ops_t afc_timing_bootstrap_ops;
#endif
src/sm_io/modules/afc_timing/sm_io_afc_timing_exports.c 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Joao Brito <joao.brito@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "sm_io_exports_helper.h"
#include "sm_io_codes.h"
/* Description SMIO AFC_TIMING functions */
disp_op_t afc_timing_set_get_link_status_exp = {
.name = AFC_TIMING_NAME_SET_GET_LINK_STATUS,
.opcode = AFC_TIMING_OPCODE_SET_GET_LINK_STATUS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_rxen_status_exp = {
.name = AFC_TIMING_NAME_SET_GET_RXEN_STATUS,
.opcode = AFC_TIMING_OPCODE_SET_GET_RXEN_STATUS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_ref_clk_locked_exp = {
.name = AFC_TIMING_NAME_SET_GET_REF_CLK_LOCKED,
.opcode = AFC_TIMING_OPCODE_SET_GET_REF_CLK_LOCKED,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_code_0_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_IN0,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_IN0,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_code_1_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_IN1,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_IN1,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_code_2_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_IN2,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_IN2,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_code_3_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_IN3,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_IN3,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_code_4_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_IN4,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_IN4,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_code_5_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_IN5,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_IN5,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_code_6_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_IN6,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_IN6,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_delay_0_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_DLY0,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_DLY0,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_delay_1_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_DLY1,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_DLY1,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_delay_2_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_DLY2,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_DLY2,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_delay_3_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_DLY3,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_DLY3,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_delay_4_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_DLY4,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_DLY4,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_delay_5_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_DLY5,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_DLY5,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_delay_6_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_DLY6,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_DLY6,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_width_0_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_WDT0,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_WDT0,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_width_1_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_WDT1,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_WDT1,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_width_2_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_WDT2,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_WDT2,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_width_3_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_WDT3,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_WDT3,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_width_4_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_WDT4,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_WDT4,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_width_5_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_WDT5,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_WDT5,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_evt_width_6_exp = {
.name = AFC_TIMING_NAME_SET_GET_EVT_WDT6,
.opcode = AFC_TIMING_OPCODE_SET_GET_EVT_WDT6,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_freq_kp_exp = {
.name = AFC_TIMING_NAME_SET_GET_FREQ_KP,
.opcode = AFC_TIMING_OPCODE_SET_GET_FREQ_KP,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_freq_ki_exp = {
.name = AFC_TIMING_NAME_SET_GET_FREQ_KI,
.opcode = AFC_TIMING_OPCODE_SET_GET_FREQ_KI,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_phase_kp_exp = {
.name = AFC_TIMING_NAME_SET_GET_PHASE_KP,
.opcode = AFC_TIMING_OPCODE_SET_GET_PHASE_KP,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_phase_ki_exp = {
.name = AFC_TIMING_NAME_SET_GET_PHASE_KI,
.opcode = AFC_TIMING_OPCODE_SET_GET_PHASE_KI,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_phase_bias_exp = {
.name = AFC_TIMING_NAME_SET_GET_PHASE_BIAS,
.opcode = AFC_TIMING_OPCODE_SET_GET_PHASE_BIAS,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t afc_timing_set_get_avg_exponent_exp = {
.name = AFC_TIMING_NAME_SET_GET_AVG_EXPONENT,
.opcode = AFC_TIMING_OPCODE_SET_GET_AVG_EXPONENT,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
/* Exported function description */
const disp_op_t *afc_timing_exp_ops [] = {
&afc_timing_set_get_link_status_exp,
&afc_timing_set_get_rxen_status_exp,
&afc_timing_set_get_ref_clk_locked_exp,
&afc_timing_set_get_evt_code_0_exp,
&afc_timing_set_get_evt_code_1_exp,
&afc_timing_set_get_evt_code_2_exp,
&afc_timing_set_get_evt_code_3_exp,
&afc_timing_set_get_evt_code_4_exp,
&afc_timing_set_get_evt_code_5_exp,
&afc_timing_set_get_evt_code_6_exp,
&afc_timing_set_get_evt_delay_0_exp,
&afc_timing_set_get_evt_delay_1_exp,
&afc_timing_set_get_evt_delay_2_exp,
&afc_timing_set_get_evt_delay_3_exp,
&afc_timing_set_get_evt_delay_4_exp,
&afc_timing_set_get_evt_delay_5_exp,
&afc_timing_set_get_evt_delay_6_exp,
&afc_timing_set_get_evt_width_0_exp,
&afc_timing_set_get_evt_width_1_exp,
&afc_timing_set_get_evt_width_2_exp,
&afc_timing_set_get_evt_width_3_exp,
&afc_timing_set_get_evt_width_4_exp,
&afc_timing_set_get_evt_width_5_exp,
&afc_timing_set_get_evt_width_6_exp,
&afc_timing_set_get_freq_kp_exp,
&afc_timing_set_get_freq_ki_exp,
&afc_timing_set_get_phase_kp_exp,
&afc_timing_set_get_phase_ki_exp,
&afc_timing_set_get_phase_bias_exp,
&afc_timing_set_get_avg_exponent_exp,
NULL
};
src/sm_io/modules/afc_timing/sm_io_afc_timing_exports.h 0 → 100644
View file @ 9b00c780
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_AFC_TIMING_EXPORTS_H_
#define _SM_IO_AFC_TIMING_EXPORTS_H_
#include "disptable.h"
extern disp_op_t afc_timing_set_get_link_status_exp;
extern disp_op_t afc_timing_set_get_rxen_status_exp;
extern disp_op_t afc_timing_set_get_ref_clk_locked_exp;
extern disp_op_t afc_timing_set_get_evt_code_0_exp;
extern disp_op_t afc_timing_set_get_evt_code_1_exp;
extern disp_op_t afc_timing_set_get_evt_code_2_exp;
extern disp_op_t afc_timing_set_get_evt_code_3_exp;
extern disp_op_t afc_timing_set_get_evt_code_4_exp;
extern disp_op_t afc_timing_set_get_evt_code_5_exp;
extern disp_op_t afc_timing_set_get_evt_code_6_exp;
extern disp_op_t afc_timing_set_get_evt_delay_0_exp;
extern disp_op_t afc_timing_set_get_evt_delay_1_exp;
extern disp_op_t afc_timing_set_get_evt_delay_2_exp;
extern disp_op_t afc_timing_set_get_evt_delay_3_exp;
extern disp_op_t afc_timing_set_get_evt_delay_4_exp;
extern disp_op_t afc_timing_set_get_evt_delay_5_exp;
extern disp_op_t afc_timing_set_get_evt_delay_6_exp;
extern disp_op_t afc_timing_set_get_evt_width_0_exp;
extern disp_op_t afc_timing_set_get_evt_width_1_exp;
extern disp_op_t afc_timing_set_get_evt_width_2_exp;
extern disp_op_t afc_timing_set_get_evt_width_3_exp;
extern disp_op_t afc_timing_set_get_evt_width_4_exp;
extern disp_op_t afc_timing_set_get_evt_width_5_exp;
extern disp_op_t afc_timing_set_get_evt_width_6_exp;
extern disp_op_t afc_timing_set_get_freq_kp_exp;
extern disp_op_t afc_timing_set_get_freq_ki_exp;
extern disp_op_t afc_timing_set_get_phase_kp_exp;
extern disp_op_t afc_timing_set_get_phase_ki_exp;
extern disp_op_t afc_timing_set_get_phase_bias_exp;
extern disp_op_t afc_timing_set_get_avg_exponent_exp;
extern const disp_op_t *afc_timing_exp_ops [];
#endif
src/sm_io/modules/modules.mk
View file @ 9b00c780
......@@ -8,7 +8,8 @@ include $(SRC_DIR)/sm_io/modules/fmc130m_4ch/fmc130m_4ch.mk \
$(SRC_DIR)/sm_io/modules/rffe/rffe.mk \
$(SRC_DIR)/sm_io/modules/afc_diag/afc_diag.mk \
$(SRC_DIR)/sm_io/modules/trigger_iface/trigger_iface.mk \
$(SRC_DIR)/sm_io/modules/trigger_mux/trigger_mux.mk
$(SRC_DIR)/sm_io/modules/trigger_mux/trigger_mux.mk \
$(SRC_DIR)/sm_io/modules/afc_timing/afc_timing.mk
sm_io_modules_DIR = $(SRC_DIR)/sm_io/modules
......@@ -23,4 +24,5 @@ sm_io_modules_OBJS = $(sm_io_modules_DIR)/sm_io_codes.o \
$(sm_io_rffe_OBJS) \
$(sm_io_afc_diag_OBJS) \
$(sm_io_trigger_iface_OBJS) \
$(sm_io_trigger_mux_OBJS)
$(sm_io_trigger_mux_OBJS) \
$(sm_io_afc_timing_OBJS)
src/sm_io/modules/sm_io_codes.c
View file @ 9b00c780
......@@ -19,6 +19,7 @@ const disp_op_t **smio_exp_ops [] = {
afc_diag_exp_ops,
trigger_iface_exp_ops,
trigger_mux_exp_ops,
afc_timing_exp_ops,
NULL
};
src/sm_io/modules/sm_io_codes.h
View file @ 9b00c780
......@@ -33,6 +33,7 @@ typedef struct _smio_rffe_version_t smio_rffe_version_t;
#include "sm_io_afc_diag_codes.h"
#include "sm_io_trigger_iface_codes.h"
#include "sm_io_trigger_mux_codes.h"
#include "sm_io_afc_timing_codes.h"
/* Include all function descriptors */
#include "sm_io_fmc130m_4ch_exports.h"
......@@ -46,6 +47,7 @@ typedef struct _smio_rffe_version_t smio_rffe_version_t;
#include "sm_io_afc_diag_exports.h"
#include "sm_io_trigger_iface_exports.h"
#include "sm_io_trigger_mux_exports.h"
#include "sm_io_afc_timing_exports.h"
/* Merge all function descriptors in a single structure */
extern const disp_op_t **smio_exp_ops [];
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment