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Beam Positoning Monitor - Software
Commit a28a964b authored by Lucas Russo's avatar Lucas Russo
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include/*: remove static layout of boards 

Now, these addresses are read from SDB
parent 61c66844
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Showing with 35 additions and 498 deletions
include/boards/afcv3/mem_layout.h
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include/boards/afcv3_1/mem_layout.h
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include/boards/ml605/mem_layout.h
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......@@ -15,95 +15,6 @@
#define SDB_ADDRESS 0x00300000UL
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define FMC1_130M_BASE_RAW_ADDR 0x00310000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC1_130M_SI571_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC1_130M_AD9510_RAW_SPI (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC1_130M_EEPROM_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC1_130M_LM75A_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define FMC1_250M_BASE_RAW_ADDR 0x00310000
#define FMC1_250M_CTRL_RAW_REGS (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC1_250M_AMC7823_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC1_250M_ISLA216P_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define FMC1_250M_AD9510_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_AD9510_RAW_SPI_OFFS)
#define FMC1_250M_SI571_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_SI571_RAW_I2C_OFFS)
#define FMC1_250M_EEPROM_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_EEPROM_RAW_I2C_OFFS)
#define WB_ACQ1_BASE_RAW_ADDR 0x00330000
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
/* The following is a bit of a hack.
* We employ a generic API for talking to the hardware.
* So, our transport layer (PCIe or Ethernet, for now)
* should be invisible to the SMIO instances.
*
* However, PCI devices generally employ multiple BAR
* registers mapped to different parts of the device.
* For instance, in the bpm-gw FPGA firmware, the PCIe
* core has 3 BARs (BAR0, BAR2 and BAR4) mapped to the
* following:
*
* BAR0 -> PCIe control registers
* BAR2 -> DDR3 SDRAM
* BAR4 -> Wishbone (necessary to use pages mechanism)
*
* So, we define our addresses as the logic address plus
* the BAR number. With this, the PCIe transport layer
* can differentiate between multiple bars and select
* the correct one to read or write
*/
/* Wishbone Addresses */
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
#define FMC1_130M_FMC_ADC_COMMON (BAR4_ADDR | FMC1_130M_FMC_ADC_COMMON_RAW_REGS)
#define FMC1_130M_FMC_ACTIVE_CLK (BAR4_ADDR | FMC1_130M_FMC_ACTIVE_CLK_RAW)
#define FMC1_130M_EEPROM_I2C (BAR4_ADDR | FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (BAR4_ADDR | FMC1_130M_LM75A_RAW_I2C)
#define FMC1_250M_BASE_ADDR (BAR4_ADDR | FMC1_250M_BASE_RAW_ADDR)
#define FMC1_250M_CTRL_REGS (BAR4_ADDR | FMC1_250M_CTRL_RAW_REGS)
#define FMC1_250M_FMC_ADC_COMMON (BAR4_ADDR | FMC1_250M_FMC_ADC_COMMON_RAW_REGS)
#define FMC1_250M_FMC_ACTIVE_CLK (BAR4_ADDR | FMC1_250M_FMC_ACTIVE_CLK_RAW)
#define FMC1_250M_EEPROM_I2C (BAR4_ADDR | FMC1_250M_EEPROM_RAW_I2C)
#define FMC1_250M_AMC7823_SPI (BAR4_ADDR | FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (BAR4_ADDR | FMC1_250M_ISLA216P_RAW_SPI)
#define WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ1_BASE_RAW_ADDR)
/************************* ML605 Gateware Options *************************/
/********************* FMC130M_4CH SMIO Gateware Options ******************/
......
include/mem_layout_common.h
View file @ a28a964b
......@@ -46,6 +46,39 @@ extern "C" {
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
/* FMC_ACTIVE_CLK Component */
#define FMC_ACTIVE_CLK_CTRL_REGS_OFFS (FMC_ACTIVE_CLK_CTRL_RAW_REGS_OFFS)
#define FMC_ACTIVE_CLK_SI571_I2C_OFFS (FMC_ACTIVE_CLK_SI571_RAW_I2C_OFFS)
#define FMC_ACTIVE_CLK_AD9510_SPI_OFFS (FMC_ACTIVE_CLK_AD9510_RAW_SPI_OFFS)
/* FMC_130M Components */
#define FMC_130M_CTRL_REGS_OFFS (FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC_130M_FMC_ADC_COMMON_OFFS (FMC_130M_FMC_ADC_COMMON_RAW_REGS_OFFS)
#define FMC_130M_FMC_ACTIVE_CLK_OFFS (FMC_130M_FMC_ACTIVE_CLK_RAW_OFFS)
#define FMC_130M_EEPROM_I2C_OFFS (FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (FMC_130M_LM75A_RAW_I2C_OFFS)
/* FMC_250M Components */
#define FMC_250M_CTRL_REGS_OFFS (FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC_250M_FMC_ADC_COMMON_OFFS (FMC_250M_FMC_ADC_COMMON_RAW_REGS_OFFS)
#define FMC_250M_FMC_ACTIVE_CLK_OFFS (FMC_250M_FMC_ACTIVE_CLK_RAW_OFFS)
#define FMC_250M_EEPROM_I2C_OFFS (FMC_250M_EEPROM_RAW_I2C_OFFS)
#define FMC_250M_AMC7823_SPI_OFFS (FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC_250M_ISLA216P_SPI_OFFS (FMC_250M_ISLA216P_RAW_SPI_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (DSP_BPM_RAW_SWAP_OFFS)
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_REGS_OFFS (WB_ACQ_CORE_CTRL_RAW_REGS_OFFS)
/* Trigger Interface Components */
#define WB_TRIGGER_IFACE_REG_OFFS (WB_TRIGGER_IFACE_RAW_REG_OFFS)
/* Trigger Mux Components */
#define WB_TRIGGER_MUX_REG_OFFS (WB_TRIGGER_MUX_RAW_REG_OFFS)
/* The following is a bit of a hack.
* We employ a generic API for talking to the hardware.
* So, our transport layer (PCIe or Ethernet, for now)
......@@ -67,40 +100,8 @@ extern "C" {
* the correct one to read or write
*/
/* FMC_ACTIVE_CLK Component */
#define FMC_ACTIVE_CLK_CTRL_REGS_OFFS (BAR4_ADDR | FMC_ACTIVE_CLK_CTRL_RAW_REGS_OFFS)
#define FMC_ACTIVE_CLK_SI571_I2C_OFFS (BAR4_ADDR | FMC_ACTIVE_CLK_SI571_RAW_I2C_OFFS)
#define FMC_ACTIVE_CLK_AD9510_SPI_OFFS (BAR4_ADDR | FMC_ACTIVE_CLK_AD9510_RAW_SPI_OFFS)
/* FMC_130M Components */
#define FMC_130M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC_130M_FMC_ADC_COMMON_OFFS (BAR4_ADDR | FMC_130M_FMC_ADC_COMMON_RAW_REGS_OFFS)
#define FMC_130M_FMC_ACTIVE_CLK_OFFS (BAR4_ADDR | FMC_130M_FMC_ACTIVE_CLK_RAW_OFFS)
#define FMC_130M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (BAR4_ADDR | FMC_130M_LM75A_RAW_I2C_OFFS)
/* FMC_250M Components */
#define FMC_250M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_250M_CTRL_RAW_REGS_OFFS)
#define FMC_250M_FMC_ADC_COMMON_OFFS (BAR4_ADDR | FMC_250M_FMC_ADC_COMMON_RAW_REGS_OFFS)
#define FMC_250M_FMC_ACTIVE_CLK_OFFS (BAR4_ADDR | FMC_250M_FMC_ACTIVE_CLK_RAW_OFFS)
#define FMC_250M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_250M_EEPROM_RAW_I2C_OFFS)
#define FMC_250M_AMC7823_SPI_OFFS (BAR4_ADDR | FMC_250M_AMC7823_RAW_SPI_OFFS)
#define FMC_250M_ISLA216P_SPI_OFFS (BAR4_ADDR | FMC_250M_ISLA216P_RAW_SPI_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (BAR4_ADDR | DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (BAR4_ADDR | DSP_BPM_RAW_SWAP_OFFS)
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_REGS_OFFS (BAR4_ADDR | WB_ACQ_CORE_CTRL_RAW_REGS_OFFS)
/* Trigger Interface Components */
#define WB_TRIGGER_IFACE_REG_OFFS (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_REG_OFFS)
/* Trigger Mux Components */
#define WB_TRIGGER_MUX_REG_OFFS (BAR4_ADDR | WB_TRIGGER_MUX_RAW_REG_OFFS)
/* Large Memory Addresses */
/* FIXME. Large Memory Addresses. We should not have to specify BAR2_ADDR,
* as this is specific to PCIe */
#define LARGE_MEM_ADDR (BAR2_ADDR | LARGE_MEM_RAW_ADDR)
#ifdef __cplusplus
......
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