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Beam Positoning Monitor - Software
Commit aa7501cf authored by Lucas Russo's avatar Lucas Russo
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hal/include/*/*/ddr3_map_ml605.h: fix non-aligned start address 

For invalid temporary channels, such as TBT position and FOFB
position, the start address was not aligned to 8 or 16 bit, causing
a segmentation fault on reading from these address.

This fixes #80 github issue.
parent 289fb357
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Showing with 8 additions and 8 deletions
hal/include/board/ml605/ddr3_map_ml605.h
View file @ aa7501cf
......@@ -28,7 +28,7 @@
#define DDR3_ADC0_MEM_SIZE 2
#define DDR3_ADC0_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADC0_MEM_SIZE)
#define DDR3_ADC0_START_ADDR (DDR3_DUMMY_INIT0_START_ADDR + DDR3_ADC0_MEM_BOOL*DDR3_DUMMY_INIT0_SAMPLE_SIZE)
#define DDR3_ADC0_START_ADDR (DDR3_DUMMY_INIT0_START_ADDR + DDR3_DUMMY_INIT0_MEM_BOOL*DDR3_DUMMY_INIT0_SAMPLE_SIZE)
#define DDR3_ADC0_END_ADDR (DDR3_ADC0_START_ADDR + DDR3_ADC0_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADC0_MEM_BOOL*DDR3_ADC0_SAMPLE_SIZE)
#define DDR3_ADC0_MAX_SAMPLES ((DDR3_ADC0_END_ADDR-DDR3_ADC0_START_ADDR) / DDR3_ADC0_SAMPLE_SIZE)
......@@ -38,7 +38,7 @@
#define DDR3_TBTAMP0_MEM_SIZE 2
#define DDR3_TBTAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTAMP0_MEM_SIZE)
#define DDR3_TBTAMP0_START_ADDR (DDR3_ADC0_END_ADDR + DDR3_TBTAMP0_MEM_BOOL*DDR3_ADC0_SAMPLE_SIZE)
#define DDR3_TBTAMP0_START_ADDR (DDR3_ADC0_END_ADDR + DDR3_ADC0_MEM_BOOL*DDR3_ADC0_SAMPLE_SIZE)
#define DDR3_TBTAMP0_END_ADDR (DDR3_TBTAMP0_START_ADDR + DDR3_TBTAMP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTAMP0_MEM_BOOL*DDR3_TBTAMP0_SAMPLE_SIZE)
#define DDR3_TBTAMP0_MAX_SAMPLES ((DDR3_TBTAMP0_END_ADDR-DDR3_TBTAMP0_START_ADDR) / DDR3_TBTAMP0_SAMPLE_SIZE)
......@@ -48,7 +48,7 @@
#define DDR3_TBTPOS0_MEM_SIZE 0
#define DDR3_TBTPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPOS0_MEM_SIZE)
#define DDR3_TBTPOS0_START_ADDR (DDR3_TBTAMP0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTAMP0_SAMPLE_SIZE)
#define DDR3_TBTPOS0_START_ADDR (DDR3_TBTAMP0_END_ADDR + DDR3_TBTAMP0_MEM_BOOL*DDR3_TBTAMP0_SAMPLE_SIZE)
#define DDR3_TBTPOS0_END_ADDR (DDR3_TBTPOS0_START_ADDR + DDR3_TBTPOS0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_TBTPOS0_MAX_SAMPLES ((DDR3_TBTPOS0_END_ADDR-DDR3_TBTPOS0_START_ADDR) / DDR3_TBTPOS0_SAMPLE_SIZE)
......@@ -58,7 +58,7 @@
#define DDR3_FOFBAMP0_MEM_SIZE 2
#define DDR3_FOFBAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBAMP0_MEM_SIZE)
#define DDR3_FOFBAMP0_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_FOFBAMP0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBAMP0_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBAMP0_END_ADDR (DDR3_FOFBAMP0_START_ADDR + DDR3_FOFBAMP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBAMP0_MEM_BOOL*DDR3_FOFBAMP0_SAMPLE_SIZE)
#define DDR3_FOFBAMP0_MAX_SAMPLES ((DDR3_FOFBAMP0_END_ADDR-DDR3_FOFBAMP0_START_ADDR) / DDR3_FOFBAMP0_SAMPLE_SIZE)
......@@ -68,7 +68,7 @@
#define DDR3_FOFBPOS0_MEM_SIZE 0
#define DDR3_FOFBPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPOS0_MEM_SIZE)
#define DDR3_FOFBPOS0_START_ADDR (DDR3_FOFBAMP0_END_ADDR + DDR3_FOFBPOS0_MEM_BOOL*DDR3_FOFBAMP0_SAMPLE_SIZE)
#define DDR3_FOFBPOS0_START_ADDR (DDR3_FOFBAMP0_END_ADDR + DDR3_FOFBAMP0_MEM_BOOL*DDR3_FOFBAMP0_SAMPLE_SIZE)
#define DDR3_FOFBPOS0_END_ADDR (DDR3_FOFBPOS0_START_ADDR + DDR3_FOFBPOS0_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBPOS0_MEM_BOOL*DDR3_FOFBPOS0_SAMPLE_SIZE)
#define DDR3_FOFBPOS0_MAX_SAMPLES ((DDR3_FOFBPOS0_END_ADDR-DDR3_FOFBPOS0_START_ADDR) / DDR3_FOFBPOS0_SAMPLE_SIZE)
......@@ -78,7 +78,7 @@
#define DDR3_MONITAMP0_MEM_SIZE 0
#define DDR3_MONITAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITAMP0_MEM_SIZE)
#define DDR3_MONITAMP0_START_ADDR (DDR3_FOFBPOS0_END_ADDR + DDR3_MONITAMP0_MEM_BOOL*DDR3_FOFBPOS0_SAMPLE_SIZE)
#define DDR3_MONITAMP0_START_ADDR (DDR3_FOFBPOS0_END_ADDR + DDR3_FOFBPOS0_MEM_BOOL*DDR3_FOFBPOS0_SAMPLE_SIZE)
#define DDR3_MONITAMP0_END_ADDR (DDR3_MONITAMP0_START_ADDR + DDR3_MONITAMP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_MONITAMP0_MEM_BOOL*DDR3_MONITAMP0_SAMPLE_SIZE)
#define DDR3_MONITAMP0_MAX_SAMPLES ((DDR3_MONITAMP0_END_ADDR-DDR3_MONITAMP0_START_ADDR) / DDR3_MONITAMP0_SAMPLE_SIZE)
......@@ -88,7 +88,7 @@
#define DDR3_MONITPOS0_MEM_SIZE 0
#define DDR3_MONITPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITPOS0_MEM_SIZE)
#define DDR3_MONITPOS0_START_ADDR (DDR3_MONITAMP0_END_ADDR + DDR3_MONITPOS0_MEM_BOOL*DDR3_MONITAMP0_SAMPLE_SIZE)
#define DDR3_MONITPOS0_START_ADDR (DDR3_MONITAMP0_END_ADDR + DDR3_MONITAMP0_MEM_BOOL*DDR3_MONITAMP0_SAMPLE_SIZE)
#define DDR3_MONITPOS0_END_ADDR (DDR3_MONITPOS0_START_ADDR + DDR3_MONITPOS0_MEM_SIZE*MEM_REGION_SIZE - DDR3_MONITPOS0_MEM_BOOL*DDR3_MONITPOS0_SAMPLE_SIZE)
#define DDR3_MONITPOS0_MAX_SAMPLES ((DDR3_MONITPOS0_END_ADDR-DDR3_MONITPOS0_START_ADDR) / DDR3_MONITPOS0_SAMPLE_SIZE)
......@@ -98,7 +98,7 @@
#define DDR3_MONIT1POS0_MEM_SIZE 0
#define DDR3_MONIT1POS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONIT1POS0_MEM_SIZE)
#define DDR3_MONIT1POS0_START_ADDR (DDR3_MONITPOS0_END_ADDR + DDR3_MONIT1POS0_MEM_BOOL*DDR3_MONITPOS0_SAMPLE_SIZE)
#define DDR3_MONIT1POS0_START_ADDR (DDR3_MONITPOS0_END_ADDR + DDR3_MONITPOS0_MEM_BOOL*DDR3_MONITPOS0_SAMPLE_SIZE)
#define DDR3_MONIT1POS0_END_ADDR (DDR3_MONIT1POS0_START_ADDR + DDR3_MONIT1POS0_MEM_SIZE*MEM_REGION_SIZE - DDR3_MONIT1POS0_MEM_BOOL*DDR3_MONIT1POS0_SAMPLE_SIZE)
#define DDR3_MONIT1POS0_MAX_SAMPLES ((DDR3_MONIT1POS0_END_ADDR-DDR3_MONIT1POS0_START_ADDR) / DDR3_MONIT1POS0_SAMPLE_SIZE)
......
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