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Beam Positoning Monitor - Software
Commit c171576c authored by Lucas Russo's avatar Lucas Russo
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include/hw: use new WB register maps 

The FPGA gateware was changed to uniformize
the WB register map for the FMC ACTIVE part.
parent fa4c67c1
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Showing with 73 additions and 73 deletions
include/hw/wb_fmc130m_4ch_regs.h
View file @ c171576c
......@@ -3,7 +3,7 @@
* File : fmc130m_4ch_regs.h
* Author : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
* Created : Fri May 16 20:05:39 2014
* Created : Fri Apr 15 17:13:52 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
......@@ -65,25 +65,25 @@
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: ADC LTC2208 control register (4 chips) */
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: RAND in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_RAND WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Temperate Alarm in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_TEMP_ALARM WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DITH in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_DITH WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: SHDN in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_SHDN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: PGA in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_PGA WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Clock distribution control register */
......@@ -105,25 +105,25 @@
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Monitor and FMC status control register */
/* definitions for register: ADC LTC2208 control register (4 chips) */
/* definitions for field: Temperate Alarm in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_TEMP_ALARM WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RAND in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_RAND WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DITH in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_DITH WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: SHDN in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_SHDN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PGA in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_PGA WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for field: Reserved in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: FPGA control */
......@@ -310,12 +310,12 @@
#define WB_FMC_130M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_130M_4CH_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_REG_ADC 0x00000008
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_REG_MONITOR 0x00000008
/* [0xc]: REG Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_REG_CLK_DISTRIB 0x0000000c
/* [0x10]: REG Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_REG_MONITOR 0x00000010
/* [0x10]: REG ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_REG_ADC 0x00000010
/* [0x14]: REG FPGA control */
#define WB_FMC_130M_4CH_CSR_REG_FPGA_CTRL 0x00000014
/* [0x18]: REG IDELAY ADC0 calibration */
......
include/hw/wb_fmc250m_4ch_regs.h
View file @ c171576c
......@@ -3,7 +3,7 @@
* File : fmc250m_4ch_regs.h
* Author : auto-generated by wbgen2 from wb_fmc250m_4ch_regs.wb
* Created : Mon Feb 22 10:48:46 2016
* Created : Fri Apr 15 16:48:45 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc250m_4ch_regs.wb
......@@ -34,39 +34,36 @@
/* definitions for register: Status register */
/* definitions for field: MMCM locked status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_MMCM_LOCKED WBGEN2_GEN_MASK(0, 1)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_MMCM_LOCKED WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC power good status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_PWR_GOOD WBGEN2_GEN_MASK(1, 1)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_PWR_GOOD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC board present status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_PRST WBGEN2_GEN_MASK(2, 1)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_PRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_MASK WBGEN2_GEN_MASK(3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_MASK WBGEN2_GEN_MASK(3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 28)
/* definitions for register: Clock distribution control register */
/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Trigger control */
/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Direction in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Monitor and FMC status control register */
......@@ -94,22 +91,25 @@
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* definitions for register: Trigger control */
/* definitions for register: Clock distribution control register */
/* definitions for field: Direction in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Global ADC Status register */
......@@ -526,13 +526,13 @@
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* [0x0]: REG Status register */
#define WB_FMC_250M_4CH_CSR_REG_FMC_STA 0x00000000
/* [0x4]: REG Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_REG_CLK_DISTRIB 0x00000004
#define WB_FMC_250M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_250M_4CH_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_REG_MONITOR 0x00000008
/* [0xc]: REG Trigger control */
#define WB_FMC_250M_4CH_CSR_REG_TRIGGER 0x0000000c
/* [0xc]: REG Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_REG_CLK_DISTRIB 0x0000000c
/* [0x10]: REG Global ADC Status register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_STA 0x00000010
/* [0x14]: REG Global ADC Control register */
......
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