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Beam Positoning Monitor - Software
Commit cf04d968 authored by Lucas Russo's avatar Lucas Russo Committed by Henrique Silva
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hal/*: add new acquisition channels for AFCv3

parent b26f1093
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Showing with 308 additions and 43 deletions
hal/include/board/afcv3/acq_chan_afcv3.h
View file @ cf04d968
......@@ -15,24 +15,52 @@
#define ADCSWAP0_CHAN_ID (ADC0_CHAN_ID + 1)
#define ADCSWAP0_SAMPLE_SIZE 8 /* 8 Bytes -> ADCSWAP0 = 16-bit / ADCSWAP1 = 16-bit ... */
/* MIXER I */
#define MIX0_CHAN_ID (ADCSWAP0_CHAN_ID + 1)
#define MIX0_SAMPLE_SIZE 16 /* 16 Bytes -> MIX0 = 32-bit / MIX1 = 32-bit ... */
/* MIXER I/Q 1/2 */
#define MIXIQ120_CHAN_ID (ADCSWAP0_CHAN_ID + 1)
#define MIXIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI0 = 32-bit / MIXQ0 = 32-bit ... */
/* MIXER I/Q 3/4 */
#define MIXIQ340_CHAN_ID (MIXIQ120_CHAN_ID + 1)
#define MIXIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI2 = 32-bit / MIXQ2 = 32-bit ... */
/* TBTDECIM I/Q 1/2 */
#define TBTDECIMIQ120_CHAN_ID (MIXIQ340_CHAN_ID + 1)
#define TBTDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* TBTDECIM I/Q 3/4 */
#define TBTDECIMIQ340_CHAN_ID (TBTDECIMIQ120_CHAN_ID + 1)
#define TBTDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* TBT AMP */
#define TBTAMP0_CHAN_ID (MIX0_CHAN_ID + 1)
#define TBTAMP0_CHAN_ID (TBTDECIMIQ340_CHAN_ID + 1)
#define TBTAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTAMP0 = 32-bit / TBTAMP1 = 32-bit ... */
/* TBT PHASE */
#define TBTPHA0_CHAN_ID (TBTAMP0_CHAN_ID + 1)
#define TBTPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTPHA0 = 32-bit / TBTPHA1 = 32-bit ... */
/* TBT POS */
#define TBTPOS0_CHAN_ID (TBTAMP0_CHAN_ID + 1)
#define TBTPOS0_CHAN_ID (TBTPHA0_CHAN_ID + 1)
#define TBTPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* FOFBDECIM I/Q 1/2 */
#define FOFBDECIMIQ120_CHAN_ID (TBTPOS0_CHAN_ID + 1)
#define FOFBDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* FOFBDECIM I/Q 3/4 */
#define FOFBDECIMIQ340_CHAN_ID (FOFBDECIMIQ120_CHAN_ID + 1)
#define FOFBDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* FOFB AMP */
#define FOFBAMP0_CHAN_ID (TBTPOS0_CHAN_ID + 1)
#define FOFBAMP0_CHAN_ID (FOFBDECIMIQ340_CHAN_ID + 1)
#define FOFBAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBAMP0 = 32-bit / FOFBAMP1 = 32-bit ... */
/* FOFB PHA */
#define FOFBPHA0_CHAN_ID (FOFBAMP0_CHAN_ID + 1)
#define FOFBPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBPHA0 = 32-bit / FOFBPHA1 = 32-bit ... */
/* FOFB POS */
#define FOFBPOS0_CHAN_ID (FOFBAMP0_CHAN_ID + 1)
#define FOFBPOS0_CHAN_ID (FOFBPHA0_CHAN_ID + 1)
#define FOFBPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT AMP */
......
hal/include/board/afcv3/ddr3_map_afcv3.h
View file @ cf04d968
This diff is collapsed.
hal/sm_io/modules/acq/ddr3_map.c
View file @ cf04d968
......@@ -84,11 +84,32 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIX0_CHAN_ID,
.start_addr = DDR3_MIX0_START_ADDR,
.end_addr = DDR3_MIX0_END_ADDR,
.max_samples = DDR3_MIX0_MAX_SAMPLES,
.sample_size = DDR3_MIX0_SAMPLE_SIZE
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ120_START_ADDR,
.end_addr = DDR3_MIXIQ120_END_ADDR,
.max_samples = DDR3_MIXIQ120_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ340_START_ADDR,
.end_addr = DDR3_MIXIQ340_END_ADDR,
.max_samples = DDR3_MIXIQ340_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ120_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ120_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ340_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ340_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
......@@ -97,6 +118,13 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_TBTAMP0_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.start_addr = DDR3_TBTPHA0_START_ADDR,
.end_addr = DDR3_TBTPHA0_END_ADDR,
.max_samples = DDR3_TBTPHA0_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.start_addr = DDR3_TBTPOS0_START_ADDR,
......@@ -104,6 +132,20 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_TBTPOS0_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ120_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ120_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ340_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ340_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.start_addr = DDR3_FOFBAMP0_START_ADDR,
......@@ -111,6 +153,13 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_FOFBAMP0_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.start_addr = DDR3_FOFBPHA0_START_ADDR,
.end_addr = DDR3_FOFBPHA0_END_ADDR,
.max_samples = DDR3_FOFBPHA0_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.start_addr = DDR3_FOFBPOS0_START_ADDR,
......@@ -157,11 +206,32 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIX0_CHAN_ID,
.start_addr = DDR3_MIX1_START_ADDR,
.end_addr = DDR3_MIX1_END_ADDR,
.max_samples = DDR3_MIX1_MAX_SAMPLES,
.sample_size = DDR3_MIX0_SAMPLE_SIZE
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ121_START_ADDR,
.end_addr = DDR3_MIXIQ121_END_ADDR,
.max_samples = DDR3_MIXIQ121_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ341_START_ADDR,
.end_addr = DDR3_MIXIQ341_END_ADDR,
.max_samples = DDR3_MIXIQ341_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ121_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ121_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ341_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ341_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
......@@ -170,6 +240,13 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_TBTAMP1_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.start_addr = DDR3_TBTPHA1_START_ADDR,
.end_addr = DDR3_TBTPHA1_END_ADDR,
.max_samples = DDR3_TBTPHA1_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.start_addr = DDR3_TBTPOS1_START_ADDR,
......@@ -177,6 +254,20 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_TBTPOS1_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ121_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ121_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ341_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ341_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.start_addr = DDR3_FOFBAMP1_START_ADDR,
......@@ -184,6 +275,13 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_FOFBAMP1_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.start_addr = DDR3_FOFBPHA1_START_ADDR,
.end_addr = DDR3_FOFBPHA1_END_ADDR,
.max_samples = DDR3_FOFBPHA1_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.start_addr = DDR3_FOFBPOS1_START_ADDR,
......
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