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Beam Positoning Monitor - Software
Commit d4f235ae authored by Juliano Murari's avatar Juliano Murari
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hal/sm_io/modules/acq: add new SMIO module

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hal/sm_io/modules/acq/acq.mk 0 → 100644
View file @ d4f235ae
sm_io_acq_DIR = hal/sm_io/modules/acq
sm_io_acq_OBJS = $(sm_io_acq_DIR)/sm_io_acq_core.o \
$(sm_io_acq_DIR)/sm_io_acq_exp.o \
$(sm_io_acq_DIR)/sm_io_acq_codes.o \
$(sm_io_acq_DIR)/ddr3_map.o
sm_io_acq_INCLUDE_DIRS = $(sm_io_acq_DIR)
hal/sm_io/modules/acq/ddr3_map.c 0 → 100644
View file @ d4f235ae
#include "ddr3_map.h"
const acq_buf_t __acq_buf[END_CHAN_ID] = {
{ADC_CHAN_ID, DDR3_ADC_START_ADDR, DDR3_ADC_END_ADDR, DDR3_ADC_MAX_SAMPLES, DDR3_ADC_SAMPLE_SIZE},
{TBTAMP_CHAN_ID, DDR3_TBTAMP_START_ADDR, DDR3_TBTAMP_END_ADDR, DDR3_TBTAMP_MAX_SAMPLES, DDR3_TBTAMP_SAMPLE_SIZE},
{TBTPOS_CHAN_ID, DDR3_TBTPOS_START_ADDR, DDR3_TBTPOS_END_ADDR, DDR3_TBTPOS_MAX_SAMPLES, DDR3_TBTPOS_SAMPLE_SIZE},
{FOFBAMP_CHAN_ID, DDR3_FOFBAMP_START_ADDR, DDR3_FOFBAMP_END_ADDR, DDR3_FOFBAMP_MAX_SAMPLES, DDR3_FOFBAMP_SAMPLE_SIZE},
{FOFBPOS_CHAN_ID, DDR3_FOFBPOS_START_ADDR, DDR3_FOFBPOS_END_ADDR, DDR3_FOFBPOS_MAX_SAMPLES, DDR3_FOFBPOS_SAMPLE_SIZE}
};
hal/sm_io/modules/acq/ddr3_map.h 0 → 100644
View file @ d4f235ae
#ifndef DDR3_MAP_H_
#define DDR3_MAP_H_
#include "wb_acq_core_regs.h"
/*************** Memory Regions *************/
#define MEM_TOTAL_SIZE (1 << 28) // 256 MB
#define MEM_REGION_SIZE (MEM_TOTAL_SIZE / 8)
#define BLOCK_SIZE 32768
/* FPGA Specific */
/* Do not touch these unless you know what you are doing! */
#define DDR3_PAYLOAD_SIZE 32 /* In Bytes: Virtex6 (ML605) and Artix7 (AFC) */
/* ADC */
#define ADC_CHAN_ID 0
#define DDR3_ADC_SAMPLE_SIZE 8 // 8 Bytes -> ADC0 = 16-bit / ADC1 = 16-bit ...
#define DDR3_ADC_START_ADDR 0x0
#define DDR3_ADC_END_ADDR (DDR3_ADC_START_ADDR + 2*MEM_REGION_SIZE - DDR3_ADC_SAMPLE_SIZE)
#define DDR3_ADC_MAX_SAMPLES ((DDR3_ADC_END_ADDR-DDR3_ADC_START_ADDR) / DDR3_ADC_SAMPLE_SIZE)
/* TBT AMP */
#define TBTAMP_CHAN_ID 1
#define DDR3_TBTAMP_SAMPLE_SIZE 16 // 16 Bytes -> TBTAMP0 = 32-bit / TBTAMP1 = 32-bit ...
#define DDR3_TBTAMP_START_ADDR (DDR3_ADC_END_ADDR + DDR3_ADC_SAMPLE_SIZE)
#define DDR3_TBTAMP_END_ADDR (DDR3_TBTAMP_START_ADDR + MEM_REGION_SIZE - DDR3_TBTAMP_SAMPLE_SIZE)
#define DDR3_TBTAMP_MAX_SAMPLES ((DDR3_TBTAMP_END_ADDR-DDR3_TBTAMP_START_ADDR) / DDR3_TBTAMP_SAMPLE_SIZE)
// TBT POS
#define TBTPOS_CHAN_ID 2
#define DDR3_TBTPOS_SAMPLE_SIZE 16 // 16 Bytes -> X = 32-bit / Y = 32-bit ...
#define DDR3_TBTPOS_START_ADDR (DDR3_TBTAMP_END_ADDR + DDR3_TBTAMP_SAMPLE_SIZE)
#define DDR3_TBTPOS_END_ADDR (DDR3_TBTPOS_START_ADDR + 2*MEM_REGION_SIZE - DDR3_TBTPOS_SAMPLE_SIZE)
#define DDR3_TBTPOS_MAX_SAMPLES ((DDR3_TBTPOS_END_ADDR-DDR3_TBTPOS_START_ADDR) / DDR3_TBTPOS_SAMPLE_SIZE)
// FOFB AMP
#define FOFBAMP_CHAN_ID 3
#define DDR3_FOFBAMP_SAMPLE_SIZE 16 // 16 Bytes -> FOFBAMP0 = 32-bit / FOFBAMP1 = 32-bit ...
#define DDR3_FOFBAMP_START_ADDR (DDR3_TBTPOS_END_ADDR + DDR3_TBTPOS_SAMPLE_SIZE)
#define DDR3_FOFBAMP_END_ADDR (DDR3_FOFBAMP_START_ADDR + MEM_REGION_SIZE - DDR3_FOFBAMP_SAMPLE_SIZE)
#define DDR3_FOFBAMP_MAX_SAMPLES ((DDR3_FOFBAMP_END_ADDR-DDR3_FOFBAMP_START_ADDR) / DDR3_FOFBAMP_SAMPLE_SIZE)
// FOFB POS
#define FOFBPOS_CHAN_ID 4
#define DDR3_FOFBPOS_SAMPLE_SIZE 16 // 16 Bytes -> X = 32-bit / Y = 32-bit ...
#define DDR3_FOFBPOS_START_ADDR (DDR3_FOFBAMP_END_ADDR + DDR3_FOFBAMP_SAMPLE_SIZE)
#define DDR3_FOFBPOS_END_ADDR (DDR3_FOFBPOS_START_ADDR + 2*MEM_REGION_SIZE - DDR3_FOFBPOS_SAMPLE_SIZE)
#define DDR3_FOFBPOS_MAX_SAMPLES ((DDR3_FOFBPOS_END_ADDR-DDR3_FOFBPOS_START_ADDR) / DDR3_FOFBPOS_SAMPLE_SIZE)
#define END_CHAN_ID 5
struct _acq_buf_t {
uint32_t id;
uint32_t start_addr;
uint32_t end_addr;
uint32_t max_samples;
uint32_t sample_size;
};
typedef struct _acq_buf_t acq_buf_t;
extern const acq_buf_t __acq_buf[END_CHAN_ID];
#endif
hal/sm_io/modules/acq/sm_io_acq_codes.c 0 → 100644
View file @ d4f235ae
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU LGPL, version 3 or any later version.
*/
#include <sm_io_acq_codes.h>
const uint32_t acq_reply_ops [ACQ_REPLY_END] = {
[0] = ACQ_REQ_OK,
[1] = ACQ_REQ_ERR,
[2] = ACQ_CHECK_OK,
[3] = ACQ_CHECK_ERR,
[4] = ACQ_BLOCK_OK,
[5] = ACQ_BLOCK_ERR
};
hal/sm_io/modules/acq/sm_io_acq_codes.h 0 → 100644
View file @ d4f235ae
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU LGPL, version 3 or any later version.
*/
#ifndef _SM_IO_ACQ_CODES_H_
#define _SM_IO_ACQ_CODES_H_
#include <inttypes.h>
/* Messaging Reply OPCODES */
#define ACQ_REPLY_SIZE (sizeof(uint32_t))
#define ACQ_REPLY_TYPE uint32_t
#define ACQ_REQ_OK 0
#define ACQ_REQ_ERR 1
#define ACQ_CHECK_OK 2
#define ACQ_CHECK_ERR 3
#define ACQ_BLOCK_OK 4
#define ACQ_BLOCK_ERR 5
#define ACQ_REPLY_END 6
extern const ACQ_REPLY_TYPE acq_reply_ops [ACQ_REPLY_END];
#endif
hal/sm_io/modules/acq/sm_io_acq_core.c 0 → 100644
View file @ d4f235ae
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU LGPL, version 3 or any later version.
*/
#include <stdlib.h>
#include <assert.h>
#include <czmq.h>
#include "sm_io_acq_core.h"
#include "sm_io_err.h"
#include "hal_assert.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_acq_core]", \
err_str, err_goto_label)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_acq_core]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io_acq_core]", \
smio_err_str (err_type))
/* Creates a new instance of Device Information */
smio_acq_t * smio_acq_new (uint32_t num_samples)
{
smio_acq_t *self = (smio_acq_t *) zmalloc (sizeof *self);
ASSERT_ALLOC(self, err_self_alloc);
/* Set default value for all channels */
for (uint32_t i = 0; i < END_CHAN_ID; i++) {
self->acq_params[i].num_samples = num_samples;
}
/* initilize acquisition buffer areas. Defined in ddr3_map.h */
self->acq_buf = __acq_buf;
return self;
err_self_alloc:
return NULL;
}
/* Destroy an instance of the Device Information */
smio_err_e smio_acq_destroy (smio_acq_t **self_p)
{
assert (self_p);
if (*self_p) {
smio_acq_t *self = *self_p;
self->acq_buf = NULL;
free (self);
*self_p = NULL;
}
return SMIO_SUCCESS;
}
hal/sm_io/modules/acq/sm_io_acq_core.h 0 → 100644
View file @ d4f235ae
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU LGPL, version 3 or any later version.
*/
#ifndef _SM_IO_ACQ_CORE_H_
#define _SM_IO_ACQ_CORE_H_
#include <inttypes.h>
#include "sm_io_err.h"
#include "ddr3_map.h"
typedef struct _acq_params_t {
uint32_t num_samples;
} acq_params_t;
struct _smio_acq_t {
acq_params_t acq_params[END_CHAN_ID];
const acq_buf_t *acq_buf;
};
/* Opaque class structure */
typedef struct _smio_acq_t smio_acq_t;
/***************** Our methods *****************/
/* Creates a new instance of the smio realizationn */
smio_acq_t * smio_acq_new (uint32_t num_samples);
/* Destroys the smio realizationn */
smio_err_e smio_acq_destroy (smio_acq_t **self_p);
#endif
hal/sm_io/modules/acq/sm_io_acq_exp.c 0 → 100644
View file @ d4f235ae
This diff is collapsed.
hal/sm_io/modules/acq/sm_io_acq_exp.h 0 → 100644
View file @ d4f235ae
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU LGPL, version 3 or any later version.
*/
#ifndef _ACQ_H_
#define _ACQ_H_
#include "sm_io_bootstrap.h"
#include "smio_thsafe_zmq_client.h"
#include "exp_ops_codes.h"
#include "sm_io_acq_core.h"
/* Known modules IDs (from SDB records defined in FPGA) */
#define ACQ_SDB_DEVID 0x4519a0ad
#define ACQ_SDB_NAME "ACQ"
extern const smio_bootstrap_ops_t acq_bootstrap_ops;
#endif
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