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Beam Positoning Monitor - Software
Commit dccf064b authored by Lucas Russo's avatar Lucas Russo Committed by Henrique Silva
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hal/*: add new ADC SWAP acquisition path 

Now we have a new acquisition channel, called
ADCSWAP which is the ADC RAW data after the switching
module.
parent c7d030f6
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Showing with 43 additions and 4 deletions
hal/include/board/afcv3/acq_chan_afcv3.h
View file @ dccf064b
......@@ -11,8 +11,12 @@
#define ADC0_CHAN_ID 0
#define ADC0_SAMPLE_SIZE 8 /* 8 Bytes -> ADC0 = 16-bit / ADC1 = 16-bit ... */
/* ADC SWAPPED (after the switching module) */
#define ADCSWAP0_CHAN_ID (ADC0_CHAN_ID + 1)
#define ADCSWAP0_SAMPLE_SIZE 8 /* 8 Bytes -> ADCSWAP0 = 16-bit / ADCSWAP1 = 16-bit ... */
/* MIXER I */
#define MIX0_CHAN_ID (ADC0_CHAN_ID + 1)
#define MIX0_CHAN_ID (ADCSWAP0_CHAN_ID + 1)
#define MIX0_SAMPLE_SIZE 16 /* 16 Bytes -> MIX0 = 32-bit / MIX1 = 32-bit ... */
/* TBT AMP */
......
hal/include/board/afcv3/ddr3_map_afcv3.h
View file @ dccf064b
......@@ -22,7 +22,7 @@
/************************ Acquistion 0 Channel Parameters **************/
/* ADC 0
/* ADC 0 (shares the same memory space as the ADCSWAP0)
* Size: 2 DDR3 regions */
#define DDR3_ADC0_SAMPLE_SIZE ADC0_SAMPLE_SIZE
#define DDR3_ADC0_MEM_SIZE 2
......@@ -32,13 +32,24 @@
#define DDR3_ADC0_END_ADDR (DDR3_ADC0_START_ADDR + DDR3_ADC0_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADC0_MEM_BOOL*DDR3_ADC0_SAMPLE_SIZE)
#define DDR3_ADC0_MAX_SAMPLES ((DDR3_ADC0_END_ADDR-DDR3_ADC0_START_ADDR) / DDR3_ADC0_SAMPLE_SIZE)
/* ADCSWAP 0 (shares the same memory space as the ADC0)
* Size: 2 DDR3 regions */
#define DDR3_ADCSWAP0_SAMPLE_SIZE ADCSWAP0_SAMPLE_SIZE
#define DDR3_ADCSWAP0_MEM_SIZE 2
#define DDR3_ADCSWAP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADCSWAP0_MEM_SIZE)
#define DDR3_ADCSWAP0_START_ADDR (DDR3_DUMMY_INIT0_START_ADDR + DDR3_DUMMY_INIT0_MEM_BOOL*DDR3_DUMMY_INIT0_SAMPLE_SIZE)
#define DDR3_ADCSWAP0_END_ADDR (DDR3_ADCSWAP0_START_ADDR + DDR3_ADCSWAP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_ADCSWAP0_MAX_SAMPLES ((DDR3_ADCSWAP0_END_ADDR-DDR3_ADCSWAP0_START_ADDR) / DDR3_ADCSWAP0_SAMPLE_SIZE)
/* MIXER 0
* Size: 1 DDR3 regions */
#define DDR3_MIX0_SAMPLE_SIZE MIX0_SAMPLE_SIZE
#define DDR3_MIX0_MEM_SIZE 1
#define DDR3_MIX0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIX0_MEM_SIZE)
#define DDR3_MIX0_START_ADDR (DDR3_ADC0_END_ADDR + DDR3_ADC0_MEM_BOOL*DDR3_ADC0_SAMPLE_SIZE)
#define DDR3_MIX0_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIX0_END_ADDR (DDR3_MIX0_START_ADDR + DDR3_MIX0_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIX0_MEM_BOOL*DDR3_MIX0_SAMPLE_SIZE)
#define DDR3_MIX0_MAX_SAMPLES ((DDR3_MIX0_END_ADDR-DDR3_MIX0_START_ADDR) / DDR3_MIX0_SAMPLE_SIZE)
......@@ -134,13 +145,23 @@
#define DDR3_ADC1_END_ADDR (DDR3_ADC1_START_ADDR + DDR3_ADC1_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADC1_MEM_BOOL*DDR3_ADC1_SAMPLE_SIZE)
#define DDR3_ADC1_MAX_SAMPLES ((DDR3_ADC1_END_ADDR-DDR3_ADC1_START_ADDR) / DDR3_ADC1_SAMPLE_SIZE)
/* ADCSWAP 1
* Size: 2 DDR3 regions */
#define DDR3_ADCSWAP1_SAMPLE_SIZE ADCSWAP0_SAMPLE_SIZE
#define DDR3_ADCSWAP1_MEM_SIZE 2
#define DDR3_ADCSWAP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADCSWAP1_MEM_SIZE)
#define DDR3_ADCSWAP1_START_ADDR (DDR3_DUMMY_END0_START_ADDR + DDR3_DUMMY_END0_MEM_BOOL*DDR3_DUMMY_END0_SAMPLE_SIZE)
#define DDR3_ADCSWAP1_END_ADDR (DDR3_ADCSWAP1_START_ADDR + DDR3_ADCSWAP1_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADCSWAP1_MEM_BOOL*DDR3_ADCSWAP1_SAMPLE_SIZE)
#define DDR3_ADCSWAP1_MAX_SAMPLES ((DDR3_ADCSWAP1_END_ADDR-DDR3_ADCSWAP1_START_ADDR) / DDR3_ADCSWAP1_SAMPLE_SIZE)
/* MIXER 1
* Size: 1 DDR3 regions */
#define DDR3_MIX1_SAMPLE_SIZE MIX0_SAMPLE_SIZE
#define DDR3_MIX1_MEM_SIZE 1
#define DDR3_MIX1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIX1_MEM_SIZE)
#define DDR3_MIX1_START_ADDR (DDR3_ADC1_END_ADDR + DDR3_ADC1_MEM_BOOL*DDR3_ADC1_SAMPLE_SIZE)
#define DDR3_MIX1_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP1_MEM_BOOL*DDR3_ADCSWAP1_SAMPLE_SIZE)
#define DDR3_MIX1_END_ADDR (DDR3_MIX1_START_ADDR + DDR3_MIX1_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIX1_MEM_BOOL*DDR3_MIX1_SAMPLE_SIZE)
#define DDR3_MIX1_MAX_SAMPLES ((DDR3_MIX1_END_ADDR-DDR3_MIX1_START_ADDR) / DDR3_MIX1_SAMPLE_SIZE)
......
hal/sm_io/modules/acq/ddr3_map.c
View file @ dccf064b
......@@ -76,6 +76,13 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_ADC0_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.start_addr = DDR3_ADCSWAP0_START_ADDR,
.end_addr = DDR3_ADCSWAP0_END_ADDR,
.max_samples = DDR3_ADCSWAP0_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIX0_CHAN_ID,
.start_addr = DDR3_MIX0_START_ADDR,
......@@ -142,6 +149,13 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
.max_samples = DDR3_ADC1_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.start_addr = DDR3_ADCSWAP1_START_ADDR,
.end_addr = DDR3_ADCSWAP1_END_ADDR,
.max_samples = DDR3_ADCSWAP1_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIX0_CHAN_ID,
.start_addr = DDR3_MIX1_START_ADDR,
......
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