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Conv TTL Blocking - Gateware
Commit 2710324a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Checking something on i2c-test branch

parent 8760fc48
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Showing with 478 additions and 278 deletions
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ 2710324a
......@@ -14,7 +14,7 @@ NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
NET "CLK20_VCXO" LOC = E16;
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
#TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
......
hdl/IMAGES/image1/project/image1.xise
View file @ 2710324a
......@@ -17,23 +17,23 @@
<files>
<file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
......@@ -41,7 +41,7 @@
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
......@@ -81,7 +81,7 @@
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
......@@ -141,7 +141,7 @@
</file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
......@@ -149,7 +149,7 @@
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
......@@ -186,7 +186,7 @@
</file>
<file xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 2710324a
......@@ -52,7 +52,7 @@ use UNISIM.VCOMPONENTS.ALL;
entity image1_core is
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6
g_number_of_channels : NATURAL := 6
);
port
(
......@@ -62,14 +62,14 @@ entity image1_core is
-- LEDs
led_array_o : out t_led_array_o;
led_front_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_front_n_o : out std_logic_vector(g_number_of_channels downto 1);
led_rear_n_o : out std_logic_vector(g_number_of_channels downto 1);
-- I/Os for pulses
pulse_front_n_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_front_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_front_n_i : in std_logic_vector(g_number_of_channels downto 1);
pulse_front_o : out std_logic_vector(g_number_of_channels downto 1);
pulse_rear_i : in std_logic_vector(g_number_of_channels downto 1);
pulse_rear_o : out std_logic_vector(g_number_of_channels downto 1);
inv_n_i : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1);
......@@ -87,7 +87,7 @@ entity image1_core is
-- Enable signals
fpga_en_o : out std_logic;
fpga_out_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
......@@ -109,16 +109,92 @@ end image1_core;
architecture Behavioral of image1_core is
--============================================================================
-- Constant declarations
--============================================================================
constant c_nr_masters : NATURAL := 1;
constant c_nr_slaves : NATURAL := 2;
constant c_master_i2c_bridge : NATURAL := 0;
constant c_slave_statregs : natural := 0;
constant c_slave_i2c_bridge : NATURAL := 1;
constant c_slave_multiboot : NATURAL := 2;
constant c_slave_m25p32 : NATURAL := 3;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word aligned
-----------------------------------------
-- M25P32 [0200-03FF]
-- MULTIBOOT [0080-00CF]
-- I2C_SLAVE [0040-007F]
-- SR [0000-003F]
-----------------------------------------
-- base address definitions
constant c_addr_statregs : t_wishbone_address := x"00000000";
constant c_addr_i2c_bridge : t_wishbone_address := X"00000040";
constant c_addr_multiboot : t_wishbone_address := X"00000080";
constant c_addr_m25p32 : t_wishbone_address := X"00000200";
-- address mask definitions
-- 64 words per page: 6 + 1 bits
constant c_mask_statregs : t_wishbone_address := x"FFFFFFC0";
constant c_mask_i2c_bridge : t_wishbone_address := X"FFFFFFC0";
constant c_mask_multiboot : t_wishbone_address := X"FFFFFFC0";
constant c_mask_m25p32 : t_wishbone_address := X"FFFFFE00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_addr_m25p32,
--c_addr_multiboot,
c_addr_statregs,
c_addr_i2c_bridge);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_mask_m25p32,
-- c_mask_multiboot,
c_mask_statregs,
c_mask_i2c_bridge);
--============================================================================
-- Component declarations
--============================================================================
component statregs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'IDENT_L' in reg: 'SR_L'
sr_l_ident_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'IDENT_H' in reg: 'SR_H'
sr_h_ident_h_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'RTMM' in reg: 'SR_H'
sr_h_rtmm_i : in std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'RTMP' in reg: 'SR_H'
sr_h_rtmp_i : in std_logic_vector(2 downto 0)
);
end component statregs;
component basic_trigger_top
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns
g_number_of_channels : NATURAL := 6;
g_clk_period : TIME := 20 ns;
g_pulse_length : TIME := 1000 ns;
g_led_blinking_length : TIME := (10**6)*250 ns
);
port
(
......@@ -127,7 +203,7 @@ architecture Behavioral of image1_core is
led_ttl_o : out STD_LOGIC;
fpga_en_o : out STD_LOGIC;
fpga_out_en_o : out STD_LOGIC;
fpga_ttl_en_o : out STD_LOGIC;
fpga_inv_en_o : out STD_LOGIC;
fpga_blo_en_o : out STD_LOGIC;
......@@ -137,40 +213,20 @@ architecture Behavioral of image1_core is
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_front_i : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_front_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_front_i : in STD_LOGIC_VECTOR(g_number_of_channels downto 1);
pulse_front_o : out STD_LOGIC_VECTOR(g_number_of_channels downto 1);
pulse_rear_i : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_i : in STD_LOGIC_VECTOR(g_number_of_channels downto 1);
pulse_rear_o : out STD_LOGIC_VECTOR(g_number_of_channels downto 1);
led_front_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_rear_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_front_o : out STD_LOGIC_VECTOR(g_number_of_channels downto 1);
led_rear_o : out STD_LOGIC_VECTOR(g_number_of_channels downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1)
);
end component;
-- Trigger leds I2C test component
component test_trigleds_wb is
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Bits' in reg: 'LED'
trigleds_reg_bits_o : out std_logic_vector(5 downto 0)
);
end component test_trigleds_wb;
-- I2C bridge top-level
component i2c_slave_top
generic
......@@ -250,10 +306,10 @@ architecture Behavioral of image1_core is
signal rtmp_ok : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_NUM_SLAVES - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_NUM_SLAVES - 1 downto 0);
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_nr_slaves - 1 downto 0);
-- Internal I2C signals
signal i2c_addr : std_logic_vector(6 downto 0);
......@@ -262,15 +318,15 @@ architecture Behavioral of image1_core is
signal i2c_up : std_logic;
-- Internal pulse signal
signal pulse_front_in : std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
signal pulse_front_in : std_logic_vector(g_number_of_channels downto 1);
-- Internal signals for bicolor LED matrix control
signal leds_array : t_leds_array;
signal led_state_array : t_led_state_array(c_NB_ARRAY_LEDS - 1 downto 0);
-- !!!!!!!!!!!!!!!!!!!
-- I2C test front panel LED signal
signal trigleds : std_logic_vector(5 downto 0);
-- Front and rear pulse LED signals
signal led_front : std_logic_vector(g_number_of_channels downto 1);
signal led_rear : std_logic_vector(g_number_of_channels downto 1);
begin
......@@ -356,17 +412,17 @@ begin
cmp_basic_trigger: basic_trigger_top
generic map
(
g_NUMBER_OF_CHANNELS => c_NUMBER_OF_CHANNELS,
g_CLK_PERIOD => c_CLKB_PERIOD,
g_OUTPUT_PULSE_LENGTH => c_OUTPUT_PULSE_LENGTH,
g_LED_BLINKING_LENGTH => c_LED_BLINKING_LENGTH
g_number_of_channels => g_number_of_channels,
g_clk_period => c_CLKB_PERIOD,
g_pulse_length => c_OUTPUT_PULSE_LENGTH,
g_led_blinking_length => c_LED_BLINKING_LENGTH
)
port map
(
clk_i => clk_200,
rst_i => rst_i, -- s_rst.SYS_B(c_RST_B_CLKS - 1),
rst_i => rst_i,
led_ttl_o => leds_array.top.TTL_N,
fpga_en_o => fpga_en_o,
fpga_out_en_o => fpga_out_en_o,
fpga_ttl_en_o => fpga_ttl_en_o,
fpga_inv_en_o => fpga_inv_en_o,
fpga_blo_en_o => fpga_blo_en_o,
......@@ -377,21 +433,49 @@ begin
pulse_front_o => pulse_front_o,
pulse_rear_i => pulse_rear_i,
pulse_rear_o => pulse_rear_o,
led_front_o => open, -- led_front_n_o,
led_rear_o => led_rear_n_o,
led_front_o => led_front,
led_rear_o => led_rear,
inv_i => inv_n_i,
inv_o => inv_o
);
-- Assign pulse LED outputs
led_front_n_o <= not led_front;
led_rear_n_o <= not led_rear;
cmp_statregs: statregs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk_50,
wb_adr_i => xbar_master_out(c_slave_statregs).adr,
wb_dat_i => xbar_master_out(c_slave_statregs).dat,
wb_dat_o => xbar_master_in(c_slave_statregs).dat,
wb_cyc_i => xbar_master_out(c_slave_statregs).cyc,
wb_sel_i => xbar_master_out(c_slave_statregs).sel,
wb_stb_i => xbar_master_out(c_slave_statregs).stb,
wb_we_i => xbar_master_out(c_slave_statregs).we,
wb_ack_o => xbar_master_in(c_slave_statregs).ack,
wb_stall_o => xbar_master_in(c_slave_statregs).stall,
-- Port for std_logic_vector field: 'IDENT_L' in reg: 'SR_L'
sr_l_ident_l_i => (others => '0'),
-- Port for std_logic_vector field: 'IDENT_H' in reg: 'SR_H'
sr_h_ident_h_i => (others => '0'),
-- Port for std_logic_vector field: 'RTMM' in reg: 'SR_H'
sr_h_rtmm_i => rtmm_i,
-- Port for std_logic_vector field: 'RTMP' in reg: 'SR_H'
sr_h_rtmp_i => rtmp_i
);
--============================================================================
-- I2C slave module instantiation and connections
--============================================================================
--
-- -- xbar_slave_out(c_MASTER_I2C_SLAVE).stall;
-- -- xbar_slave_out(c_MASTER_I2C_SLAVE).int;
-- -- xbar_master_in(c_SLAVE_I2C_SLAVE).stall,
-- -- xbar_master_in(c_SLAVE_I2C_SLAVE).int,
-- -- xbar_slave_out(c_master_i2c_bridge).stall;
-- -- xbar_slave_out(c_master_i2c_bridge).int;
-- -- xbar_master_in(c_slave_i2c_bridge).stall,
-- -- xbar_master_in(c_slave_i2c_bridge).int,
--
cmp_i2c_slave: i2c_slave_top
port map
......@@ -404,33 +488,33 @@ begin
scl_o => i2c_slave_o.SCL_O,
wb_clk_i => clk_50,
wb_rst_i => rst_i,
wb_master_stb_o => xbar_slave_in(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => xbar_slave_in(c_MASTER_I2C_SLAVE).cyc,
wb_master_sel_o => xbar_slave_in(c_MASTER_I2C_SLAVE).sel,
wb_master_we_o => xbar_slave_in(c_MASTER_I2C_SLAVE).we,
wb_master_dat_i => xbar_slave_out(c_MASTER_I2C_SLAVE).dat,
wb_master_dat_o => xbar_slave_in(c_MASTER_I2C_SLAVE).dat,
wb_master_adr_o => xbar_slave_in(c_MASTER_I2C_SLAVE).adr(15 downto 0),
wb_master_ack_i => xbar_slave_out(c_MASTER_I2C_SLAVE).ack,
wb_master_rty_i => xbar_slave_out(c_MASTER_I2C_SLAVE).rty,
wb_master_err_i => xbar_slave_out(c_MASTER_I2C_SLAVE).err,
wb_slave_stb_i => xbar_master_out(c_SLAVE_I2C_SLAVE).stb,
wb_slave_cyc_i => xbar_master_out(c_SLAVE_I2C_SLAVE).cyc,
wb_slave_sel_i => xbar_master_out(c_SLAVE_I2C_SLAVE).sel,
wb_slave_we_i => xbar_master_out(c_SLAVE_I2C_SLAVE).we,
wb_slave_dat_i => xbar_master_out(c_SLAVE_I2C_SLAVE).dat,
wb_slave_dat_o => xbar_master_in(c_SLAVE_I2C_SLAVE).dat,
wb_slave_adr_i => xbar_master_out(c_SLAVE_I2C_SLAVE).adr( 5 downto 2),
wb_slave_ack_o => xbar_master_in(c_SLAVE_I2C_SLAVE).ack,
wb_slave_rty_o => xbar_master_in(c_SLAVE_I2C_SLAVE).rty,
wb_slave_err_o => xbar_master_in(c_SLAVE_I2C_SLAVE).err,
wb_master_stb_o => xbar_slave_in(c_master_i2c_bridge).stb,
wb_master_cyc_o => xbar_slave_in(c_master_i2c_bridge).cyc,
wb_master_sel_o => xbar_slave_in(c_master_i2c_bridge).sel,
wb_master_we_o => xbar_slave_in(c_master_i2c_bridge).we,
wb_master_dat_i => xbar_slave_out(c_master_i2c_bridge).dat,
wb_master_dat_o => xbar_slave_in(c_master_i2c_bridge).dat,
wb_master_adr_o => xbar_slave_in(c_master_i2c_bridge).adr(15 downto 0),
wb_master_ack_i => xbar_slave_out(c_master_i2c_bridge).ack,
wb_master_rty_i => xbar_slave_out(c_master_i2c_bridge).rty,
wb_master_err_i => xbar_slave_out(c_master_i2c_bridge).err,
wb_slave_stb_i => xbar_master_out(c_slave_i2c_bridge).stb,
wb_slave_cyc_i => xbar_master_out(c_slave_i2c_bridge).cyc,
wb_slave_sel_i => xbar_master_out(c_slave_i2c_bridge).sel,
wb_slave_we_i => xbar_master_out(c_slave_i2c_bridge).we,
wb_slave_dat_i => xbar_master_out(c_slave_i2c_bridge).dat,
wb_slave_dat_o => xbar_master_in(c_slave_i2c_bridge).dat,
wb_slave_adr_i => xbar_master_out(c_slave_i2c_bridge).adr( 5 downto 2),
wb_slave_ack_o => xbar_master_in(c_slave_i2c_bridge).ack,
wb_slave_rty_o => xbar_master_in(c_slave_i2c_bridge).rty,
wb_slave_err_o => xbar_master_in(c_slave_i2c_bridge).err,
pf_wb_addr_o => open,
rd_done_o => i2c_rd_done,
wr_done_o => i2c_wr_done,
i2c_addr_i => i2c_addr
);
xbar_slave_in(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
xbar_slave_in(c_master_i2c_bridge).adr(31 downto 16) <= (others => '0');
-- Process to set the I2C_UP signal for display on the front panel
-- of the front module. The I2C_UP signal is permanently set once an
......@@ -454,16 +538,16 @@ begin
-- inst_m25p32: m25p32_top
-- port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
-- wb_clk => clk_50,
-- wb_we_i => xbar_master_out(c_SLAVE_M25P32).we,
-- wb_stb_i => xbar_master_out(c_SLAVE_M25P32).stb,
-- wb_cyc_i => xbar_master_out(c_SLAVE_M25P32).cyc,
-- wb_sel_i => xbar_master_out(c_SLAVE_M25P32).sel,
-- wb_data_i => xbar_master_out(c_SLAVE_M25P32).dat,
-- wb_data_o => xbar_master_in(c_SLAVE_M25P32).dat,
-- wb_addr_i => xbar_master_out(c_SLAVE_M25P32).adr( 8 downto 2),
-- wb_ack_o => xbar_master_in(c_SLAVE_M25P32).ack,
-- wb_rty_o => xbar_master_in(c_SLAVE_M25P32).rty,
-- wb_err_o => xbar_master_in(c_SLAVE_M25P32).err,
-- wb_we_i => xbar_master_out(c_slave_m25p32).we,
-- wb_stb_i => xbar_master_out(c_slave_m25p32).stb,
-- wb_cyc_i => xbar_master_out(c_slave_m25p32).cyc,
-- wb_sel_i => xbar_master_out(c_slave_m25p32).sel,
-- wb_data_i => xbar_master_out(c_slave_m25p32).dat,
-- wb_data_o => xbar_master_in(c_slave_m25p32).dat,
-- wb_addr_i => xbar_master_out(c_slave_m25p32).adr( 8 downto 2),
-- wb_ack_o => xbar_master_in(c_slave_m25p32).ack,
-- wb_rty_o => xbar_master_in(c_slave_m25p32).rty,
-- wb_err_o => xbar_master_in(c_slave_m25p32).err,
-- miso_word_rcv => open,
-- op_finished_o => open,
-- prom_mosi_o => spi_master_o.MOSI,
......@@ -475,36 +559,35 @@ begin
-- inst_multiboot: multiboot_top
-- port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
-- wb_clk => clk_50,
-- wb_we_i => xbar_master_out(c_SLAVE_MULTIBOOT).we,
-- wb_stb_i => xbar_master_out(c_SLAVE_MULTIBOOT).stb,
-- wb_cyc_i => xbar_master_out(c_SLAVE_MULTIBOOT).cyc,
-- wb_sel_i => xbar_master_out(c_SLAVE_MULTIBOOT).sel,
-- wb_data_i => xbar_master_out(c_SLAVE_MULTIBOOT).dat,
-- wb_data_o => xbar_master_in(c_SLAVE_MULTIBOOT).dat,
-- wb_addr_i => xbar_master_out(c_SLAVE_MULTIBOOT).adr( 5 downto 2),
-- wb_ack_o => xbar_master_in(c_SLAVE_MULTIBOOT).ack,
-- wb_rty_o => xbar_master_in(c_SLAVE_MULTIBOOT).rty,
-- wb_err_o => xbar_master_in(c_SLAVE_MULTIBOOT).err);
-- wb_we_i => xbar_master_out(c_slave_multiboot).we,
-- wb_stb_i => xbar_master_out(c_slave_multiboot).stb,
-- wb_cyc_i => xbar_master_out(c_slave_multiboot).cyc,
-- wb_sel_i => xbar_master_out(c_slave_multiboot).sel,
-- wb_data_i => xbar_master_out(c_slave_multiboot).dat,
-- wb_data_o => xbar_master_in(c_slave_multiboot).dat,
-- wb_addr_i => xbar_master_out(c_slave_multiboot).adr( 5 downto 2),
-- wb_ack_o => xbar_master_in(c_slave_multiboot).ack,
-- wb_rty_o => xbar_master_in(c_slave_multiboot).rty,
-- wb_err_o => xbar_master_in(c_slave_multiboot).err);
--
--
--============================================================================
-- Instantiation and connection of a Wishbone crossbar module
--============================================================================
xbar_master_in(c_SLAVE_I2C_SLAVE).stall <= '0';
xbar_master_in(c_SLAVE_I2C_SLAVE).int <= '0';
xbar_master_in(c_slave_trigleds_wb).int <= '0';
xbar_master_in(c_slave_i2c_bridge).stall <= '0';
xbar_master_in(c_slave_i2c_bridge).int <= '0';
-- xbar_master_in(c_SLAVE_M25P32).stall <= '0';
-- xbar_master_in(c_SLAVE_M25P32).int <= '0';
-- xbar_master_in(c_SLAVE_MULTIBOOT).stall <= '0';
-- xbar_master_in(c_SLAVE_MULTIBOOT).int <= '0';
-- xbar_master_in(c_slave_m25p32).stall <= '0';
-- xbar_master_in(c_slave_m25p32).int <= '0';
-- xbar_master_in(c_slave_multiboot).stall <= '0';
-- xbar_master_in(c_slave_multiboot).int <= '0';
cmp_wb_crossbar: xwb_crossbar
generic map
(
g_num_masters => c_NUM_MASTERS,
g_num_slaves => c_NUM_SLAVES,
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
-- Address of the slaves connected
-- It should be noted that the default address length is 32
......@@ -522,29 +605,6 @@ begin
master_o => xbar_master_out
);
--============================================================================
-- I2C test trigger LEDs instantiation and connections
--============================================================================
cmp_test_trigleds: test_trigleds_wb
port map
(
rst_n_i => rst_n,
clk_sys_i => clk_50,
wb_dat_i => xbar_master_out(c_slave_trigleds_wb).dat,
wb_dat_o => xbar_master_in(c_slave_trigleds_wb).dat,
wb_cyc_i => xbar_master_out(c_slave_trigleds_wb).cyc,
wb_sel_i => xbar_master_out(c_slave_trigleds_wb).sel,
wb_stb_i => xbar_master_out(c_slave_trigleds_wb).stb,
wb_we_i => xbar_master_out(c_slave_trigleds_wb).we,
wb_ack_o => xbar_master_in(c_slave_trigleds_wb).ack,
wb_stall_o => xbar_master_in(c_slave_trigleds_wb).stall,
-- Port for std_logic_vector field: 'Bits' in reg: 'LED'
trigleds_reg_bits_o => trigleds
);
-- !!!!!
led_front_n_o <= not trigleds;
--============================================================================
-- RTM detection module
--============================================================================
......
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 2710324a
......@@ -65,60 +65,11 @@ package image1_pkg is
constant c_WB_CLK_PERIOD : TIME := (c_CLKOUTA_DIVIDE*c_PLL_IN_PERIOD)/c_CLKFBOUT_MULT;
constant c_CLKB_PERIOD : TIME := (c_CLKOUTB_DIVIDE*c_PLL_IN_PERIOD)/c_CLKFBOUT_MULT;
constant c_RST_TIME : TIME := 250 ns;
constant c_RST_TIME : TIME := 250 ns;
constant c_RST_PLL_CLKS : NATURAL := c_RST_TIME/c_PLL_IN_PERIOD;
constant c_RST_A_CLKS : NATURAL := c_RST_TIME/c_WB_CLK_PERIOD;
constant c_RST_B_CLKS : NATURAL := c_RST_TIME/c_CLKB_PERIOD;
constant c_NUM_MASTERS : NATURAL := 1;
constant c_NUM_SLAVES : NATURAL := 2;
constant c_MASTER_I2C_SLAVE : NATURAL := 0;
constant c_SLAVE_I2C_SLAVE : NATURAL := 0;
-- !!!!!!!!!!!!!!!!
constant c_slave_trigleds_wb : natural := 1;
-- !!!!!!!!!!!!!!!!
constant c_SLAVE_MULTIBOOT : NATURAL := 1;
constant c_SLAVE_M25P32 : NATURAL := 2;
--! ==================================
--! MEMORY MAPPINGS
--! ==================================
--! Byte aligned
--! It should be noted that all internal modules are word aligned.
--! Thus, access to byte 1,2 or 3 within an internal word register
--! will be processed as an access to such register (indeed, like
--! accessing to byte 0).
--! ==================================
--! M25P32 [0200-03FF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! ==================================
constant c_ADDR_M25P32 : t_wishbone_address := X"00000200";
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000080";
constant c_ADDR_I2C_SLAVE : t_wishbone_address := X"00000040";
-- !!
constant c_addr_trigleds_wb : t_wishbone_address := X"00000080";
--! 64 words per page: 6 + 1 bits
constant c_MASK_M25P32 : t_wishbone_address := X"FFFFFE00";
constant c_MASK_MULTIBOOT : t_wishbone_address := X"FFFFFFC0";
constant c_MASK_I2C_SLAVE : t_wishbone_address := X"FFFFFFC0";
-- !!!!!!!
constant c_mask_trigleds_wb : t_wishbone_address := X"FFFFFFC0";
constant c_addresses : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (--c_ADDR_M25P32,
--c_ADDR_MULTIBOOT,
c_addr_trigleds_wb,
c_ADDR_I2C_SLAVE);
constant c_masks : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (--c_MASK_M25P32,
-- c_MASK_MULTIBOOT,
c_mask_trigleds_wb,
c_MASK_I2C_SLAVE);
-- component basic_trigger_top
-- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
-- g_CLK_PERIOD : TIME := 20 ns;
......@@ -194,53 +145,53 @@ package image1_pkg is
-- );
-- end component;
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port(wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC);
end component;
component multiboot_top
generic(g_MBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_MBA_map_addr);
g_GBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_GBA_map_addr);
--! This is a vendor-dependant SPI opcode.
--! Pleasem take a look to the flash memory manual and put here
--! the op-code/instruction-code for a read operation over SPI
--! i.e. for m25p32 memory that corresponds to X"03"
--! Set it up accordingly.
g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
port(wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
end component;
-- component m25p32_top
-- generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
-- port(wb_rst_i : in STD_LOGIC;
-- wb_clk_i : in STD_LOGIC;
--
-- wb_we_i : in STD_LOGIC;
-- wb_stb_i : in STD_LOGIC;
-- wb_cyc_i : in STD_LOGIC;
-- wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
-- wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
-- wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
-- wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
-- wb_ack_o : out STD_LOGIC;
-- wb_rty_o : out STD_LOGIC;
-- wb_err_o : out STD_LOGIC;
--
-- miso_word_rcv : out STD_LOGIC;
-- op_finished_o : out STD_LOGIC;
--
-- prom_mosi_o : out STD_LOGIC;
-- prom_cclk_o : out STD_LOGIC;
-- prom_cs0_b_n_o : out STD_LOGIC;
-- prom_din_i : in STD_LOGIC);
-- end component;
--
-- component multiboot_top
-- generic(g_MBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_MBA_map_addr);
-- g_GBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_GBA_map_addr);
-- --! This is a vendor-dependant SPI opcode.
-- --! Pleasem take a look to the flash memory manual and put here
-- --! the op-code/instruction-code for a read operation over SPI
-- --! i.e. for m25p32 memory that corresponds to X"03"
-- --! Set it up accordingly.
-- g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
-- port(wb_rst_i : in STD_LOGIC;
-- wb_clk_i : in STD_LOGIC;
-- wb_we_i : in STD_LOGIC;
-- wb_stb_i : in STD_LOGIC;
-- wb_cyc_i : in STD_LOGIC;
-- wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
-- wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
-- wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
-- wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
-- wb_ack_o : out STD_LOGIC;
-- wb_rty_o : out STD_LOGIC;
-- wb_err_o : out STD_LOGIC);
-- end component;
-- component rtm_detector
-- generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
......
hdl/IMAGES/image1/rtl/sr.wb 0 → 100644
View file @ 2710324a
peripheral {
name = "Wishbone interface for CONV-TTL-BLO status register";
hdl_entity = "statregs";
prefix = "sr";
-- lower 32 bits of SR corresponding to IDENT_L
reg {
name = "SR_L";
prefix = "l";
field {
name = "IDENT_L";
description = "Lower 32 bits of IDENT register";
prefix = "ident_l";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Upper 32 bits of SR
reg {
name = "SR_H";
prefix = "h";
field {
name = "IDENT_H";
description = "Upper 16 bits of IDENT register";
prefix = "ident_h";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTMM";
description = "RTMM identification bits";
prefix = "rtmm";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTMP";
description = "RTMP identification bits";
prefix = "rtmp";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/IMAGES/image1/rtl/statregs.vhd 0 → 100644
View file @ 2710324a
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone interface for CONV-TTL-BLO status register
---------------------------------------------------------------------------------------
-- File : statregs.vhd
-- Author : auto-generated by wbgen2 from sr.wb
-- Created : Fri Feb 22 17:54:47 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity statregs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'IDENT_L' in reg: 'SR_L'
sr_l_ident_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'IDENT_H' in reg: 'SR_H'
sr_h_ident_h_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'RTMM' in reg: 'SR_H'
sr_h_rtmm_i : in std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'RTMP' in reg: 'SR_H'
sr_h_rtmp_i : in std_logic_vector(2 downto 0)
);
end statregs;
architecture syn of statregs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= sr_l_ident_l_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= sr_h_ident_h_i;
rddata_reg(18 downto 16) <= sr_h_rtmm_i;
rddata_reg(21 downto 19) <= sr_h_rtmp_i;
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- IDENT_L
-- IDENT_H
-- RTMM
-- RTMP
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/IMAGES/image1/top/image1_top.vhd
View file @ 2710324a
......@@ -42,10 +42,6 @@ use work.wishbone_pkg.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity image1_top is
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6
);
port
(
RST : in std_logic;
......@@ -66,12 +62,12 @@ entity image1_top is
LED_WR_OWNADDR_I2C : out std_logic;
-- I/Os for pulses
PULSE_FRONT_LED_N : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
PULSE_FRONT_LED_N : out std_logic_vector(6 downto 1);
PULSE_REAR_LED_N : out std_logic_vector(6 downto 1);
FPGA_INPUT_TTL_N : in std_logic_vector(6 downto 1);
FPGA_OUT_TTL : out std_logic_vector(6 downto 1);
FPGA_BLO_IN : in std_logic_vector(6 downto 1);
FPGA_TRIG_BLO : out std_logic_vector(6 downto 1);
INV_IN_N : in std_logic_vector(4 downto 1);
INV_OUT : out std_logic_vector(4 downto 1);
......@@ -95,10 +91,16 @@ entity image1_top is
FPGA_BLO_OE : out std_logic;
FPGA_TRIG_TTL_OE : out std_logic;
FPGA_INV_OE : out std_logic;
LEVEL : in std_logic;--TTL/INV_TTL_N
EXTRA_SWITCH : in std_logic_vector(1 downto 1);--! General enable
MR_N : out std_logic;-- It allows power sequencing of the
-- 24V rail after a security given delay
--TTL/INV_TTL_N
LEVEL : in std_logic;
EXTRA_SWITCH : in std_logic_vector(7 downto 1);
-- It allows power sequencing of the
-- 24V rail after a security given delay
MR_N : out std_logic;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
......@@ -148,7 +150,7 @@ architecture Behavioral of image1_top is
-- Enable signals
fpga_en_o : out std_logic;
fpga_out_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
......@@ -175,7 +177,7 @@ architecture Behavioral of image1_top is
signal s_spi_master_i : t_spi_master_i;
signal s_spi_master_o : t_spi_master_o;
signal s_rtm_i : t_rtm_i;
signal switch : std_logic_vector(1 downto 1);
signal switch : std_logic_vector(7 downto 1);
signal rtmm, rtmp : std_logic_vector(2 downto 0);
......@@ -223,7 +225,10 @@ begin
switch <= EXTRA_SWITCH;
cmp_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
generic map
(
g_number_of_channels => 6
)
port map
(
rst_i => RST,
......@@ -244,7 +249,7 @@ begin
fpga_gap_i => FPGA_GAP,
spi_master_i => s_spi_master_i,
spi_master_o => s_spi_master_o,
fpga_en_o => FPGA_OE,
fpga_out_en_o => FPGA_OE,
fpga_blo_en_o => FPGA_BLO_OE,
fpga_ttl_en_o => FPGA_TRIG_TTL_OE,
fpga_inv_en_o => FPGA_INV_OE,
......
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 2710324a
......@@ -43,7 +43,7 @@ entity basic_trigger_top is
led_ttl_o : out std_logic;
-- Enable signals
fpga_en_o : out std_logic;
fpga_out_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
......@@ -124,27 +124,27 @@ begin
-- +---------+-----------------+
-- | level_i | Switch | Level |
-- +---------+---------+-------+
-- | 0 TTL | UP | TTL |
-- | 1 TTL_N | DOWN | TTL_N |
-- | 0 | UP | TTL |
-- | 1 | DOWN | TTL_N |
-- +---------+---------+-------+
level <= level_i;
led_ttl_o <= level;
-- pulse signal assignments
pulse_in_front <= pulse_front_i when (level = '0') else
not pulse_front_i;
pulse_in <= pulse_in_front or pulse_rear_i;
pulse_in_front <= pulse_front_i when (level = '0') else
not pulse_front_i;
pulse_in <= pulse_in_front or pulse_rear_i;
fpga_en_o <= fpga_out_en when (switch_i = '0') else '0';
fpga_out_en_o <= fpga_out_en when (switch_i = '0') else '0';
fpga_ttl_en_o <= fpga_out_ttl_en;
fpga_inv_en_o <= fpga_out_inv_en;
fpga_blo_en_o <= fpga_out_blo_en;
led_front_o <= not(led); -- No need of accurate sync, hence we place
led_rear_o <= not(led); -- some combinatorial here.
led_front_o <= led; -- No need of accurate sync, hence we place
led_rear_o <= led; -- some combinatorial here.
pulse_front_o <= pulse_out when level = '0' else
not pulse_out;
pulse_front_o <= pulse_out when level = '0' else
pulse_out_n;
pulse_rear_o <= pulse_out;
-- As we have one Schmitt inverter in the input,
......@@ -153,7 +153,7 @@ begin
inv_o <= inv_i;
gen_trig_cores: for i in 1 to g_number_of_channels generate
trigger: basic_trigger_core
cmp_repeater: basic_trigger_core
generic map
(
g_clk_period => g_clk_period,
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 2710324a
......@@ -237,17 +237,22 @@ begin
when others =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
when c_CTR0_addr =>
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_CTR0);
when c_LT_addr =>
when c_LT_addr =>
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_LT);
when c_DTX_addr =>
when c_DTX_addr =>
wb_slave_dat_o <= s_DTX;
when c_DRXA_addr =>
when c_DRXA_addr =>
wb_slave_dat_o <= DRXA_i;
when c_DRXB_addr =>
when c_DRXB_addr =>
wb_slave_dat_o <= DRXB_i;
when others =>
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
......@@ -260,7 +265,6 @@ begin
-- This is the process that controls the wishbone master interface
-- which bridges the i2c interface with the wishbone interface.
-- wb_clk_i Main clock
p_master_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
......
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