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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
8762bfef
Commit
8762bfef
authored
Sep 06, 2013
by
Theodor-Adrian Stana
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software trigger of iprog command working
parent
b58a52a4
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conv_ttl_blo.bin
hdl/multiboot/syn/conv_ttl_blo.bin
+0
-0
conv_ttl_blo.bit
hdl/multiboot/syn/conv_ttl_blo.bit
+0
-0
conv_ttl_blo.gise
hdl/multiboot/syn/conv_ttl_blo.gise
+14
-14
conv_ttl_blo.vhd
hdl/multiboot/top/conv_ttl_blo.vhd
+1
-1
No files found.
hdl/multiboot/syn/conv_ttl_blo.bin
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8762bfef
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hdl/multiboot/syn/conv_ttl_blo.bit
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hdl/multiboot/syn/conv_ttl_blo.gise
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8762bfef
...
...
@@ -73,35 +73,35 @@
</files>
<transforms
xmlns=
"http://www.xilinx.com/XMLSchema"
>
<transform
xil_pn:end_ts=
"1378
302273"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469104"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302273"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"-1700432985017783241"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469104"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"-1700432985017783241"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302273"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-5050901284947628582"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469104"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-5050901284947628582"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302273"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469104"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302273"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"-2180482239361632071"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469104"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"-2180482239361632071"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302273"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469104"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302273"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"-6206634123545964380"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469104"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"-6206634123545964380"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302293"
xil_pn:in_ck=
"-7576895194167686066"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"8267614965335338665"
xil_pn:start_ts=
"1378302273
"
>
<transform
xil_pn:end_ts=
"1378
469124"
xil_pn:in_ck=
"-7576895194167686066"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"8267614965335338665"
xil_pn:start_ts=
"1378469104
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
...
...
@@ -119,11 +119,11 @@
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
<outfile
xil_pn:name=
"xst"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302293"
xil_pn:in_ck=
"3498961748663175870"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"-3953035127305197084"
xil_pn:start_ts=
"1378302293
"
>
<transform
xil_pn:end_ts=
"1378
469124"
xil_pn:in_ck=
"3498961748663175870"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"-3953035127305197084"
xil_pn:start_ts=
"1378469124
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302303"
xil_pn:in_ck=
"4600148398000832553"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"-7879307074684351365"
xil_pn:start_ts=
"1378302293
"
>
<transform
xil_pn:end_ts=
"1378
469134"
xil_pn:in_ck=
"4600148398000832553"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"-7879307074684351365"
xil_pn:start_ts=
"1378469124
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_ngo"
/>
...
...
@@ -132,7 +132,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo.ngd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_ngdbuild.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302363"
xil_pn:in_ck=
"4600148398000832554"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1378302303
"
>
<transform
xil_pn:end_ts=
"1378
469199"
xil_pn:in_ck=
"4600148398000832554"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1378469134
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
...
...
@@ -145,7 +145,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo_summary.xml"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_usage.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302402"
xil_pn:in_ck=
"-9057307156948659133"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1378302363
"
>
<transform
xil_pn:end_ts=
"1378
469239"
xil_pn:in_ck=
"-9057307156948659133"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1378469199
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
...
...
@@ -159,7 +159,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo_pad.txt"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_par.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302424"
xil_pn:in_ck=
"-336926714118358808"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"6587536580693756888"
xil_pn:start_ts=
"1378302402
"
>
<transform
xil_pn:end_ts=
"1378
469261"
xil_pn:in_ck=
"-336926714118358808"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"6587536580693756888"
xil_pn:start_ts=
"1378469239
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/bitgen.xmsgs"
/>
...
...
@@ -171,7 +171,7 @@
<outfile
xil_pn:name=
"webtalk.log"
/>
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"1378
302402"
xil_pn:in_ck=
"4600148398000832422"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1378302391
"
>
<transform
xil_pn:end_ts=
"1378
469239"
xil_pn:in_ck=
"4600148398000832422"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1378469228
"
>
<status
xil_pn:value=
"FailedRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/trce.xmsgs"
/>
...
...
hdl/multiboot/top/conv_ttl_blo.vhd
View file @
8762bfef
...
...
@@ -130,7 +130,7 @@ architecture behav of conv_ttl_blo is
-- Constant declarations
--============================================================================
-- Firmware version
constant
c_fwvers
:
std_logic_vector
(
15
downto
0
)
:
=
x"020
1
"
;
constant
c_fwvers
:
std_logic_vector
(
15
downto
0
)
:
=
x"020
2
"
;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
...
...
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