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Conv TTL Blocking - Gateware
Commit bfa6c70e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Improved page write time to roughly 12 mins 

This was done by packing three flash data bytes into one register
and combining this with the newly-implemented writemregs command
which gives us the possibility to write 8 regs at once, thus
24 flash bytes at once.
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent a8a7895b
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hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ bfa6c70e
......@@ -64,6 +64,21 @@ entity multiboot_fsm is
reg_bootsts_img_o : out std_logic_vector(15 downto 0);
reg_bootsts_valid_o : out std_logic;
-- Flash access register signals
reg_far_data_i : in std_logic_vector(23 downto 0);
reg_far_data_o : out std_logic_vector(23 downto 0);
reg_far_nbytes_i : in std_logic_vector(1 downto 0);
reg_far_xfer_i : in std_logic;
reg_far_cs_i : in std_logic;
reg_far_ready_o : out std_logic;
-- SPI master signals
spi_xfer_o : out std_logic;
spi_cs_o : out std_logic;
spi_data_i : in std_logic_vector(7 downto 0);
spi_data_o : out std_logic_vector(7 downto 0);
spi_ready_i : in std_logic;
---- Flash read data and ready bit
--reg_flrd_o : out std_logic_vector(31 downto 0);
--reg_flrrdy_o : out std_logic;
......@@ -104,6 +119,8 @@ architecture behav of multiboot_fsm is
-- idle state
IDLE,
-- flash states
SPI_XFER1,
SPI_XFER2,
FLR_CMDADDR,
FLR_DATA,
FLW_DATA,
......@@ -162,11 +179,15 @@ architecture behav of multiboot_fsm is
signal fsm_cmd : std_logic_vector(3 downto 0);
signal fsm_cmd_reg : std_logic_vector(3 downto 0);
signal fl_bcnt : unsigned(1 downto 0);
signal fl_bcnt : unsigned(1 downto 0);
signal fl_sreg : std_logic_vector(31 downto 0);
signal fl_sreg : std_logic_vector(31 downto 0);
signal first : std_logic;
signal first : std_logic;
signal spi_data_int : std_logic_vector(23 downto 0);
signal spi_cnt : unsigned(1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -181,13 +202,18 @@ begin
-- Form state machine command vector from inputs
fsm_cmd <= --reg_flw_i &
--reg_flr_i &
'0' &
reg_far_xfer_i &
reg_iprog_i &
reg_wgb_i &
reg_wmb_i &
reg_rdbootsts_i;
-- Assign SPI outputs
spi_cs_o <= reg_far_cs_i;
spi_data_o <= spi_data_int(7 downto 0);
-- The state machine process
p_fsm : process(clk_i)
variable v_idx : integer := 0;
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
......@@ -198,6 +224,12 @@ begin
icap_wr_n_o <= '1';
reg_bootsts_img_o <= (others => '0');
reg_bootsts_valid_o <= '0';
reg_far_ready_o <= '1';
reg_far_data_o <= (others => '0');
spi_data_int <= (others => '0');
spi_cnt <= "00";
spi_xfer_o <= '0';
--fl_addr_o <= (others => '0');
--fl_serase_o <= '0';
--fl_write_o <= '0';
......@@ -224,7 +256,7 @@ begin
icap_wr_n_o <= '1';
fsm_cmd_reg <= fsm_cmd;
case fsm_cmd is
when "1000" | "0001" =>
when "0010" | "0001" =>
state <= DUMMY_1;
--when "010000" =>
-- state <= FLR_DATA;
......@@ -244,6 +276,12 @@ begin
-- state <= FLW_DATA;
-- fl_write_o <= '1';
-- end if;
when "0100" =>
spi_cnt <= "00";
spi_data_int <= reg_far_data_i;
reg_far_data_o <= (others => '0');
reg_far_ready_o <= '0';
state <= SPI_XFER1;
when others =>
state <= IDLE;
end case;
......@@ -251,6 +289,24 @@ begin
--====================================================================
-- Flash read sequence
--====================================================================
when SPI_XFER1 =>
spi_xfer_o <= '1';
state <= SPI_XFER2;
when SPI_XFER2 =>
spi_xfer_o <= '0';
if (spi_ready_i = '1') then
spi_cnt <= spi_cnt + 1;
spi_data_int <= x"00" & spi_data_int(23 downto 8);
state <= SPI_XFER1;
v_idx := to_integer(unsigned(spi_cnt));
reg_far_data_o((1+v_idx)*8 - 1 downto v_idx*8) <= spi_data_i;
if (spi_cnt = unsigned(reg_far_nbytes_i)) then
reg_far_ready_o <= '1';
state <= IDLE;
end if;
end if;
--when FLR_CMDADDR =>
-- fl_read_o <= '0';
-- if (fl_ready_i = '1') then
......@@ -337,7 +393,7 @@ begin
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
case fsm_cmd_reg is
when "1000" =>
when "0010" =>
state <= GEN_1;
when "0001" =>
state <= BOOTSTS_CMD;
......
hdl/multiboot/rtl/multiboot_regs.vhd
View file @ bfa6c70e
......@@ -54,8 +54,6 @@ entity multiboot_regs is
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_wmb_o : out std_logic;
multiboot_cr_wgb_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
--multiboot_cr_flr_o : out std_logic;
--multiboot_cr_flw_o : out std_logic;
......@@ -71,12 +69,13 @@ entity multiboot_regs is
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
-- Fields of FAR register
multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(7 downto 0);
multiboot_far_data_o : out std_logic_vector(7 downto 0);
--multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(23 downto 0);
multiboot_far_data_o : out std_logic_vector(23 downto 0);
multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_ready_i : in std_logic;
multiboot_far_cs_o : out std_logic
multiboot_far_cs_o : out std_logic;
multiboot_far_ready_i : in std_logic
---- Fields of bitstream address registers
--multiboot_flrdr_i : in std_logic_vector(31 downto 0);
......@@ -87,9 +86,8 @@ end multiboot_regs;
architecture behav of multiboot_regs is
signal multiboot_cr_rdbootsts_int : std_logic;
signal multiboot_cr_wmb_int : std_logic;
signal multiboot_cr_wgb_int : std_logic;
signal multiboot_cr_iprog_int : std_logic;
signal multiboot_cr_iprog_unl_int : std_logic;
signal multiboot_cr_flr_int : std_logic;
signal multiboot_cr_flw_int : std_logic;
signal multiboot_sr_bootsts_img_int : std_logic_vector(15 downto 0);
......@@ -101,9 +99,11 @@ signal multiboot_mbbar_int : std_logic_vector(31 downto 0);
signal multiboot_flrdr_int : std_logic_vector(31 downto 0);
signal multiboot_flwdr_int : std_logic_vector(31 downto 0);
signal multiboot_far_data_load_int : std_logic;
signal multiboot_far_data_int : std_logic_vector(23 downto 0);
signal multiboot_far_nbytes_int : std_logic_vector(1 downto 0);
signal multiboot_far_xfer_int : std_logic;
signal multiboot_far_ready_int : std_logic;
signal multiboot_far_cs_int : std_logic;
signal multiboot_far_ready_int : std_logic;
signal ack_sreg : std_logic_vector(1 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -132,25 +132,23 @@ begin
ack_in_progress <= '0';
rddata_reg <= (others => '0');
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_cr_iprog_unl_int <= '0';
--multiboot_cr_flr_int <= '0';
multiboot_gbbar_int <= (others => '0');
multiboot_mbbar_int <= (others => '0');
multiboot_far_data_load_int <= '0';
multiboot_far_xfer_int <= '0';
multiboot_far_nbytes_int <= "00";
multiboot_far_data_int <= (others => '0');
--multiboot_far_data_load_int <= '0';
multiboot_far_cs_int <= '0';
multiboot_far_xfer_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(0) <= ack_sreg(1);
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_far_data_load_int <= '0';
--multiboot_far_data_load_int <= '0';
multiboot_far_xfer_int <= '0';
--multiboot_cr_flr_int <= '0';
--multiboot_cr_flw_int <= '0';
......@@ -164,16 +162,17 @@ begin
when "000" =>
if (wb_we_i = '1') then
multiboot_cr_rdbootsts_int <= wrdata_reg(0);
multiboot_cr_wmb_int <= wrdata_reg(1);
multiboot_cr_wgb_int <= wrdata_reg(2);
multiboot_cr_iprog_int <= wrdata_reg(3);
multiboot_cr_iprog_unl_int <= wrdata_reg(16);
if (multiboot_cr_iprog_unl_int = '1') then
multiboot_cr_iprog_int <= wrdata_reg(17);
end if;
--multiboot_cr_flr_int <= wrdata_reg(4);
--multiboot_cr_flw_int <= wrdata_reg(5);
end if;
rddata_reg(0) <= multiboot_cr_rdbootsts_int;
rddata_reg(1) <= multiboot_cr_wmb_int;
rddata_reg(2) <= multiboot_cr_wgb_int;
rddata_reg(3) <= multiboot_cr_iprog_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
--rddata_reg(4) <= multiboot_cr_flr_int;
......@@ -188,8 +187,8 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(16) <= multiboot_cr_iprog_unl_int;
rddata_reg(17) <= multiboot_cr_iprog_int;
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
......@@ -244,14 +243,20 @@ begin
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
multiboot_far_data_load_int <= '1';
multiboot_far_xfer_int <= wrdata_reg(8);
multiboot_far_cs_int <= wrdata_reg(10);
--multiboot_far_data_load_int <= '1';
multiboot_far_data_int <= wrdata_reg(23 downto 0);
multiboot_far_nbytes_int <= wrdata_reg(25 downto 24);
multiboot_far_xfer_int <= wrdata_reg(26);
multiboot_far_cs_int <= wrdata_reg(27);
end if;
rddata_reg(7 downto 0) <= multiboot_far_data_i;
rddata_reg(8) <= multiboot_far_xfer_int;
rddata_reg(9) <= multiboot_far_ready_int;
rddata_reg(10) <= multiboot_far_cs_int;
rddata_reg(23 downto 0) <= multiboot_far_data_i;
rddata_reg(25 downto 24) <= multiboot_far_nbytes_int;
rddata_reg(26) <= multiboot_far_xfer_int;
rddata_reg(27) <= multiboot_far_cs_int;
rddata_reg(28) <= multiboot_far_ready_int;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
-- when "101" =>
......@@ -278,10 +283,6 @@ begin
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- Read BOOTSTS register
multiboot_cr_rdbootsts_o <= multiboot_cr_rdbootsts_int;
-- Write MultiBoot Bitstream
multiboot_cr_wmb_o <= multiboot_cr_wmb_int;
-- Write Golden Bitstream
multiboot_cr_wgb_o <= multiboot_cr_wgb_int;
-- IPROG
multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
---- Flash read
......@@ -293,8 +294,9 @@ begin
-- MBBAR
multiboot_mbbar_o <= multiboot_mbbar_int;
-- FAR outputs
multiboot_far_data_o <= wrdata_reg(7 downto 0);
multiboot_far_data_load_o <= multiboot_far_data_load_int;
multiboot_far_data_o <= multiboot_far_data_int; --wrdata_reg(23 downto 0);
multiboot_far_nbytes_o <= multiboot_far_nbytes_int;
--multiboot_far_data_load_o <= multiboot_far_data_load_int;
multiboot_far_xfer_o <= multiboot_far_xfer_int;
multiboot_far_cs_o <= multiboot_far_cs_int;
---- Flash data word
......
hdl/multiboot/rtl/xil_multiboot.vhd
View file @ bfa6c70e
......@@ -96,8 +96,6 @@ architecture behav of xil_multiboot is
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_wmb_o : out std_logic;
multiboot_cr_wgb_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
--multiboot_cr_flr_o : out std_logic;
--multiboot_cr_flw_o : out std_logic;
......@@ -113,12 +111,13 @@ architecture behav of xil_multiboot is
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
-- Fields of FAR register
multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(7 downto 0);
multiboot_far_data_o : out std_logic_vector(7 downto 0);
--multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(23 downto 0);
multiboot_far_data_o : out std_logic_vector(23 downto 0);
multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_ready_i : in std_logic;
multiboot_far_cs_o : out std_logic
multiboot_far_cs_o : out std_logic;
multiboot_far_ready_i : in std_logic
---- Fields of bitstream address registers
--multiboot_flrdr_i : in std_logic_vector(31 downto 0);
......@@ -150,6 +149,20 @@ architecture behav of xil_multiboot is
reg_bootsts_img_o : out std_logic_vector(15 downto 0);
reg_bootsts_valid_o : out std_logic;
-- Flash access register signals
reg_far_data_i : in std_logic_vector(23 downto 0);
reg_far_data_o : out std_logic_vector(23 downto 0);
reg_far_nbytes_i : in std_logic_vector(1 downto 0);
reg_far_xfer_i : in std_logic;
reg_far_cs_i : in std_logic;
reg_far_ready_o : out std_logic;
-- SPI master signals
spi_xfer_o : out std_logic;
spi_cs_o : out std_logic;
spi_data_i : in std_logic_vector(7 downto 0);
spi_data_o : out std_logic_vector(7 downto 0);
spi_ready_i : in std_logic;
---- Flash read data and ready bit
--reg_flrd_o : out std_logic_vector(31 downto 0);
--reg_flrrdy_o : out std_logic;
......@@ -179,54 +192,93 @@ architecture behav of xil_multiboot is
);
end component multiboot_fsm;
-- Flash controller component
component m25p_flash is
port
(
component spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone registers (FAR register access)
far_data_load_i : in std_logic;
far_data_i : in std_logic_vector(7 downto 0);
far_data_o : out std_logic_vector(7 downto 0);
far_xfer_i : in std_logic;
far_ready_o : out std_logic;
far_cs_i : in std_logic;
-- Data readout interface.
-- 1: sets flash read address to addr_i
set_addr_i : in std_logic;
-- start address for read operations
addr_i : in std_logic_vector(23 downto 0);
-- data request: when 1, the controller reads subsequent bytes from
-- the flash, starting from addr_i address.
read_i : in std_logic;
-- read data output
data_o : out std_logic_vector(7 downto 0);
-- when 1, data_o contains a valid byte and the controller is ready to accept
-- another command
ready_o : out std_logic;
-- SPI bus, connect to the flash memory.
-- state of the Chip select line (1 = CS active). External control
-- allows for multi-transfer commands (SPI master itself does not
-- control the state of spi_cs_n_o)
cs_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component m25p_flash;
);
end component spi_master;
-- -- Flash controller component
-- component m25p_flash is
-- port
-- (
-- clk_sys_i : in std_logic;
-- rst_n_i : in std_logic;
--
-- -- Wishbone registers (FAR register access)
-- far_data_load_i : in std_logic;
-- far_data_i : in std_logic_vector(7 downto 0);
-- far_data_o : out std_logic_vector(7 downto 0);
-- far_xfer_i : in std_logic;
-- far_ready_o : out std_logic;
-- far_cs_i : in std_logic;
--
-- -- Data readout interface.
--
-- -- 1: sets flash read address to addr_i
-- set_addr_i : in std_logic;
--
-- -- start address for read operations
-- addr_i : in std_logic_vector(23 downto 0);
--
-- -- data request: when 1, the controller reads subsequent bytes from
-- -- the flash, starting from addr_i address.
-- read_i : in std_logic;
--
-- -- read data output
-- data_o : out std_logic_vector(7 downto 0);
--
-- -- when 1, data_o contains a valid byte and the controller is ready to accept
-- -- another command
-- ready_o : out std_logic;
--
-- -- SPI bus, connect to the flash memory.
-- spi_cs_n_o : out std_logic;
-- spi_sclk_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic
-- );
-- end component m25p_flash;
--============================================================================
-- Signal declarations
--============================================================================
-- Control and status register signals
signal rdbootsts : std_logic;
signal wmb, wgb : std_logic;
signal iprog : std_logic;
signal flr : std_logic;
signal flw : std_logic;
......@@ -239,12 +291,20 @@ architecture behav of xil_multiboot is
signal fsm_icap_dout : std_logic_vector(15 downto 0);
-- Flash controller signals
signal far_data_load : std_logic;
signal far_data_out : std_logic_vector(7 downto 0);
signal far_data_in : std_logic_vector(7 downto 0);
signal fl_far_xfer : std_logic;
signal fl_far_ready : std_logic;
signal fl_far_cs : std_logic;
--signal far_data_load : std_logic;
signal far_data_out : std_logic_vector(23 downto 0);
signal far_data_in : std_logic_vector(23 downto 0);
signal far_nbytes : std_logic_vector(1 downto 0);
signal far_xfer : std_logic;
signal far_cs : std_logic;
signal far_ready : std_logic;
-- SPI master signals
signal spi_data_in : std_logic_vector(7 downto 0);
signal spi_data_out : std_logic_vector(7 downto 0);
signal spi_xfer : std_logic;
signal spi_cs : std_logic;
signal spi_ready : std_logic;
signal fl_addr : std_logic_vector(23 downto 0);
signal fl_rstat : std_logic;
......@@ -297,8 +357,6 @@ begin
wb_stall_o => wbs_o.stall,
multiboot_cr_rdbootsts_o => rdbootsts,
multiboot_cr_wmb_o => wmb,
multiboot_cr_wgb_o => wgb,
multiboot_cr_iprog_o => iprog,
--multiboot_cr_flr_o => flr,
--multiboot_cr_flw_o => flw,
......@@ -311,12 +369,13 @@ begin
multiboot_gbbar_o => gbbar,
multiboot_mbbar_o => mbbar,
multiboot_far_data_load_o => far_data_load,
--multiboot_far_data_load_o => far_data_load,
multiboot_far_data_i => far_data_in,
multiboot_far_data_o => far_data_out,
multiboot_far_xfer_o => fl_far_xfer,
multiboot_far_ready_i => fl_far_ready,
multiboot_far_cs_o => fl_far_cs
multiboot_far_nbytes_o => far_nbytes,
multiboot_far_xfer_o => far_xfer,
multiboot_far_cs_o => far_cs,
multiboot_far_ready_i => far_ready
-- multiboot_flrdr_i => flrd,
-- multiboot_flwdr_o => flwd
......@@ -332,8 +391,8 @@ begin
rst_n_i => rst_n_i,
reg_rdbootsts_i => rdbootsts,
reg_wmb_i => wmb,
reg_wgb_i => wgb,
reg_wmb_i => '0', --wmb,
reg_wgb_i => '0', --wgb,
reg_iprog_i => iprog,
--reg_flr_i => flr,
--reg_flw_i => flw,
......@@ -343,6 +402,19 @@ begin
reg_bootsts_img_o => bootsts_img,
reg_bootsts_valid_o => sr_valid,
reg_far_data_i => far_data_out,
reg_far_data_o => far_data_in,
reg_far_nbytes_i => far_nbytes,
reg_far_xfer_i => far_xfer,
reg_far_cs_i => far_cs,
reg_far_ready_o => far_ready,
spi_xfer_o => spi_xfer,
spi_cs_o => spi_cs,
spi_data_i => spi_data_out,
spi_data_o => spi_data_in,
spi_ready_i => spi_ready,
--fl_addr_o => fl_addr,
--fl_rstat_o => fl_rstat,
......@@ -369,26 +441,26 @@ begin
--============================================================================
-- Flash controller instantiation
--============================================================================
cmp_flash_ctrl : m25p_flash
cmp_spi_master : spi_master
generic map
(
g_div_ratio_log2 => 0,
g_num_data_bits => 8
)
port map
(
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
far_data_load_i => far_data_load,
far_data_i => far_data_out,
far_data_o => far_data_in,
far_xfer_i => fl_far_xfer,
far_ready_o => fl_far_ready,
far_cs_i => fl_far_cs,
set_addr_i => '0',
addr_i => (others => '0'),
read_i => '0',
data_o => open,
ready_o => open,
spi_cs_n_o => spi_cs_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
cs_i => spi_cs,
start_i => spi_xfer,
cpol_i => '0',
data_i => spi_data_in,
data_o => spi_data_out,
ready_o => spi_ready,
spi_cs_n_o => spi_cs_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
);
--============================================================================
......
hdl/multiboot/sim/testbench.vhd
View file @ bfa6c70e
......@@ -161,7 +161,7 @@ architecture behav of testbench is
signal fvcc : real;
signal ready : std_logic;
signal fldat : std_logic_vector(7 downto 0);
signal fldat : std_logic_vector(23 downto 0);
--==============================================================================
-- architecture begin
......@@ -252,7 +252,7 @@ begin
-- dummy xfer
str <= "dummy 1 ";
adr <= x"00000090";
dat <= x"00000100";
dat <= x"04000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -264,13 +264,13 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
ready <= '0';
......@@ -282,7 +282,7 @@ begin
str <= "rd cmd ";
adr <= x"00000090";
dat <= x"0000050b";
dat <= x"0c00000b";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -294,25 +294,25 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
ready <= '0';
---------------------------------------------------------------------
-- address 0
-- address
---------------------------------------------------------------------
wait for c_clk_per;
str <= "addr 0 ";
str <= "address ";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -324,25 +324,114 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
ready <= '0';
-- ---------------------------------------------------------------------
-- -- address 0
-- ---------------------------------------------------------------------
-- wait for c_clk_per;
--
-- str <= "addr 0 ";
-- adr <= x"00000090";
-- dat <= x"00000500";
-- write <= '1';
-- transfer <= '1';
-- wait for c_clk_per;
-- transfer <= '0';
--
-- wait for c_clk_per;
--
-- -- wait for ready
-- while (ready /= '1') loop
-- wait for c_clk_per;
-- adr <= x"00000090";
-- dat <= x"00000400";
-- write <= '0';
-- transfer <= '1';
-- wait for c_clk_per;
-- transfer <= '0';
-- wait until wb_ack = '1';
-- ready <= wb_dat_in(28);
-- end loop;
--
-- ready <= '0';
--
-- ---------------------------------------------------------------------
-- -- address 1
-- ---------------------------------------------------------------------
-- wait for c_clk_per;
--
-- str <= "addr 1 ";
-- adr <= x"00000090";
-- dat <= x"00000500";
-- write <= '1';
-- transfer <= '1';
-- wait for c_clk_per;
-- transfer <= '0';
--
-- wait for c_clk_per;
--
-- -- wait for ready
-- while (ready /= '1') loop
-- wait for c_clk_per;
-- adr <= x"00000090";
-- dat <= x"00000400";
-- write <= '0';
-- transfer <= '1';
-- wait for c_clk_per;
-- transfer <= '0';
-- wait until wb_ack = '1';
-- ready <= wb_dat_in(28);
-- end loop;
--
-- ready <= '0';
--
-- ---------------------------------------------------------------------
-- -- address 2
-- ---------------------------------------------------------------------
-- wait for c_clk_per;
--
-- str <= "addr 2 ";
-- adr <= x"00000090";
-- dat <= x"00000510";
-- write <= '1';
-- transfer <= '1';
-- wait for c_clk_per;
-- transfer <= '0';
--
-- wait for c_clk_per;
--
-- -- wait for ready
-- while (ready /= '1') loop
-- wait for c_clk_per;
-- adr <= x"00000090";
-- dat <= x"00000400";
-- write <= '0';
-- transfer <= '1';
-- wait for c_clk_per;
-- transfer <= '0';
-- wait until wb_ack = '1';
-- ready <= wb_dat_in(28);
-- end loop;
--
-- ready <= '0';
---------------------------------------------------------------------
-- address 1
-- read dummy
---------------------------------------------------------------------
wait for c_clk_per;
str <= "addr 1 ";
str <= "rd dummy";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0c000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -354,25 +443,25 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
ready <= '0';
---------------------------------------------------------------------
-- address 2
-- read 1
---------------------------------------------------------------------
wait for c_clk_per;
str <= "addr 2 ";
str <= "rd 1 ";
adr <= x"00000090";
dat <= x"00000510";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -390,19 +479,21 @@ begin
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
---------------------------------------------------------------------
-- read dummy
-- read 2
---------------------------------------------------------------------
wait for c_clk_per;
str <= "rd dummy";
str <= "rd 2 ";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -414,25 +505,27 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
---------------------------------------------------------------------
-- read 1
-- read 3
---------------------------------------------------------------------
wait for c_clk_per;
str <= "rd 1 ";
str <= "rd 3 ";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -444,27 +537,27 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(7 downto 0);
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
---------------------------------------------------------------------
-- read 2
-- read 4
---------------------------------------------------------------------
wait for c_clk_per;
str <= "rd 2 ";
str <= "rd 4 ";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -476,27 +569,27 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(7 downto 0);
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
---------------------------------------------------------------------
-- read 3
-- read 5
---------------------------------------------------------------------
wait for c_clk_per;
str <= "rd 3 ";
str <= "rd 5 ";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -508,27 +601,27 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(7 downto 0);
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
---------------------------------------------------------------------
-- read 4
-- read 6
---------------------------------------------------------------------
wait for c_clk_per;
str <= "rd 4 ";
str <= "rd 6 ";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -540,27 +633,27 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(7 downto 0);
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
---------------------------------------------------------------------
-- read 5
-- read 7
---------------------------------------------------------------------
wait for c_clk_per;
str <= "rd 5 ";
str <= "rd 7 ";
adr <= x"00000090";
dat <= x"00000500";
dat <= x"0e000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -572,16 +665,48 @@ begin
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000400";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
---------------------------------------------------------------------
-- read last
---------------------------------------------------------------------
wait for c_clk_per;
str <= "rd last ";
adr <= x"00000090";
dat <= x"0c000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait for c_clk_per;
-- wait for ready
while (ready /= '1') loop
wait for c_clk_per;
adr <= x"00000090";
dat <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(7 downto 0);
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
......@@ -592,7 +717,7 @@ begin
str <= "rd end ";
adr <= x"00000090";
dat <= x"00000100";
dat <= x"04000000";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -610,10 +735,10 @@ begin
wait for c_clk_per;
transfer <= '0';
wait until wb_ack = '1';
ready <= wb_dat_in(9);
ready <= wb_dat_in(28);
end loop;
fldat <= wb_dat_in(7 downto 0);
fldat <= wb_dat_in(23 downto 0);
ready <= '0';
......
hdl/multiboot/sim/transcript
View file @ bfa6c70e
# // ModelSim SE 10.1 Dec 5 2011 Linux 3.2.0-52-generic-pae
# // ModelSim SE 10.1 Dec 5 2011 Linux 3.2.0-54-generic-pae
# //
# // Copyright 1991-2011 Mentor Graphics Corporation
# // All Rights Reserved.
......@@ -110,13 +110,522 @@ do run.do
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# ** Error: testbench.vhd(260): near ":": syntax error
# ** Error: testbench.vhd(328): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 16
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "testbench.vhd""
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/read_i'.
# Executing ONERROR command at macro ./wave.do line 29
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/ready_o'.
# Executing ONERROR command at macro ./wave.do line 30
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/data_o'.
# Executing ONERROR command at macro ./wave.do line 31
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/spi_cs_n_o'.
# Executing ONERROR command at macro ./wave.do line 32
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/spi_sclk_o'.
# Executing ONERROR command at macro ./wave.do line 33
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/spi_mosi_o'.
# Executing ONERROR command at macro ./wave.do line 34
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/spi_miso_i'.
# Executing ONERROR command at macro ./wave.do line 35
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Error: False instruction, please retry
# Time: 50528 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
# ** Error: False instruction, please retry
# Time: 54208 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
add wave \
sim:/testbench/fldat
restart; run 300 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Error: False instruction, please retry
# Time: 50528 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
# ** Error: False instruction, please retry
# Time: 54208 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
add wave \
sim:/testbench/UUT/cmp_fsm/spi_xfer_o \
sim:/testbench/UUT/cmp_fsm/spi_cs_o \
sim:/testbench/UUT/cmp_fsm/spi_data_i \
sim:/testbench/UUT/cmp_fsm/spi_data_o \
sim:/testbench/UUT/cmp_fsm/spi_ready_i \
sim:/testbench/UUT/cmp_fsm/spi_data_int \
sim:/testbench/UUT/cmp_fsm/spi_cnt
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
restart; run 300 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Error: False instruction, please retry
# Time: 50528 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
# ** Error: False instruction, please retry
# Time: 54208 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
add wave \
sim:/testbench/UUT/cmp_fsm/reg_far_data_i \
sim:/testbench/UUT/cmp_fsm/reg_far_data_o \
sim:/testbench/UUT/cmp_fsm/reg_far_nbytes_i \
sim:/testbench/UUT/cmp_fsm/reg_far_xfer_i \
sim:/testbench/UUT/cmp_fsm/reg_far_cs_i \
sim:/testbench/UUT/cmp_fsm/reg_far_ready_o
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
restart; run 300 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Error: False instruction, please retry
# Time: 50528 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
# ** Error: False instruction, please retry
# Time: 54208 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
add wave \
sim:/testbench/UUT/spi_cs_n_o \
sim:/testbench/UUT/spi_sclk_o \
sim:/testbench/UUT/spi_mosi_o \
sim:/testbench/UUT/spi_miso_i
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
restart; run 300 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Error: False instruction, please retry
# Time: 50528 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
# ** Error: False instruction, please retry
# Time: 54208 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
add wave \
sim:/testbench/UUT/cmp_spi_master/data_i \
sim:/testbench/UUT/cmp_spi_master/data_o
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# ** Warning: ../rtl/m25p_flash.vhd(140): (vcom-1445) Duplicate signal "spi_wdata" found in sensitivity list.
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Error: False instruction, please retry
# Time: 50528 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
# ** Error: False instruction, please retry
# Time: 56592 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# ** Warning: ../rtl/m25p_flash.vhd(140): (vcom-1445) Duplicate signal "spi_wdata" found in sensitivity list.
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Warning: Instruction canceled because the chip is deselected
# Time: 53072 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
# ** Error: False instruction, please retry
# Time: 54224 ns Iteration: 6 Instance: /testbench/cmp_mem/SPI_decoder
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -232,7 +741,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -250,79 +758,11 @@ do run.do
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_fsm/fl_addr_o'.
# Executing ONERROR command at macro ./wave.do line 10
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_fsm/fl_read_o'.
# Executing ONERROR command at macro ./wave.do line 11
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_fsm/fl_endcmd_o'.
# Executing ONERROR command at macro ./wave.do line 12
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/rstat_i'.
# Executing ONERROR command at macro ./wave.do line 16
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/serase_i'.
# Executing ONERROR command at macro ./wave.do line 17
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/write_i'.
# Executing ONERROR command at macro ./wave.do line 18
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/endcmd_i'.
# Executing ONERROR command at macro ./wave.do line 20
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/data_i'.
# Executing ONERROR command at macro ./wave.do line 22
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_fsm/reg_flr_i'.
# Executing ONERROR command at macro ./wave.do line 31
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_fsm/reg_flw_i'.
# Executing ONERROR command at macro ./wave.do line 32
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_fsm/reg_flwd_i'.
# Executing ONERROR command at macro ./wave.do line 33
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_fsm/reg_flwrdy_o'.
# Executing ONERROR command at macro ./wave.do line 34
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave sim:/testbench/p_stim/*
restart; run 20 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/transfer \
sim:/testbench/write
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
dor
# invalid command name "dor"
di run
# ambiguous command name "di": directory_image disable disablebp disablebp_image divTime
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -427,6 +867,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -438,7 +879,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -461,45 +901,6 @@ do run.do
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/UUT/cmp_regs/multiboot_far_data_load_int \
sim:/testbench/UUT/cmp_regs/multiboot_far_xfer_int \
sim:/testbench/UUT/cmp_regs/multiboot_far_ready_int \
sim:/testbench/UUT/cmp_regs/multiboot_far_cs_int
restart; run 200 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -604,6 +1005,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -615,7 +1017,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -633,98 +1034,114 @@ do run.do
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Error: (vish-4014) No objects found matching '/testbench/p_stim/ready'.
# Executing ONERROR command at macro ./wave.do line 14
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/ready
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
run
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/wb_adr \
sim:/testbench/wb_dat_in \
sim:/testbench/wb_dat_out \
sim:/testbench/wb_cyc \
sim:/testbench/wb_stb \
sim:/testbench/wb_we
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
restart; run 100 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/wb_ack
add wave \
sim:/testbench/wb_stall
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
restart; run 100 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# ** Warning: ../rtl/m25p_flash.vhd(140): (vcom-1445) Duplicate signal "spi_wdata" found in sensitivity list.
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
......@@ -737,12 +1154,13 @@ restart; run 100 us
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
......@@ -758,8 +1176,6 @@ restart; run 100 us
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
z`do run.do
# invalid command name "z`do"
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -843,104 +1259,148 @@ do run.do
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# ** Error: ../rtl/multiboot_fsm.vhd(298): (vcom-1136) Unknown identifier "reg_far_bytes_i".
# ** Error: ../rtl/multiboot_fsm.vhd(298): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Error: ../rtl/multiboot_fsm.vhd(300): (vcom-1136) Unknown identifier "reg_far_bytes_i".
# ** Error: ../rtl/multiboot_fsm.vhd(300): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Error: ../rtl/multiboot_fsm.vhd(302): (vcom-1136) Unknown identifier "reg_far_bytes_i".
# ** Error: ../rtl/multiboot_fsm.vhd(302): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Error: ../rtl/multiboot_fsm.vhd(303): near "spi_data_int": expecting THEN
# ** Error: ../rtl/multiboot_fsm.vhd(310): near "if": expecting CASE
# ** Error: ../rtl/multiboot_fsm.vhd(375): near "when": expecting END
# ** Error: ../rtl/multiboot_fsm.vhd(381): near "when": expecting END
# ** Error: ../rtl/multiboot_fsm.vhd(387): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(393): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(410): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(416): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(422): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(428): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(434): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(440): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(446): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(452): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(458): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(464): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(474): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(480): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(486): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(492): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(498): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(504): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(509): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(514): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(519): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(528): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(533): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(538): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(545): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(551): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(560): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(566): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(575): near "when": syntax error
# ** Error: ../rtl/multiboot_fsm.vhd(583): near "when": syntax error
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 14
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "../rtl/multiboot_fsm.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
add wave \
sim:/testbench/UUT/cmp_regs/multiboot_far_data_load_int \
sim:/testbench/UUT/cmp_regs/multiboot_far_xfer_int \
sim:/testbench/UUT/cmp_regs/multiboot_far_ready_int \
sim:/testbench/UUT/cmp_regs/multiboot_far_cs_int
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
restart; run 100 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# ** Warning: ../rtl/m25p_flash.vhd(140): (vcom-1445) Duplicate signal "spi_wdata" found in sensitivity list.
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# ** Error: ../rtl/multiboot_fsm.vhd(298): (vcom-1136) Unknown identifier "reg_far_bytes_i".
# ** Error: ../rtl/multiboot_fsm.vhd(298): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Error: ../rtl/multiboot_fsm.vhd(300): (vcom-1136) Unknown identifier "reg_far_bytes_i".
# ** Error: ../rtl/multiboot_fsm.vhd(300): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Error: ../rtl/multiboot_fsm.vhd(302): (vcom-1136) Unknown identifier "reg_far_bytes_i".
# ** Error: ../rtl/multiboot_fsm.vhd(302): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Warning: [14] ../rtl/multiboot_fsm.vhd(299): (vcom-1272) Length of expected is 24; length of actual is 8.
# ** Warning: [14] ../rtl/multiboot_fsm.vhd(301): (vcom-1272) Length of expected is 24; length of actual is 16.
# ** Error: ../rtl/multiboot_fsm.vhd(591): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 14
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "../rtl/multiboot_fsm.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -1024,6 +1484,8 @@ do run.do
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# ** Warning: [14] ../rtl/multiboot_fsm.vhd(299): (vcom-1272) Length of expected is 24; length of actual is 8.
# ** Warning: [14] ../rtl/multiboot_fsm.vhd(301): (vcom-1272) Length of expected is 24; length of actual is 16.
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
......@@ -1045,6 +1507,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -1056,7 +1519,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -1079,6 +1541,13 @@ do run.do
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Fatal: (vsim-3420) Array lengths do not match. Left is 24 (23 downto 0). Right is 8 (7 downto 0).
# Time: 50600 ns Iteration: 1 Process: /testbench/UUT/cmp_fsm/p_fsm File: ../rtl/multiboot_fsm.vhd
# Fatal error in Process p_fsm at ../rtl/multiboot_fsm.vhd line 299
#
# HDL call sequence:
# Stopped at ../rtl/multiboot_fsm.vhd 299 Process p_fsm
#
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -1162,61 +1631,13 @@ do run.do
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Error: ../rtl/multiboot_fsm.vhd(299): near "<=": expecting => or '|' or '!'
# ** Error: ../rtl/multiboot_fsm.vhd(586): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 14
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "../rtl/multiboot_fsm.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -1321,6 +1742,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -1332,7 +1754,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -1355,6 +1776,13 @@ do run.do
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Fatal: (vsim-3420) Array lengths do not match. Left is 0 (-1 downto 0 (null array)). Right is 8 (7 downto 0).
# Time: 50600 ns Iteration: 1 Process: /testbench/UUT/cmp_fsm/p_fsm File: ../rtl/multiboot_fsm.vhd
# Fatal error in Process p_fsm at ../rtl/multiboot_fsm.vhd line 299
#
# HDL call sequence:
# Stopped at ../rtl/multiboot_fsm.vhd 299 Process p_fsm
#
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -1459,6 +1887,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -1470,7 +1899,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -1491,14 +1919,8 @@ do run.do
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Error: Vcc must be greater than VCCmin during at least tVSL before chip is selected
# Time: 832 ns Iteration: 5 Instance: /testbench/cmp_mem/ACDC_watch
# ** Error: Vcc must be greater than VCCmin during at least tVSL before chip is selected
# Time: 832 ns Iteration: 5 Instance: /testbench/cmp_mem/ACDC_watch
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/fldat
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -1603,6 +2025,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -1614,7 +2037,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -1635,12 +2057,44 @@ do run.do
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Error: Vcc must be greater than VCCmin during at least tVSL before chip is selected
# Time: 832 ns Iteration: 5 Instance: /testbench/cmp_mem/ACDC_watch
# ** Error: Vcc must be greater than VCCmin during at least tVSL before chip is selected
# Time: 832 ns Iteration: 5 Instance: /testbench/cmp_mem/ACDC_watch
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/UUT/cmp_regs/multiboot_far_data_int
restart; run 300 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -1745,6 +2199,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -1756,7 +2211,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......@@ -1883,6 +2337,7 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -1894,7 +2349,6 @@ do run.do
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
......
hdl/multiboot/sim/wave.do
View file @ bfa6c70e
......@@ -6,7 +6,7 @@ add wave -noupdate /testbench/transfer
add wave -noupdate /testbench/write
add wave -noupdate /testbench/str
add wave -noupdate -radix hexadecimal /testbench/wb_adr
add wave -noupdate -radix hexadecimal -childformat {{/testbench/wb_dat_in(31) -radix hexadecimal} {/testbench/wb_dat_in(30) -radix hexadecimal} {/testbench/wb_dat_in(29) -radix hexadecimal} {/testbench/wb_dat_in(28) -radix hexadecimal} {/testbench/wb_dat_in(27) -radix hexadecimal} {/testbench/wb_dat_in(26) -radix hexadecimal} {/testbench/wb_dat_in(25) -radix hexadecimal} {/testbench/wb_dat_in(24) -radix hexadecimal} {/testbench/wb_dat_in(23) -radix hexadecimal} {/testbench/wb_dat_in(22) -radix hexadecimal} {/testbench/wb_dat_in(21) -radix hexadecimal} {/testbench/wb_dat_in(20) -radix hexadecimal} {/testbench/wb_dat_in(19) -radix hexadecimal} {/testbench/wb_dat_in(18) -radix hexadecimal} {/testbench/wb_dat_in(17) -radix hexadecimal} {/testbench/wb_dat_in(16) -radix hexadecimal} {/testbench/wb_dat_in(15) -radix hexadecimal} {/testbench/wb_dat_in(14) -radix hexadecimal} {/testbench/wb_dat_in(13) -radix hexadecimal} {/testbench/wb_dat_in(12) -radix hexadecimal} {/testbench/wb_dat_in(11) -radix hexadecimal} {/testbench/wb_dat_in(10) -radix hexadecimal} {/testbench/wb_dat_in(9) -radix hexadecimal} {/testbench/wb_dat_in(8) -radix hexadecimal} {/testbench/wb_dat_in(7) -radix hexadecimal} {/testbench/wb_dat_in(6) -radix hexadecimal} {/testbench/wb_dat_in(5) -radix hexadecimal} {/testbench/wb_dat_in(4) -radix hexadecimal} {/testbench/wb_dat_in(3) -radix hexadecimal} {/testbench/wb_dat_in(2) -radix hexadecimal} {/testbench/wb_dat_in(1) -radix hexadecimal} {/testbench/wb_dat_in(0) -radix hexadecimal}} -subitemconfig {/testbench/wb_dat_in(31) {-radix hexadecimal} /testbench/wb_dat_in(30) {-radix hexadecimal} /testbench/wb_dat_in(29) {-radix hexadecimal} /testbench/wb_dat_in(28) {-radix hexadecimal} /testbench/wb_dat_in(27) {-radix hexadecimal} /testbench/wb_dat_in(26) {-radix hexadecimal} /testbench/wb_dat_in(25) {-radix hexadecimal} /testbench/wb_dat_in(24) {-radix hexadecimal} /testbench/wb_dat_in(23) {-radix hexadecimal} /testbench/wb_dat_in(22) {-radix hexadecimal} /testbench/wb_dat_in(21) {-radix hexadecimal} /testbench/wb_dat_in(20) {-radix hexadecimal} /testbench/wb_dat_in(19) {-radix hexadecimal} /testbench/wb_dat_in(18) {-radix hexadecimal} /testbench/wb_dat_in(17) {-radix hexadecimal} /testbench/wb_dat_in(16) {-radix hexadecimal} /testbench/wb_dat_in(15) {-radix hexadecimal} /testbench/wb_dat_in(14) {-radix hexadecimal} /testbench/wb_dat_in(13) {-radix hexadecimal} /testbench/wb_dat_in(12) {-radix hexadecimal} /testbench/wb_dat_in(11) {-radix hexadecimal} /testbench/wb_dat_in(10) {-radix hexadecimal} /testbench/wb_dat_in(9) {-radix hexadecimal} /testbench/wb_dat_in(8) {-radix hexadecimal} /testbench/wb_dat_in(7) {-radix hexadecimal} /testbench/wb_dat_in(6) {-radix hexadecimal} /testbench/wb_dat_in(5) {-radix hexadecimal} /testbench/wb_dat_in(4) {-radix hexadecimal} /testbench/wb_dat_in(3) {-radix hexadecimal} /testbench/wb_dat_in(2) {-radix hexadecimal} /testbench/wb_dat_in(1) {-radix hexadecimal} /testbench/wb_dat_in(0) {-radix hexadecimal}} /testbench/wb_dat_in
add wave -noupdate -radix hexadecimal -childformat {{/testbench/wb_dat_in(31) -radix hexadecimal} {/testbench/wb_dat_in(30) -radix hexadecimal} {/testbench/wb_dat_in(29) -radix hexadecimal} {/testbench/wb_dat_in(28) -radix hexadecimal} {/testbench/wb_dat_in(27) -radix hexadecimal} {/testbench/wb_dat_in(26) -radix hexadecimal} {/testbench/wb_dat_in(25) -radix hexadecimal} {/testbench/wb_dat_in(24) -radix hexadecimal} {/testbench/wb_dat_in(23) -radix hexadecimal} {/testbench/wb_dat_in(22) -radix hexadecimal} {/testbench/wb_dat_in(21) -radix hexadecimal} {/testbench/wb_dat_in(20) -radix hexadecimal} {/testbench/wb_dat_in(19) -radix hexadecimal} {/testbench/wb_dat_in(18) -radix hexadecimal} {/testbench/wb_dat_in(17) -radix hexadecimal} {/testbench/wb_dat_in(16) -radix hexadecimal} {/testbench/wb_dat_in(15) -radix hexadecimal} {/testbench/wb_dat_in(14) -radix hexadecimal} {/testbench/wb_dat_in(13) -radix hexadecimal} {/testbench/wb_dat_in(12) -radix hexadecimal} {/testbench/wb_dat_in(11) -radix hexadecimal} {/testbench/wb_dat_in(10) -radix hexadecimal} {/testbench/wb_dat_in(9) -radix hexadecimal} {/testbench/wb_dat_in(8) -radix hexadecimal} {/testbench/wb_dat_in(7) -radix hexadecimal} {/testbench/wb_dat_in(6) -radix hexadecimal} {/testbench/wb_dat_in(5) -radix hexadecimal} {/testbench/wb_dat_in(4) -radix hexadecimal} {/testbench/wb_dat_in(3) -radix hexadecimal} {/testbench/wb_dat_in(2) -radix hexadecimal} {/testbench/wb_dat_in(1) -radix hexadecimal} {/testbench/wb_dat_in(0) -radix hexadecimal}} -subitemconfig {/testbench/wb_dat_in(31) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(30) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(29) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(28) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(27) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(26) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(25) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(24) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(23) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(22) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(21) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(20) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(19) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(18) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(17) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(16) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(15) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(14) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(13) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(12) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(11) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(10) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(9) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(8) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(7) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(6) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(5) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(4) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(3) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(2) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(1) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(0) {-height 16 -radix hexadecimal}} /testbench/wb_dat_in
add wave -noupdate -radix hexadecimal /testbench/wb_dat_out
add wave -noupdate /testbench/wb_cyc
add wave -noupdate /testbench/wb_stb
......@@ -14,6 +14,7 @@ add wave -noupdate /testbench/wb_we
add wave -noupdate /testbench/wb_ack
add wave -noupdate /testbench/wb_stall
add wave -noupdate /testbench/ready
add wave -noupdate -radix hexadecimal /testbench/fldat
add wave -noupdate -divider regs
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_data_load_int
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_xfer_int
......@@ -23,18 +24,30 @@ add wave -noupdate -divider FSM
add wave -noupdate /testbench/UUT/cmp_fsm/state
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd_reg
add wave -noupdate /testbench/UUT/cmp_fsm/fl_bcnt
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/fl_sreg
add wave -noupdate -divider {flash ctrl}
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/read_i
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_o
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_flash_ctrl/data_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_cs_n_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_sclk_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_mosi_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_miso_i
add wave -noupdate -divider fsm-spi
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_far_data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_far_data_o
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_nbytes_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_xfer_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_cs_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_ready_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_xfer_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_cs_o
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_ready_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_int
add wave -noupdate /testbench/UUT/cmp_fsm/spi_cnt
add wave -noupdate -divider {spi pins}
add wave -noupdate /testbench/UUT/spi_cs_n_o
add wave -noupdate /testbench/UUT/spi_sclk_o
add wave -noupdate /testbench/UUT/spi_mosi_o
add wave -noupdate /testbench/UUT/spi_miso_i
add wave -noupdate -divider spi
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_spi_master/data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_spi_master/data_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {792 ns} 0}
WaveRestoreCursors {{Cursor 1} {63727 ns} 0}
configure wave -namecolwidth 335
configure wave -valuecolwidth 99
configure wave -justifyvalue left
......@@ -49,4 +62,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {3196 ns}
WaveRestoreZoom {61939 ns} {66867 ns}
hdl/multiboot/syn/conv_ttl_blo.gise
View file @ bfa6c70e
......@@ -53,7 +53,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
......@@ -64,7 +63,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
......@@ -75,35 +73,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1380021433" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021433" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021433" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021454" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745675" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -121,11 +119,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1380021454" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1380021454">
<transform xil_pn:end_ts="1381745675" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1381745675">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021465" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1380021454">
<transform xil_pn:end_ts="1381745686" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1381745675">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,7 +132,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1380021551" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1380021465">
<transform xil_pn:end_ts="1381745744" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1381745686">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -147,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1380021604" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1380021551">
<transform xil_pn:end_ts="1381745799" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1381745744">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -161,7 +159,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1380021640" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1380021604">
<transform xil_pn:end_ts="1381745835" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1381745799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -173,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1380021604" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1380021593">
<transform xil_pn:end_ts="1381745799" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381745788">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
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