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Conv TTL Blocking - Gateware
Commit bfa6c70e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Improved page write time to roughly 12 mins 

This was done by packing three flash data bytes into one register
and combining this with the newly-implemented writemregs command
which gives us the possibility to write 8 regs at once, thus
24 flash bytes at once.
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent a8a7895b
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Showing with 1294 additions and 574 deletions
hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ bfa6c70e
......@@ -64,6 +64,21 @@ entity multiboot_fsm is
reg_bootsts_img_o : out std_logic_vector(15 downto 0);
reg_bootsts_valid_o : out std_logic;
-- Flash access register signals
reg_far_data_i : in std_logic_vector(23 downto 0);
reg_far_data_o : out std_logic_vector(23 downto 0);
reg_far_nbytes_i : in std_logic_vector(1 downto 0);
reg_far_xfer_i : in std_logic;
reg_far_cs_i : in std_logic;
reg_far_ready_o : out std_logic;
-- SPI master signals
spi_xfer_o : out std_logic;
spi_cs_o : out std_logic;
spi_data_i : in std_logic_vector(7 downto 0);
spi_data_o : out std_logic_vector(7 downto 0);
spi_ready_i : in std_logic;
---- Flash read data and ready bit
--reg_flrd_o : out std_logic_vector(31 downto 0);
--reg_flrrdy_o : out std_logic;
......@@ -104,6 +119,8 @@ architecture behav of multiboot_fsm is
-- idle state
IDLE,
-- flash states
SPI_XFER1,
SPI_XFER2,
FLR_CMDADDR,
FLR_DATA,
FLW_DATA,
......@@ -162,11 +179,15 @@ architecture behav of multiboot_fsm is
signal fsm_cmd : std_logic_vector(3 downto 0);
signal fsm_cmd_reg : std_logic_vector(3 downto 0);
signal fl_bcnt : unsigned(1 downto 0);
signal fl_bcnt : unsigned(1 downto 0);
signal fl_sreg : std_logic_vector(31 downto 0);
signal fl_sreg : std_logic_vector(31 downto 0);
signal first : std_logic;
signal first : std_logic;
signal spi_data_int : std_logic_vector(23 downto 0);
signal spi_cnt : unsigned(1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -181,13 +202,18 @@ begin
-- Form state machine command vector from inputs
fsm_cmd <= --reg_flw_i &
--reg_flr_i &
'0' &
reg_far_xfer_i &
reg_iprog_i &
reg_wgb_i &
reg_wmb_i &
reg_rdbootsts_i;
-- Assign SPI outputs
spi_cs_o <= reg_far_cs_i;
spi_data_o <= spi_data_int(7 downto 0);
-- The state machine process
p_fsm : process(clk_i)
variable v_idx : integer := 0;
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
......@@ -198,6 +224,12 @@ begin
icap_wr_n_o <= '1';
reg_bootsts_img_o <= (others => '0');
reg_bootsts_valid_o <= '0';
reg_far_ready_o <= '1';
reg_far_data_o <= (others => '0');
spi_data_int <= (others => '0');
spi_cnt <= "00";
spi_xfer_o <= '0';
--fl_addr_o <= (others => '0');
--fl_serase_o <= '0';
--fl_write_o <= '0';
......@@ -224,7 +256,7 @@ begin
icap_wr_n_o <= '1';
fsm_cmd_reg <= fsm_cmd;
case fsm_cmd is
when "1000" | "0001" =>
when "0010" | "0001" =>
state <= DUMMY_1;
--when "010000" =>
-- state <= FLR_DATA;
......@@ -244,6 +276,12 @@ begin
-- state <= FLW_DATA;
-- fl_write_o <= '1';
-- end if;
when "0100" =>
spi_cnt <= "00";
spi_data_int <= reg_far_data_i;
reg_far_data_o <= (others => '0');
reg_far_ready_o <= '0';
state <= SPI_XFER1;
when others =>
state <= IDLE;
end case;
......@@ -251,6 +289,24 @@ begin
--====================================================================
-- Flash read sequence
--====================================================================
when SPI_XFER1 =>
spi_xfer_o <= '1';
state <= SPI_XFER2;
when SPI_XFER2 =>
spi_xfer_o <= '0';
if (spi_ready_i = '1') then
spi_cnt <= spi_cnt + 1;
spi_data_int <= x"00" & spi_data_int(23 downto 8);
state <= SPI_XFER1;
v_idx := to_integer(unsigned(spi_cnt));
reg_far_data_o((1+v_idx)*8 - 1 downto v_idx*8) <= spi_data_i;
if (spi_cnt = unsigned(reg_far_nbytes_i)) then
reg_far_ready_o <= '1';
state <= IDLE;
end if;
end if;
--when FLR_CMDADDR =>
-- fl_read_o <= '0';
-- if (fl_ready_i = '1') then
......@@ -337,7 +393,7 @@ begin
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
case fsm_cmd_reg is
when "1000" =>
when "0010" =>
state <= GEN_1;
when "0001" =>
state <= BOOTSTS_CMD;
......
hdl/multiboot/rtl/multiboot_regs.vhd
View file @ bfa6c70e
......@@ -54,8 +54,6 @@ entity multiboot_regs is
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_wmb_o : out std_logic;
multiboot_cr_wgb_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
--multiboot_cr_flr_o : out std_logic;
--multiboot_cr_flw_o : out std_logic;
......@@ -71,12 +69,13 @@ entity multiboot_regs is
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
-- Fields of FAR register
multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(7 downto 0);
multiboot_far_data_o : out std_logic_vector(7 downto 0);
--multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(23 downto 0);
multiboot_far_data_o : out std_logic_vector(23 downto 0);
multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_ready_i : in std_logic;
multiboot_far_cs_o : out std_logic
multiboot_far_cs_o : out std_logic;
multiboot_far_ready_i : in std_logic
---- Fields of bitstream address registers
--multiboot_flrdr_i : in std_logic_vector(31 downto 0);
......@@ -87,9 +86,8 @@ end multiboot_regs;
architecture behav of multiboot_regs is
signal multiboot_cr_rdbootsts_int : std_logic;
signal multiboot_cr_wmb_int : std_logic;
signal multiboot_cr_wgb_int : std_logic;
signal multiboot_cr_iprog_int : std_logic;
signal multiboot_cr_iprog_unl_int : std_logic;
signal multiboot_cr_flr_int : std_logic;
signal multiboot_cr_flw_int : std_logic;
signal multiboot_sr_bootsts_img_int : std_logic_vector(15 downto 0);
......@@ -101,9 +99,11 @@ signal multiboot_mbbar_int : std_logic_vector(31 downto 0);
signal multiboot_flrdr_int : std_logic_vector(31 downto 0);
signal multiboot_flwdr_int : std_logic_vector(31 downto 0);
signal multiboot_far_data_load_int : std_logic;
signal multiboot_far_data_int : std_logic_vector(23 downto 0);
signal multiboot_far_nbytes_int : std_logic_vector(1 downto 0);
signal multiboot_far_xfer_int : std_logic;
signal multiboot_far_ready_int : std_logic;
signal multiboot_far_cs_int : std_logic;
signal multiboot_far_ready_int : std_logic;
signal ack_sreg : std_logic_vector(1 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -132,25 +132,23 @@ begin
ack_in_progress <= '0';
rddata_reg <= (others => '0');
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_cr_iprog_unl_int <= '0';
--multiboot_cr_flr_int <= '0';
multiboot_gbbar_int <= (others => '0');
multiboot_mbbar_int <= (others => '0');
multiboot_far_data_load_int <= '0';
multiboot_far_xfer_int <= '0';
multiboot_far_nbytes_int <= "00";
multiboot_far_data_int <= (others => '0');
--multiboot_far_data_load_int <= '0';
multiboot_far_cs_int <= '0';
multiboot_far_xfer_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(0) <= ack_sreg(1);
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_far_data_load_int <= '0';
--multiboot_far_data_load_int <= '0';
multiboot_far_xfer_int <= '0';
--multiboot_cr_flr_int <= '0';
--multiboot_cr_flw_int <= '0';
......@@ -164,16 +162,17 @@ begin
when "000" =>
if (wb_we_i = '1') then
multiboot_cr_rdbootsts_int <= wrdata_reg(0);
multiboot_cr_wmb_int <= wrdata_reg(1);
multiboot_cr_wgb_int <= wrdata_reg(2);
multiboot_cr_iprog_int <= wrdata_reg(3);
multiboot_cr_iprog_unl_int <= wrdata_reg(16);
if (multiboot_cr_iprog_unl_int = '1') then
multiboot_cr_iprog_int <= wrdata_reg(17);
end if;
--multiboot_cr_flr_int <= wrdata_reg(4);
--multiboot_cr_flw_int <= wrdata_reg(5);
end if;
rddata_reg(0) <= multiboot_cr_rdbootsts_int;
rddata_reg(1) <= multiboot_cr_wmb_int;
rddata_reg(2) <= multiboot_cr_wgb_int;
rddata_reg(3) <= multiboot_cr_iprog_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
--rddata_reg(4) <= multiboot_cr_flr_int;
......@@ -188,8 +187,8 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(16) <= multiboot_cr_iprog_unl_int;
rddata_reg(17) <= multiboot_cr_iprog_int;
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
......@@ -244,14 +243,20 @@ begin
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
multiboot_far_data_load_int <= '1';
multiboot_far_xfer_int <= wrdata_reg(8);
multiboot_far_cs_int <= wrdata_reg(10);
--multiboot_far_data_load_int <= '1';
multiboot_far_data_int <= wrdata_reg(23 downto 0);
multiboot_far_nbytes_int <= wrdata_reg(25 downto 24);
multiboot_far_xfer_int <= wrdata_reg(26);
multiboot_far_cs_int <= wrdata_reg(27);
end if;
rddata_reg(7 downto 0) <= multiboot_far_data_i;
rddata_reg(8) <= multiboot_far_xfer_int;
rddata_reg(9) <= multiboot_far_ready_int;
rddata_reg(10) <= multiboot_far_cs_int;
rddata_reg(23 downto 0) <= multiboot_far_data_i;
rddata_reg(25 downto 24) <= multiboot_far_nbytes_int;
rddata_reg(26) <= multiboot_far_xfer_int;
rddata_reg(27) <= multiboot_far_cs_int;
rddata_reg(28) <= multiboot_far_ready_int;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
-- when "101" =>
......@@ -278,10 +283,6 @@ begin
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- Read BOOTSTS register
multiboot_cr_rdbootsts_o <= multiboot_cr_rdbootsts_int;
-- Write MultiBoot Bitstream
multiboot_cr_wmb_o <= multiboot_cr_wmb_int;
-- Write Golden Bitstream
multiboot_cr_wgb_o <= multiboot_cr_wgb_int;
-- IPROG
multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
---- Flash read
......@@ -293,8 +294,9 @@ begin
-- MBBAR
multiboot_mbbar_o <= multiboot_mbbar_int;
-- FAR outputs
multiboot_far_data_o <= wrdata_reg(7 downto 0);
multiboot_far_data_load_o <= multiboot_far_data_load_int;
multiboot_far_data_o <= multiboot_far_data_int; --wrdata_reg(23 downto 0);
multiboot_far_nbytes_o <= multiboot_far_nbytes_int;
--multiboot_far_data_load_o <= multiboot_far_data_load_int;
multiboot_far_xfer_o <= multiboot_far_xfer_int;
multiboot_far_cs_o <= multiboot_far_cs_int;
---- Flash data word
......
hdl/multiboot/rtl/xil_multiboot.vhd
View file @ bfa6c70e
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hdl/multiboot/sim/testbench.vhd
View file @ bfa6c70e
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hdl/multiboot/sim/transcript
View file @ bfa6c70e
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hdl/multiboot/sim/wave.do
View file @ bfa6c70e
......@@ -6,7 +6,7 @@ add wave -noupdate /testbench/transfer
add wave -noupdate /testbench/write
add wave -noupdate /testbench/str
add wave -noupdate -radix hexadecimal /testbench/wb_adr
add wave -noupdate -radix hexadecimal -childformat {{/testbench/wb_dat_in(31) -radix hexadecimal} {/testbench/wb_dat_in(30) -radix hexadecimal} {/testbench/wb_dat_in(29) -radix hexadecimal} {/testbench/wb_dat_in(28) -radix hexadecimal} {/testbench/wb_dat_in(27) -radix hexadecimal} {/testbench/wb_dat_in(26) -radix hexadecimal} {/testbench/wb_dat_in(25) -radix hexadecimal} {/testbench/wb_dat_in(24) -radix hexadecimal} {/testbench/wb_dat_in(23) -radix hexadecimal} {/testbench/wb_dat_in(22) -radix hexadecimal} {/testbench/wb_dat_in(21) -radix hexadecimal} {/testbench/wb_dat_in(20) -radix hexadecimal} {/testbench/wb_dat_in(19) -radix hexadecimal} {/testbench/wb_dat_in(18) -radix hexadecimal} {/testbench/wb_dat_in(17) -radix hexadecimal} {/testbench/wb_dat_in(16) -radix hexadecimal} {/testbench/wb_dat_in(15) -radix hexadecimal} {/testbench/wb_dat_in(14) -radix hexadecimal} {/testbench/wb_dat_in(13) -radix hexadecimal} {/testbench/wb_dat_in(12) -radix hexadecimal} {/testbench/wb_dat_in(11) -radix hexadecimal} {/testbench/wb_dat_in(10) -radix hexadecimal} {/testbench/wb_dat_in(9) -radix hexadecimal} {/testbench/wb_dat_in(8) -radix hexadecimal} {/testbench/wb_dat_in(7) -radix hexadecimal} {/testbench/wb_dat_in(6) -radix hexadecimal} {/testbench/wb_dat_in(5) -radix hexadecimal} {/testbench/wb_dat_in(4) -radix hexadecimal} {/testbench/wb_dat_in(3) -radix hexadecimal} {/testbench/wb_dat_in(2) -radix hexadecimal} {/testbench/wb_dat_in(1) -radix hexadecimal} {/testbench/wb_dat_in(0) -radix hexadecimal}} -subitemconfig {/testbench/wb_dat_in(31) {-radix hexadecimal} /testbench/wb_dat_in(30) {-radix hexadecimal} /testbench/wb_dat_in(29) {-radix hexadecimal} /testbench/wb_dat_in(28) {-radix hexadecimal} /testbench/wb_dat_in(27) {-radix hexadecimal} /testbench/wb_dat_in(26) {-radix hexadecimal} /testbench/wb_dat_in(25) {-radix hexadecimal} /testbench/wb_dat_in(24) {-radix hexadecimal} /testbench/wb_dat_in(23) {-radix hexadecimal} /testbench/wb_dat_in(22) {-radix hexadecimal} /testbench/wb_dat_in(21) {-radix hexadecimal} /testbench/wb_dat_in(20) {-radix hexadecimal} /testbench/wb_dat_in(19) {-radix hexadecimal} /testbench/wb_dat_in(18) {-radix hexadecimal} /testbench/wb_dat_in(17) {-radix hexadecimal} /testbench/wb_dat_in(16) {-radix hexadecimal} /testbench/wb_dat_in(15) {-radix hexadecimal} /testbench/wb_dat_in(14) {-radix hexadecimal} /testbench/wb_dat_in(13) {-radix hexadecimal} /testbench/wb_dat_in(12) {-radix hexadecimal} /testbench/wb_dat_in(11) {-radix hexadecimal} /testbench/wb_dat_in(10) {-radix hexadecimal} /testbench/wb_dat_in(9) {-radix hexadecimal} /testbench/wb_dat_in(8) {-radix hexadecimal} /testbench/wb_dat_in(7) {-radix hexadecimal} /testbench/wb_dat_in(6) {-radix hexadecimal} /testbench/wb_dat_in(5) {-radix hexadecimal} /testbench/wb_dat_in(4) {-radix hexadecimal} /testbench/wb_dat_in(3) {-radix hexadecimal} /testbench/wb_dat_in(2) {-radix hexadecimal} /testbench/wb_dat_in(1) {-radix hexadecimal} /testbench/wb_dat_in(0) {-radix hexadecimal}} /testbench/wb_dat_in
add wave -noupdate -radix hexadecimal -childformat {{/testbench/wb_dat_in(31) -radix hexadecimal} {/testbench/wb_dat_in(30) -radix hexadecimal} {/testbench/wb_dat_in(29) -radix hexadecimal} {/testbench/wb_dat_in(28) -radix hexadecimal} {/testbench/wb_dat_in(27) -radix hexadecimal} {/testbench/wb_dat_in(26) -radix hexadecimal} {/testbench/wb_dat_in(25) -radix hexadecimal} {/testbench/wb_dat_in(24) -radix hexadecimal} {/testbench/wb_dat_in(23) -radix hexadecimal} {/testbench/wb_dat_in(22) -radix hexadecimal} {/testbench/wb_dat_in(21) -radix hexadecimal} {/testbench/wb_dat_in(20) -radix hexadecimal} {/testbench/wb_dat_in(19) -radix hexadecimal} {/testbench/wb_dat_in(18) -radix hexadecimal} {/testbench/wb_dat_in(17) -radix hexadecimal} {/testbench/wb_dat_in(16) -radix hexadecimal} {/testbench/wb_dat_in(15) -radix hexadecimal} {/testbench/wb_dat_in(14) -radix hexadecimal} {/testbench/wb_dat_in(13) -radix hexadecimal} {/testbench/wb_dat_in(12) -radix hexadecimal} {/testbench/wb_dat_in(11) -radix hexadecimal} {/testbench/wb_dat_in(10) -radix hexadecimal} {/testbench/wb_dat_in(9) -radix hexadecimal} {/testbench/wb_dat_in(8) -radix hexadecimal} {/testbench/wb_dat_in(7) -radix hexadecimal} {/testbench/wb_dat_in(6) -radix hexadecimal} {/testbench/wb_dat_in(5) -radix hexadecimal} {/testbench/wb_dat_in(4) -radix hexadecimal} {/testbench/wb_dat_in(3) -radix hexadecimal} {/testbench/wb_dat_in(2) -radix hexadecimal} {/testbench/wb_dat_in(1) -radix hexadecimal} {/testbench/wb_dat_in(0) -radix hexadecimal}} -subitemconfig {/testbench/wb_dat_in(31) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(30) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(29) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(28) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(27) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(26) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(25) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(24) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(23) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(22) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(21) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(20) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(19) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(18) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(17) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(16) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(15) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(14) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(13) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(12) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(11) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(10) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(9) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(8) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(7) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(6) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(5) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(4) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(3) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(2) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(1) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(0) {-height 16 -radix hexadecimal}} /testbench/wb_dat_in
add wave -noupdate -radix hexadecimal /testbench/wb_dat_out
add wave -noupdate /testbench/wb_cyc
add wave -noupdate /testbench/wb_stb
......@@ -14,6 +14,7 @@ add wave -noupdate /testbench/wb_we
add wave -noupdate /testbench/wb_ack
add wave -noupdate /testbench/wb_stall
add wave -noupdate /testbench/ready
add wave -noupdate -radix hexadecimal /testbench/fldat
add wave -noupdate -divider regs
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_data_load_int
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_xfer_int
......@@ -23,18 +24,30 @@ add wave -noupdate -divider FSM
add wave -noupdate /testbench/UUT/cmp_fsm/state
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd_reg
add wave -noupdate /testbench/UUT/cmp_fsm/fl_bcnt
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/fl_sreg
add wave -noupdate -divider {flash ctrl}
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/read_i
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_o
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_flash_ctrl/data_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_cs_n_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_sclk_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_mosi_o
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_miso_i
add wave -noupdate -divider fsm-spi
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_far_data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_far_data_o
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_nbytes_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_xfer_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_cs_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_ready_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_xfer_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_cs_o
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_ready_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_int
add wave -noupdate /testbench/UUT/cmp_fsm/spi_cnt
add wave -noupdate -divider {spi pins}
add wave -noupdate /testbench/UUT/spi_cs_n_o
add wave -noupdate /testbench/UUT/spi_sclk_o
add wave -noupdate /testbench/UUT/spi_mosi_o
add wave -noupdate /testbench/UUT/spi_miso_i
add wave -noupdate -divider spi
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_spi_master/data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_spi_master/data_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {792 ns} 0}
WaveRestoreCursors {{Cursor 1} {63727 ns} 0}
configure wave -namecolwidth 335
configure wave -valuecolwidth 99
configure wave -justifyvalue left
......@@ -49,4 +62,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {3196 ns}
WaveRestoreZoom {61939 ns} {66867 ns}
hdl/multiboot/syn/conv_ttl_blo.gise
View file @ bfa6c70e
......@@ -53,7 +53,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
......@@ -64,7 +63,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
......@@ -75,35 +73,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1380021433" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021433" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021433" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1380021433">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021434" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021454" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1380021434">
<transform xil_pn:end_ts="1381745675" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1381745655">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -121,11 +119,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1380021454" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1380021454">
<transform xil_pn:end_ts="1381745675" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1381745675">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1380021465" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1380021454">
<transform xil_pn:end_ts="1381745686" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1381745675">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,7 +132,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1380021551" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1380021465">
<transform xil_pn:end_ts="1381745744" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1381745686">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -147,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1380021604" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1380021551">
<transform xil_pn:end_ts="1381745799" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1381745744">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -161,7 +159,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1380021640" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1380021604">
<transform xil_pn:end_ts="1381745835" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1381745799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -173,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1380021604" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1380021593">
<transform xil_pn:end_ts="1381745799" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381745788">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
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