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Conv TTL Blocking - Gateware
Commits
eb348ac7
Commit
eb348ac7
authored
Dec 08, 2013
by
Theodor-Adrian Stana
Browse files
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Changed registers component and made the necessary changes at top-level
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
18bc9038
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8 changed files
with
570 additions
and
392 deletions
+570
-392
hdlguide-conv-ttl-blo.tex
doc/hdlguide/hdlguide-conv-ttl-blo.tex
+97
-50
conv_regs.vhd
modules/Release/conv_regs.vhd
+51
-33
conv_regs.wb
modules/Release/conv_regs.wb
+25
-16
rtm_detector.vhd
modules/rtm_detector.vhd
+13
-8
Makefile
syn/Release/Makefile
+1
-0
conv_ttl_blo.xise
syn/Release/conv_ttl_blo.xise
+100
-96
conv_ttl_blo.ucf
top/Release/conv_ttl_blo.ucf
+41
-41
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+242
-148
No files found.
doc/hdlguide/hdlguide-conv-ttl-blo.tex
View file @
eb348ac7
...
...
@@ -725,15 +725,15 @@ following sections list the memory map of each peripheral.
\multicolumn
{
1
}{
c
}{
\textbf
{
Periph.
}}
&
\multicolumn
{
2
}{
c
}{
\textbf
{
Address
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Base
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
End
}}
&
\\
\hline
CSR
&
0x000
&
0x0f
&
Control and status register
\\
MultiBoot
&
0x040
&
0x5f
&
MultiBoot module
\\
CSR
&
0x000
&
0x0
0
f
&
Control and status register
\\
MultiBoot
&
0x040
&
0x
0
5f
&
MultiBoot module
\\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
% CSR
%
SUBSEC:
CSR
%------------------------------------------------------------------------------
\subsection
{
Control and status registers
}
\label
{
app:memmap-csr
}
...
...
@@ -745,8 +745,8 @@ following sections list the memory map of each peripheral.
\textbf
{
Offset
}
&
\textbf
{
Name
}
&
\textbf
{
Description
}
\\
0x0
&
BID
&
Board ID register
\\
0x4
&
SR
&
Status register
\\
0x8
&
\textit
{
Reserved
}
&
Read undefined; write as 0
\\
0xc
&
\textit
{
Reserved
}
&
Read undefined; write as 0
\\
0x8
&
CR
&
Control register
\\
0xc
&
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
\end{tabular}
\end{table}
...
...
@@ -755,7 +755,7 @@ following sections list the memory map of each peripheral.
\begin{tabular}
{
l l c c l
}
\textbf
{
Bits
}
&
\textbf
{
Field
}
&
\textbf
{
Access
}
&
\textbf
{
Default
}
&
\textbf
{
Description
}
\\
31..0
&
ID
&
R/O
&
0x
424c4f32
&
Board ID
\\
31..0
&
ID
&
R/O
&
0x
54424c4f
&
Board ID
\\
\end{tabular}
\vspace*
{
11pt
}
...
...
@@ -764,7 +764,7 @@ following sections list the memory map of each peripheral.
{
\begin{tabular}
{
l l
}
\textbf
{
Field
}
&
\textbf
{
Description
}
\\
ID
&
Board ID (ASCII string
\textbf
{
BLO2
}
)
\\
ID
&
Board ID (ASCII string
\textbf
{
TBLO
}
)
\\
\end{tabular}
}
...
...
@@ -773,10 +773,11 @@ following sections list the memory map of each peripheral.
\begin{tabular}
{
l l c c l
}
\textbf
{
Bits
}
&
\textbf
{
Field
}
&
\textbf
{
Access
}
&
\textbf
{
Default
}
&
\textbf
{
Description
}
\\
15..0
&
FWVERS
&
R/O
&
X
&
Firmware version
\\
23..16
&
SWITCHES
&
R/O
&
X
&
Switch status
\\
29..24
&
RTM
&
R/O
&
X
&
RTM detection lines
\\
31..30
&
\textit
{
Reserved
}
&
R/O
&
X
&
\\
7..0
&
FWVERS
&
R/O
&
X
&
Firmware version
\\
15..8
&
SWITCHES
&
R/O
&
X
&
Switch status
\\
21..16
&
RTM
&
R/O
&
X
&
RTM detection lines
\\
22
&
CWDTO
&
R/W
&
0
&
Communication Watchdog Timeout
\\
31..23
&
\textit
{
Reserved
}
&
--
&
X
&
\\
\end{tabular}
\noindent
...
...
@@ -785,12 +786,12 @@ following sections list the memory map of each peripheral.
\textbf
{
Field
}
&
\textbf
{
Description
}
\\
FWVERS
&
Firmware version
\newline
-- leftmost
byt
e
\textit
{
hex value
}
is major release
\textit
{
decimal value
}
\newline
-- rightmost
byt
e
\textit
{
hex value
}
is minor release
\textit
{
decimal value
}
\newline
-- leftmost
nibbl
e
\textit
{
hex value
}
is major release
\textit
{
decimal value
}
\newline
-- rightmost
nibbl
e
\textit
{
hex value
}
is minor release
\textit
{
decimal value
}
\newline
e.g.
\newline
0x
0101 -- v1.0
1
\newline
0x
0107 -- v1.07
\newline
0x
0274 -- v2.74
\newline
0x
11 -- v1.
1
\newline
0x
1e -- v1.15
\newline
0x
20 -- v2.0
\newline
etc.
\\
SWITCHES
&
Current switch status
\newline
bit 0 -- SW1.1
\newline
...
...
@@ -800,14 +801,47 @@ following sections list the memory map of each peripheral.
\textbf
{
1
}
-- switch is
\textbf
{
OFF
}
\newline
\textbf
{
0
}
-- switch is
\textbf
{
ON
}
\\
RTM
&
RTM detection lines status
\newline
\textbf
{
0
}
-- line active
\newline
\textbf
{
1
}
-- line inactive
\\
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
\textbf
{
0
}
-- line active
\newline
\textbf
{
1
}
-- line inactive
\\
CWDTO
&
Communication watchdog timeout status
\newline
\textbf
{
0
}
-- watchdog idle
\newline
\textbf
{
1
}
-- communication error has occured and watchdog timer fired
\newline
This bit is cleared by writing a '1' to it
\\
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection
{
Control register
}
\begin{tabular}
{
l l c c l
}
\textbf
{
Bits
}
&
\textbf
{
Field
}
&
\textbf
{
Access
}
&
\textbf
{
Default
}
&
\textbf
{
Description
}
\\
0
&
RST
\_
UNL
&
R/W
&
0
&
Reset bit unlock
\\
1
&
RST
&
R/W
&
0
&
Reset bit
\\
31..2
&
\textit
{
Reserved
}
&
--
&
X
&
\\
\end{tabular}
\noindent
{
\begin{tabular}
{
l p
{
.8
\textwidth
}}
\textbf
{
Field
}
&
\textbf
{
Description
}
\\
RST
\_
UNL
&
Reset bit unlock
\newline
\textbf
{
0
}
-- RST bit locked, cannot be written
\newline
\textbf
{
1
}
-- RST bit unlocked, can be written
\\
RST
&
Reset bit
\newline
\textbf
{
0
}
-- Idle
\newline
\textbf
{
1
}
-- Initiate a system reset
\newline
This bit needs to be unlocked by writing a '1' to the RST
\_
UNL bit in a
previous cycle. A write to this bit while RST
\_
UNL = '0' has no effect.
\newline
Writing this bit to 1 with RST
\_
UNL = '1' will issue a system reset and
the communication to the board will be lost for approx. 100~ms
\\
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
\end{tabular}
}
%------------------------------------------------------------------------------
%
MULTIBOOT
%
SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\subsection
{
MultiBoot module
}
\label
{
app:memmap-multiboot
}
...
...
@@ -825,9 +859,9 @@ following sections list the memory map of each peripheral.
0x08
&
GBBAR
&
Golden Bitstream Base Address Register
\\
0x0c
&
MBBAR
&
Multiboot Bitstream Base Address Register
\\
0x10
&
FAR
&
Flash access register
\\
0x14
&
\textit
{
Reserved
}
&
Read undefined; write as 0
\\
0x18
&
\textit
{
Reserved
}
&
Read undefined; write as 0
\\
0x1c
&
\textit
{
Reserved
}
&
Read undefined; write as 0
\\
0x14
&
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
0x18
&
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
0x1c
&
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
\end{tabular}
}
...
...
@@ -851,26 +885,35 @@ following sections list the memory map of each peripheral.
{
\begin{tabular}
{
l p
{
.7
\textwidth
}}
\textbf
{
Field
}
&
\textbf
{
Description
}
\\
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
IPROG
&
When 1, it triggers the FSM to send the IPROG command to the ICAP controller
\newline
This bit needs to be unlocked by setting the IPROG
\_
UNL bit in a previous cycle
\\
IPROG
\_
UNL
&
Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing
the IPROG bit
\\
RDCFGREG
&
Initiate a read from the FPGA configuration register at address CFGREGADR
\newline
This bit is automatically cleared by hardware
\\
\textit
{
Reserved
}
&
Write as '0'; read undefined.
\\
IPROG
&
Start IPROG sequence
\newline
\textbf
{
0
}
-- Idle
\newline
\textbf
{
1
}
-- Start the IPROG sequence
\newline
This bit needs to be unlocked by setting the IPROG
\_
UNL bit in a previous cycle. Any
write to this bit with IPROG
\_
UNL = '0' has no effect.
\newline
Writing this bit to '1' with IPROG
\_
UNL = '1' will issue the IPROG sequence and
communication to the board will be lost until reprogramming is completed
\\
IPROG
\_
UNL
&
Unlock bit for the IPROG command
\newline
\textbf
{
0
}
-- IPROG bit locked, cannot be written
\newline
\textbf
{
1
}
-- IPROG bit unlocked, can be written
\\
RDCFGREG
&
Read FPGA configuration register
\newline
\textbf
{
0
}
-- Idle
\newline
\textbf
{
1
}
-- Initiate read from configuration register at address CFGREGADR
\newline
This bit is automatically cleared by hardware.
\\
CFGREGADR
&
The address of the FPGA configuration register to read (see Configuration Registers
section in~
\cite
{
ug380
}
)
\\
section in~
\cite
{
ug380
}
)
\\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection
{
IMG
R -- Image Register
}
\label
{
app:memmap-multiboot-
img
r
}
\subsubsection
{
S
R -- Image Register
}
\label
{
app:memmap-multiboot-
s
r
}
\begin{tabular}
{
l l c c l
}
\textbf
{
Bits
}
&
\textbf
{
Field
}
&
\textbf
{
Access
}
&
\textbf
{
Default
}
&
\textbf
{
Description
}
\\
31..17
&
\textit
{
Reserved
}
&
--
&
X
&
\\
16
&
VALID
&
R/O
&
0
&
Image register is valid
\\
31..18
&
\textit
{
Reserved
}
&
--
&
X
&
\\
17
&
WDTO
&
R/W
&
0
&
Watchdog timeout
\\
16
&
IMGVALID
&
R/O
&
0
&
Image register is valid
\\
15..0
&
CFGREGIMG
&
R/O
&
0
&
Config. register image
\\
\end{tabular}
...
...
@@ -880,14 +923,16 @@ following sections list the memory map of each peripheral.
{
\begin{tabular}
{
l p
{
.7
\textwidth
}}
\textbf
{
Field
}
&
\textbf
{
Description
}
\\
\textit
{
Reserved
}
&
Write as '0'; read undefined
\\
VALID
&
A read has been performed from the FPGA configuration
register at address CR.CFGREGADR, and its value is
present in CFGREGIMG
\\
CFGREGIMG
&
Contains the value of the FPGA configuration register;
validated by the VALID bit (see Configuration Registers
section in~
\cite
{
ug380
}
)
\\
\textbf
{
Field
}
&
\textbf
{
Description
}
\\
\textit
{
Reserved
}
&
Write as '0'; read undefined.
\\
WDTO
&
The watchdog of the MultiBoot FSM has timed out
\newline
This bit is cleared by writing a '1' to it
\\
IMGVALID
&
A read has been performed from the FPGA configuration
register at address CR.CFGREGADR, and its value is
present in CFGREGIMG
\\
CFGREGIMG
&
Contains the value of the FPGA configuration register
(see Configuration Registers section in~
\cite
{
ug380
}
);
validated by the IMGVALID bit
\\
\end{tabular}
}
...
...
@@ -984,15 +1029,17 @@ following sections list the memory map of each peripheral.
and NBYTES read from the chip present in DATA fields
\\
CS
&
SPI chip select. Note that this pin has opposite polarity
than the normal SPI chip select pin:
\newline
'1' -- flash chip is selected (CS pin = 0)
\newline
'0' -- flash chip is not selected (CS pin = 1)
\\
XFER
&
'1' -- starts SPI transfer
\newline
\textbf
{
0
}
-- Flash chip is not selected (CS pin = 1)
\newline
\textbf
{
1
}
-- Flash chip is selected (CS pin = 0)
\\
XFER
&
Start SPI transfer
\newline
\textbf
{
1
}
-- Idle
\newline
\textbf
{
1
}
-- Start SPI transfer
\newline
This bit is automatically cleared by hardware
\\
NBYTES
&
Number of DATA fields to send in one transfer
\newline
0 -- s
end 1 byte (DATA[0])
\newline
1 -- s
end 2 bytes (DATA[0], DATA[1])
\newline
2 -- s
end 3 bytes (DATA[0], DATA[1], DATA[2])
\newline
3
--
\textit
{
Reserved
}
\\
\textbf
{
0
}
-- S
end 1 byte (DATA[0])
\newline
\textbf
{
1
}
-- S
end 2 bytes (DATA[0], DATA[1])
\newline
\textbf
{
2
}
-- S
end 3 bytes (DATA[0], DATA[1], DATA[2])
\newline
\textbf
{
3
}
--
\textit
{
Reserved
}
\\
DATA[2]
&
Write this register with the value of data byte 2
\newline
After an SPI transfer, this register contains the value of
data byte 2 read from the flash
\\
...
...
modules/Release/conv_regs.vhd
View file @
eb348ac7
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri
Aug 2 16:02:13
2013
-- Created : Fri
Dec 6 15:43:55
2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
...
...
@@ -27,26 +27,31 @@ entity conv_regs is
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i
:
in
std_logic_vector
(
15
downto
0
);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o
:
out
std_logic
;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o
:
out
std_logic
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
reg_id_bits_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
reg_sr_fwvers_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
reg_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
reg_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
reg_sr_i2c_wdto_o
:
out
std_logic
;
reg_sr_i2c_wdto_i
:
in
std_logic
;
reg_sr_i2c_wdto_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'Control Register'
reg_cr_rst_unlock_o
:
out
std_logic
;
reg_cr_rst_unlock_i
:
in
std_logic
;
reg_cr_rst_unlock_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o
:
out
std_logic
;
reg_cr_rst_i
:
in
std_logic
;
reg_cr_rst_load_o
:
out
std_logic
);
end
conv_regs
;
architecture
syn
of
conv_regs
is
signal
conv_regs_id_bits_int
:
std_logic_vector
(
31
downto
0
);
signal
conv_regs_cr_rst_unlock_int
:
std_logic
;
signal
conv_regs_cr_rst_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -74,47 +79,59 @@ begin
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
conv_regs_id_bits_int
<=
x"424c4f32"
;
conv_regs_cr_rst_unlock_int
<=
'0'
;
conv_regs_cr_rst_int
<=
'0'
;
reg_sr_i2c_wdto_load_o
<=
'0'
;
reg_cr_rst_unlock_load_o
<=
'0'
;
reg_cr_rst_load_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
reg_sr_i2c_wdto_load_o
<=
'0'
;
reg_cr_rst_unlock_load_o
<=
'0'
;
reg_cr_rst_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
reg_sr_i2c_wdto_load_o
<=
'0'
;
reg_cr_rst_unlock_load_o
<=
'0'
;
reg_cr_rst_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
if
(
wb_we_i
=
'1'
)
then
conv_regs_id_bits_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
31
downto
0
)
<=
conv_regs_id_bits_int
;
rddata_reg
(
31
downto
0
)
<=
reg_id_bits_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
if
(
wb_we_i
=
'1'
)
then
reg_sr_i2c_wdto_load_o
<=
'1'
;
end
if
;
rddata_reg
(
15
downto
0
)
<=
conv_regs_sr_fwvers_i
;
rddata_reg
(
23
downto
16
)
<=
conv_regs_sr_switches_i
;
rddata_reg
(
29
downto
24
)
<=
conv_regs_sr_rtm_i
;
rddata_reg
(
7
downto
0
)
<=
reg_sr_fwvers_i
;
rddata_reg
(
15
downto
8
)
<=
reg_sr_switches_i
;
rddata_reg
(
21
downto
16
)
<=
reg_sr_rtm_i
;
rddata_reg
(
22
)
<=
reg_sr_i2c_wdto_i
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
conv_regs_cr_rst_unlock_int
<=
wrdata_reg
(
0
);
conv_regs_cr_rst_int
<=
wrdata_reg
(
1
);
end
if
;
rddata_reg
(
0
)
<=
conv_regs_cr_rst_unlock_int
;
if
(
conv_regs_cr_rst_unlock_int
=
'1'
)
then
rddata_reg
(
1
)
<=
conv_regs_cr_rst_int
;
reg_cr_rst_unlock_load_o
<=
'1'
;
reg_cr_rst_load_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
reg_cr_rst_unlock_i
;
rddata_reg
(
1
)
<=
reg_cr_rst_i
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
...
...
@@ -161,14 +178,15 @@ begin
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- bits
conv_regs_id_bits_o
<=
conv_regs_id_bits_int
;
-- fwvers
-- switches
-- RTM detection
-- I2C Watchdog Timeout
reg_sr_i2c_wdto_o
<=
wrdata_reg
(
22
);
-- Reset unlock bit
conv_regs_cr_rst_unlock_o
<=
conv_regs_cr_rst_unlock_int
;
reg_cr_rst_unlock_o
<=
wrdata_reg
(
0
)
;
-- Reset bit
conv_regs_cr_rst_o
<=
conv_regs_cr_rst_int
;
reg_cr_rst_o
<=
wrdata_reg
(
1
)
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
modules/Release/conv_regs.wb
View file @
eb348ac7
peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "
conv_regs
";
prefix = "
reg
";
reg {
name = "Board ID
r
egister";
description = "Bits of ID register, defaulting to ASCII string
of BLO2
";
name = "Board ID
R
egister";
description = "Bits of ID register, defaulting to ASCII string
TBLO
";
prefix = "id";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Status
r
egister";
description = "Contains
fields for firmware version, switches, RTM detection lines
";
name = "Status
R
egister";
description = "Contains
various board status information
";
prefix = "sr";
field {
name = "fwvers";
prefix = "fwvers";
type = SLV;
size =
16
;
size =
8
;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
...
...
@@ -32,7 +34,6 @@ peripheral {
prefix = "switches";
type = SLV;
size = 8;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
...
...
@@ -41,13 +42,21 @@ peripheral {
prefix = "rtm";
type = SLV;
size = 6;
align = 24;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "I2C Watchdog Timeout";
prefix = "i2c_wdto";
type = BIT;
size = 1;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Control
r
egister";
name = "Control
R
egister";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
-- field {
...
...
@@ -95,22 +104,22 @@ peripheral {
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
description = "1 -
unlock reset bit
\
0 - lock reset bit
";
description = "1 -
Reset bit unlocked
\
0 - Reset bit locked
";
type = BIT;
a
lign = 30
;
a
ccess_dev = READ_WRITE
;
access_bus = READ_WRITE;
access_dev = READ_ONLY
;
load = LOAD_EXT
;
};
field {
name = "Reset bit";
prefix = "rst";
description = "1 - initiate logic reset\
0 - no reset";
0 - no reset";
type = BIT;
align = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
modules/rtm_detector.vhd
View file @
eb348ac7
...
...
@@ -75,27 +75,32 @@
-- TODO: -
--==============================================================================
library
IEEE
;
library
work
;
library
ieee
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
IEEE
.
NUMERIC_STD
.
ALL
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
rtm_detector
is
port
(
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
rtmm_ok_o
:
out
std_logic
;
rtmp_ok_o
:
out
std_logic
);
end
entity
rtm_detector
;
architecture
Behavioral
of
rtm_detector
is
architecture
behav
of
rtm_detector
is
--==============================================================================
-- architecture begin
--==============================================================================
begin
rtmm_ok_o
<=
'0'
when
(
rtmm_i
=
"111"
)
else
'1'
;
rtmp_ok_o
<=
'0'
when
(
rtmp_i
=
"111"
)
else
'1'
;
end
Behavioral
;
end
behav
;
--==============================================================================
-- architecture end
--==============================================================================
syn/Release/Makefile
View file @
eb348ac7
...
...
@@ -59,6 +59,7 @@ FILES := ../../top/Release/conv_ttl_blo.ucf \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
\
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
\
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
\
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
\
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
\
...
...
syn/Release/conv_ttl_blo.xise
View file @
eb348ac7
...
...
@@ -56,7 +56,7 @@
<property
xil_pn:name=
"Configuration Rate spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Correlate Output to Input Design"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create ASCII Configuration File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Create Bit File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create I/O Pads from Ports"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create IEEE 1532 Configuration File spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -164,7 +164,7 @@
<property
xil_pn:name=
"MultiBoot: Insert IPROG CMD in the Bitfile spartan6"
xil_pn:value=
"Enable"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Next Configuration Mode spartan6"
xil_pn:value=
"001"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Starting Address for Golden Configuration spartan6"
xil_pn:value=
"0x00000000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Starting Address for Next Configuration spartan6"
xil_pn:value=
"0x0
0000000"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"MultiBoot: Starting Address for Next Configuration spartan6"
xil_pn:value=
"0x0
b170000"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"MultiBoot: Use New Mode for Next Configuration spartan6"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: User-Defined Register for Failsafe Scheme spartan6"
xil_pn:value=
"0x0000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Hierarchy"
xil_pn:value=
"As Optimized"
xil_pn:valueState=
"default"
/>
...
...
@@ -175,7 +175,7 @@
<property
xil_pn:name=
"Optimization Effort spartan6"
xil_pn:value=
"Normal"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"Speed"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
"
"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
"
-g next_config_register_write:Disable"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Par"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -215,6 +215,7 @@
<property
xil_pn:name=
"Power Reduction Xst"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Generator"
xil_pn:value=
"ProjNav"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
...
...
@@ -243,7 +244,7 @@
<property
xil_pn:name=
"Reset On Configuration Pulse Width"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Resource Sharing"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Retain Hierarchy"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Retry Configuration if CRC Error Occurs spartan6"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Retry Configuration if CRC Error Occurs spartan6"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Run Design Rules Checker (DRC)"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Map"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
...
...
@@ -313,7 +314,7 @@
<property
xil_pn:name=
"Verilog Macros"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wait for DCM and PLL Lock (Output Events) spartan6"
xil_pn:value=
"Default (NoWait)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wakeup Clock spartan6"
xil_pn:value=
"Startup Clock"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0x
FFFF"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0x
1FFF"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Write Timing Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<!-- -->
...
...
@@ -406,279 +407,282 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"23"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
genrams/genram_pk
g.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
common/gc_fsm_watchdo
g.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"24"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/
memory_loader
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/
genram
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"25"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/
generic_shiftreg_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/
memory_loader_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"26"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/
inferred_sync
_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/
generic_shiftreg
_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"27"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/inferred_
a
sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"28"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
wishbone/wishbone_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
genrams/inferred_async_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"29"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
genrams/xilinx/generic_dpram
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
wishbone/wishbone_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"30"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram
_sameclock
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"31"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_
dual
clock.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_
same
clock.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"32"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_
simple_dpram
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_
dpram_dualclock
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
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<bindings/>
...
...
top/Release/conv_ttl_blo.ucf
View file @
eb348ac7
...
...
@@ -61,14 +61,14 @@
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk125";
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50%;
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50
%;
##=============================================================================
##-- FRONT PANEL TTLs
...
...
@@ -230,30 +230,30 @@ NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_blo_in_i[1]" IOSTANDARD =
LVCMOS33
;
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_blo_in_i[2]" IOSTANDARD =
LVCMOS33
;
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_blo_in_i[3]" IOSTANDARD =
LVCMOS33
;
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_blo_in_i[4]" IOSTANDARD =
LVCMOS33
;
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_blo_in_i[5]" IOSTANDARD =
LVCMOS33
;
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_blo_in_i[6]" IOSTANDARD =
LVCMOS33
;
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_trig_blo_o[1]" IOSTANDARD =
LVCMOS33
;
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_trig_blo_o[2]" IOSTANDARD =
LVCMOS33
;
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_trig_blo_o[3]" IOSTANDARD =
LVCMOS33
;
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_trig_blo_o[4]" IOSTANDARD =
LVCMOS33
;
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_trig_blo_o[5]" IOSTANDARD =
LVCMOS33
;
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_trig_blo_o[6]" IOSTANDARD =
LVCMOS33
;
##=============================================================================
##-- VME CONNECTOR SIGNALS
...
...
@@ -303,13 +303,13 @@ NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_prom_cclk_o" IOSTANDARD =
LVCMOS33
;
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_prom_cso_b_n_o" IOSTANDARD =
LVCMOS33
;
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_prom_miso_i" IOSTANDARD =
LVCMOS33
;
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD =
"LVCMOS33"
;
NET "fpga_prom_mosi_o" IOSTANDARD =
LVCMOS33
;
##=============================================================================
##-- WHITE RABBIT
...
...
@@ -340,20 +340,20 @@ NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i"
LOC = G3;
NET "fpga_sfp_los_i"
IOSTANDARD = "LVCMOS33"
;
NET "fpga_sfp_mod_def0_i"
LOC = K8;
NET "fpga_sfp_mod_def0_i"
IOSTANDARD = "LVCMOS33"
;
NET "fpga_sfp_rate_select_o"
LOC = C4;
NET "fpga_sfp_rate_select_o"
IOSTANDARD = "LVCMOS33"
;
NET "fpga_sfp_mod_def1_b"
LOC = G4;
NET "fpga_sfp_mod_def1_b"
IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b"
LOC = F3;
NET "fpga_sfp_mod_def2_b"
IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o"
LOC = E4;
NET "fpga_sfp_tx_disable_o"
IOSTANDARD = "LVCMOS33"
;
NET "fpga_sfp_tx_fault_i"
LOC = D2;
NET "fpga_sfp_tx_fault_i"
IOSTANDARD = "LVCMOS33"
;
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i"
IOSTANDARD = LVCMOS33
;
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i"
IOSTANDARD = LVCMOS33
;
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o"
IOSTANDARD = LVCMOS33
;
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o"
IOSTANDARD = LVCMOS33
;
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i"
IOSTANDARD = LVCMOS33
;
##-----------------------------------------------------------------------------
##-- FPGA MGT lines
...
...
@@ -394,19 +394,19 @@ NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD =
"LVCMOS33"
;
NET "extra_switch_n_i[1]" IOSTANDARD =
LVCMOS33
;
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD =
"LVCMOS33"
;
NET "extra_switch_n_i[2]" IOSTANDARD =
LVCMOS33
;
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD =
"LVCMOS33"
;
NET "extra_switch_n_i[3]" IOSTANDARD =
LVCMOS33
;
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD =
"LVCMOS33"
;
NET "extra_switch_n_i[4]" IOSTANDARD =
LVCMOS33
;
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD =
"LVCMOS33"
;
NET "extra_switch_n_i[5]" IOSTANDARD =
LVCMOS33
;
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD =
"LVCMOS33"
;
NET "extra_switch_n_i[6]" IOSTANDARD =
LVCMOS33
;
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD =
"LVCMOS33"
;
NET "extra_switch_n_i[7]" IOSTANDARD =
LVCMOS33
;
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
...
...
top/Release/conv_ttl_blo.vhd
View file @
eb348ac7
--
------------------------------------------------------------------------------
--
==============================================================================
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--
------------------------------------------------------------------------------
--
==============================================================================
--
-- unit name: conv_ttl_blo.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
-- author: Theodor Stana (t.stana@cern.ch)
-- Carlos-Gil-Soriano
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO
-- description:
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
-- components needed in the design and generates the necessary logic for
-- pulse conversion to occur on each channel.
--
-- Details about the HDL design can be found by reading the HDL guide of the
-- project in the doc/ folder.
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] ELMA, Access to board data using SNMP and I2C
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--
------------------------------------------------------------------------------
--
==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--
------------------------------------------------------------------------------
--
==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
...
...
@@ -30,7 +38,12 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
library
unisim
;
...
...
@@ -149,8 +162,18 @@ architecture behav of conv_ttl_blo is
--============================================================================
-- Constant declarations
--============================================================================
-- Board ID - ASCII string "TBLO"
constant
c_board_id
:
std_logic_vector
(
31
downto
0
)
:
=
x"54424c4f"
;
-- Firmware version
constant
c_fwvers
:
std_logic_vector
(
15
downto
0
)
:
=
x"0200"
;
-- - format: M.m
-- - M: major version hex number (e.g. 1)
-- - m: minor version hex number (e.g. 13)
-- - example: first major release v1.0 c_fwvers = x"10";
-- next minor release v1.1 c_fwvers = x"11";
-- 13 minor releases later v1.14 c_fwvers = x"1e";
-- next major release v2.0 c_fwvers = x"20";
constant
c_fwvers
:
std_logic_vector
(
7
downto
0
)
:
=
x"10"
;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
...
...
@@ -199,7 +222,7 @@ architecture behav of conv_ttl_blo is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time
:
positive
:
=
1
2
_
000
_
000
g_reset_time
:
positive
:
=
2
_
000
_
000
);
port
(
...
...
@@ -215,16 +238,20 @@ architecture behav of conv_ttl_blo is
generic
(
-- Pulse width, in number of clk_i cycles
g_pwidth
:
natural
:
=
15
;
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth
:
natural
range
20
to
40
:
=
24
;
-- Glitch filter length:
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_gf_len
:
natural
:
=
4
g_gf_len
:
natural
:
=
1
);
port
(
-- Clock and active-low reset inputs
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -238,37 +265,16 @@ architecture behav of conv_ttl_blo is
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_
i
:
in
std_logic
;
trig_
a_i
:
in
std_logic
;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_gf_len+
3
clk_i cycles
-- glitch filter enabled: g_gf_len+
5
clk_i cycles
pulse_o
:
out
std_logic
);
end
component
ctb_pulse_gen
;
-- Xilinx MultiBoot component
-- (use: remote reprogramming of the FPGA)
component
wb_xil_multiboot
is
port
(
-- Clock and reset input ports
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Wishbone ports
wbs_i
:
in
t_wishbone_slave_in
;
wbs_o
:
out
t_wishbone_slave_out
;
-- SPI ports
spi_cs_n_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
);
end
component
wb_xil_multiboot
;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component
rtm_detector
is
...
...
@@ -295,91 +301,129 @@ architecture behav of conv_ttl_blo is
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i
:
in
std_logic_vector
(
15
downto
0
);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o
:
out
std_logic
;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o
:
out
std_logic
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
reg_id_bits_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
reg_sr_fwvers_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
reg_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
reg_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
reg_sr_i2c_wdto_o
:
out
std_logic
;
reg_sr_i2c_wdto_i
:
in
std_logic
;
reg_sr_i2c_wdto_load_o
:
out
std_logic
;
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control Register'
reg_cr_rst_unlock_o
:
out
std_logic
;
reg_cr_rst_unlock_i
:
in
std_logic
;
reg_cr_rst_unlock_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o
:
out
std_logic
;
reg_cr_rst_i
:
in
std_logic
;
reg_cr_rst_load_o
:
out
std_logic
);
end
component
conv_regs
;
-- MultiBoot component
-- use: remotely reprogram the FPGA
component
wb_xil_multiboot
is
port
(
-- Clock and reset input ports
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Wishbone ports
wbs_i
:
in
t_wishbone_slave_in
;
wbs_o
:
out
t_wishbone_slave_out
;
-- SPI ports
spi_cs_n_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
);
end
component
wb_xil_multiboot
;
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signals
signal
rst_n
:
std_logic
;
signal
rst_n
:
std_logic
;
signal
rst_unlock
:
std_logic
;
signal
rst_unlock_bit
:
std_logic
;
signal
rst_unlock_bit_ld
:
std_logic
;
signal
rst_bit
:
std_logic
;
signal
rst_bit_ld
:
std_logic
;
signal
rst_fr_reg
:
std_logic
;
-- RTM detection signals
signal
rtmm
,
rtmp
:
std_logic_vector
(
2
downto
0
);
signal
rtmm_ok
,
rtmp_ok
:
std_logic
;
signal
rtmm
,
rtmp
:
std_logic_vector
(
2
downto
0
);
signal
rtmm_ok
,
rtmp_ok
:
std_logic
;
-- Signals to/from converter system registers component
signal
rtm_lines
:
std_logic_vector
(
5
downto
0
);
signal
switches_n
:
std_logic_vector
(
7
downto
0
);
signal
rtm_lines
:
std_logic_vector
(
5
downto
0
);
signal
switches_n
:
std_logic_vector
(
7
downto
0
);
signal
wdto_bit
:
std_logic
;
signal
wdto_bit_rst
:
std_logic
;
signal
wdto_bit_rst_ld
:
std_logic
;
-- Signals for pulse generation triggers
signal
trig_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_inv
:
std_logic_vector
(
g_nr_inv_chan
downto
1
);
signal
trig_ttl_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_blo_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced_edge
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_inv
:
std_logic_vector
(
g_nr_inv_chan
downto
1
);
signal
trig_ttl_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_blo_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced_edge
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- TTL-BAR lack of signal counter
signal
ttlbar_nosig_cnt
:
t_ttlbar_nosig_cnt
;
signal
ttlbar_nosig_n
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
ttlbar_nosig_cnt
:
t_ttlbar_nosig_cnt
;
signal
ttlbar_nosig_n
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- Temporary signal for blocking and TTL pulse outputs
signal
pulse_outputs
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_outp
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_outp_d0
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_outp_r_edge_p
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
blo_ch_en
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- Temporary signal for inverted-TTL pulse outputs
signal
inv_outputs
:
std_logic_vector
(
g_nr_inv_chan
downto
1
);
signal
blo_ch_en
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- Pulse status LED signals
signal
front_led_en
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
rear_led_en
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_leds
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_led_cnt
:
t_pulse_led_cnt
;
signal
pulse_leds
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_led_cnt
:
t_pulse_led_cnt
;
-- Output enable signals
signal
oe
,
ttl_oe
:
std_logic
;
signal
blo_oe
,
inv_oe
:
std_logic
;
signal
oe
,
ttl_oe
:
std_logic
;
signal
blo_oe
,
inv_oe
:
std_logic
;
-- Signal for controlling the bicolor LED matrix
signal
bicolor_led_state
:
std_logic_vector
(
23
downto
0
);
signal
bicolor_led_state
:
std_logic_vector
(
23
downto
0
);
-- Wishbone crossbar signals
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_master_in
:
t_wishbone_master_in_array
(
c_nr_slaves
-
1
downto
0
);
signal
xbar_master_out
:
t_wishbone_master_out_array
(
c_nr_slaves
-
1
downto
0
);
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_master_in
:
t_wishbone_master_in_array
(
c_nr_slaves
-
1
downto
0
);
signal
xbar_master_out
:
t_wishbone_master_out_array
(
c_nr_slaves
-
1
downto
0
);
-- I2C bridge signals
signal
i2c_tip
:
std_logic
;
signal
i2c_err
:
std_logic
;
signal
i2c_err_led
:
std_logic
;
signal
i2c_up
:
std_logic
;
signal
i2c_addr
:
std_logic_vector
(
6
downto
0
);
signal
led_i2c
:
std_logic
;
signal
led_i2c_clkdiv
:
unsigned
(
18
downto
0
);
signal
led_i2c_cnt
:
unsigned
(
2
downto
0
);
signal
blink_state
:
std_logic
;
signal
i2c_tip
:
std_logic
;
signal
i2c_err_p
:
std_logic
;
signal
i2c_wdto_p
:
std_logic
;
signal
i2c_addr
:
std_logic_vector
(
6
downto
0
);
signal
led_i2c_err
:
std_logic
;
signal
led_i2c
:
std_logic
;
signal
led_i2c_clkdiv
:
unsigned
(
18
downto
0
);
signal
led_i2c_cnt
:
unsigned
(
2
downto
0
);
signal
led_i2c_blink
:
std_logic
;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for
96
ms power-on reset
-- Configure reset generator for
100
ms power-on reset
cmp_reset_gen
:
reset_gen
generic
map
(
...
...
@@ -389,7 +433,7 @@ begin
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_i
=>
'0'
,
rst_i
=>
rst_fr_reg
,
rst_n_o
=>
rst_n
);
...
...
@@ -410,19 +454,20 @@ begin
rst_n_i
=>
rst_n
,
-- I2C lines
sda_en_o
=>
sda_oe_o
,
sda_i
=>
sda_i
,
sda_o
=>
sda_o
,
scl_en_o
=>
scl_oe_o
,
scl_i
=>
scl_i
,
scl_o
=>
scl_o
,
scl_en_o
=>
scl_oe_o
,
sda_i
=>
sda_i
,
sda_o
=>
sda_o
,
sda_en_o
=>
sda_oe_o
,
-- I2C address and status
i2c_addr_i
=>
i2c_addr
,
-- TIP and ERR outputs
tip_o
=>
i2c_tip
,
err_o
=>
i2c_err
,
err_p_o
=>
i2c_err_p
,
wdto_p_o
=>
i2c_wdto_p
,
-- Wishbone master signals
wbm_stb_o
=>
xbar_slave_in
(
0
)
.
stb
,
...
...
@@ -448,14 +493,14 @@ begin
led_i2c_clkdiv
<=
(
others
=>
'0'
);
led_i2c_cnt
<=
(
others
=>
'0'
);
led_i2c
<=
'0'
;
blink_state
<=
'0'
;
led_i2c_blink
<=
'0'
;
else
case
blink_state
is
case
led_i2c_blink
is
when
'0'
=>
led_i2c
<=
'0'
;
if
(
i2c_tip
=
'1'
)
then
blink_state
<=
'1'
;
led_i2c_blink
<=
'1'
;
end
if
;
when
'1'
=>
...
...
@@ -466,12 +511,12 @@ begin
led_i2c
<=
not
led_i2c
;
if
(
led_i2c_cnt
=
7
)
then
led_i2c_cnt
<=
(
others
=>
'0'
);
blink_state
<=
'0'
;
led_i2c_blink
<=
'0'
;
end
if
;
end
if
;
when
others
=>
blink_state
<=
'0'
;
led_i2c_blink
<=
'0'
;
end
case
;
end
if
;
...
...
@@ -479,19 +524,33 @@ begin
end
process
p_i2c_blink
;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- of the front module. The I2C error
LED
signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led
:
process
(
clk20_vcxo_i
)
is
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
i2c_err_led
<=
'0'
;
elsif
(
i2c_err
=
'1'
)
then
i2c_err_led
<=
'1'
;
led_i2c_err
<=
'0'
;
elsif
(
i2c_err
_p
=
'1'
)
then
led_i2c_err
<=
'1'
;
end
if
;
end
if
;
end
process
p_i2c_err_led
;
-- Register for the WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit
:
process
(
clk20_vcxo_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
wdto_bit
<=
'0'
;
elsif
(
i2c_wdto_p
=
'1'
)
then
wdto_bit
<=
'1'
;
elsif
(
wdto_bit_rst_ld
=
'1'
)
and
(
wdto_bit_rst
=
'1'
)
then
wdto_bit
<=
'0'
;
end
if
;
end
if
;
end
process
p_sr_wdto_bit
;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
...
...
@@ -518,38 +577,71 @@ begin
--============================================================================
-- Converter board registers
--============================================================================
-- set unused wishbone outputs
xbar_master_in
(
c_slv_conv_regs
)
.
int
<=
'0'
;
xbar_master_in
(
c_slv_conv_regs
)
.
rty
<=
'0'
;
xbar_master_in
(
c_slv_conv_regs
)
.
err
<=
'0'
;
-- set SWITCH and RTM fields
-- Set SWITCH and RTM fields
switches_n
<=
ttl_switch_n_i
&
extra_switch_n_i
(
7
downto
1
);
rtm_lines
<=
rtmp
&
rtmm
;
--
and
instantiate the component
--
Then,
instantiate the component
cmp_conv_regs
:
conv_regs
port
map
(
rst_n_i
=>
rst_n
,
clk_sys_i
=>
clk20_vcxo_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
stall
,
conv_regs_id_bits_o
=>
open
,
conv_regs_sr_fwvers_i
=>
c_fwvers
,
conv_regs_sr_switches_i
=>
switches_n
,
conv_regs_sr_rtm_i
=>
rtm_lines
,
conv_regs_cr_rst_unlock_o
=>
open
,
conv_regs_cr_rst_o
=>
open
rst_n_i
=>
rst_n
,
clk_sys_i
=>
clk20_vcxo_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
stall
,
reg_id_bits_i
=>
c_board_id
,
reg_sr_fwvers_i
=>
c_fwvers
,
reg_sr_switches_i
=>
switches_n
,
reg_sr_rtm_i
=>
rtm_lines
,
reg_sr_i2c_wdto_o
=>
wdto_bit_rst
,
reg_sr_i2c_wdto_i
=>
wdto_bit
,
reg_sr_i2c_wdto_load_o
=>
wdto_bit_rst_ld
,
reg_cr_rst_unlock_o
=>
rst_unlock_bit
,
reg_cr_rst_unlock_i
=>
rst_unlock
,
reg_cr_rst_unlock_load_o
=>
rst_unlock_bit_ld
,
reg_cr_rst_o
=>
rst_bit
,
reg_cr_rst_i
=>
rst_fr_reg
,
reg_cr_rst_load_o
=>
rst_bit_ld
);
-- Implement the RST_UNLOCK bit
p_rst_unlock
:
process
(
clk20_vcxo_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
rst_unlock
<=
'0'
;
elsif
(
rst_unlock_bit_ld
=
'1'
)
then
if
(
rst_unlock_bit
=
'1'
)
then
rst_unlock
<=
'1'
;
else
rst_unlock
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
p_rst_unlock
;
-- Implement the reset bit register
-- The register can only be set when the RST_UNLOCK bit is '1'.
p_rst_fr_reg
:
process
(
clk20_vcxo_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
rst_fr_reg
<=
'0'
;
elsif
(
rst_bit_ld
=
'1'
)
and
(
rst_bit
=
'1'
)
and
(
rst_unlock
=
'1'
)
then
rst_fr_reg
<=
'1'
;
else
rst_fr_reg
<=
'0'
;
end
if
;
end
if
;
end
process
p_rst_fr_reg
;
--============================================================================
-- Output enable logic
--============================================================================
...
...
@@ -593,6 +685,9 @@ begin
-- And now the OR gate at the inputs of the pulse generator blocks
trig_a
<=
trig_ttl_a
or
trig_blo_a
;
-----------------------------------------------------------------------------
-- Generate pulse repetition logic
-----------------------------------------------------------------------------
gen_ttl_pulse_generators
:
for
i
in
1
to
g_nr_ttl_chan
generate
-- First, resync the trigger signal into clk20_vcxo_i domain
cmp_sync_ffs
:
gc_sync_ffs
...
...
@@ -627,38 +722,37 @@ begin
-- Output pulse generators
cmp_ttl_pulse_gen
:
ctb_pulse_gen
generic
map
(
g_pwidth
=>
24
,
g_gf_len
=>
4
)
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_n_i
=>
rst_n
,
en_i
=>
'1'
,
gf_en_n_i
=>
extra_switch_n_i
(
1
),
trig_
i
=>
trig_a
(
i
),
pulse_o
=>
pulse_outp
uts
(
i
)
trig_
a_i
=>
trig_a
(
i
),
pulse_o
=>
pulse_outp
(
i
)
);
-- Pulse outputs assignment
fpga_out_ttl_o
<=
pulse_outp
uts
when
(
ttl_switch_n_i
=
'0'
)
else
not
pulse_outp
uts
;
fpga_trig_blo_o
<=
pulse_outp
uts
;
fpga_out_ttl_o
<=
pulse_outp
when
(
ttl_switch_n_i
=
'0'
)
else
not
pulse_outp
;
fpga_trig_blo_o
<=
pulse_outp
;
-- Process to flash pulse LED
on pulse reception
-- Process to flash pulse LED
when a pulse is output
-- LED flash length: 26 ms
p_pulse_led
:
process
(
clk20_vcxo_i
,
rst_n
)
is
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
pulse_led_cnt
(
i
)
<=
(
others
=>
'0'
);
pulse_leds
(
i
)
<=
'0'
;
pulse_outp_d0
(
i
)
<=
'0'
;
pulse_outp_r_edge_p
(
i
)
<=
'0'
;
pulse_led_cnt
(
i
)
<=
(
others
=>
'0'
);
pulse_leds
(
i
)
<=
'0'
;
else
pulse_outp_d0
(
i
)
<=
pulse_outp
(
i
);
pulse_outp_r_edge_p
(
i
)
<=
pulse_outp
(
i
)
and
(
not
pulse_outp_d0
(
i
));
case
pulse_leds
(
i
)
is
when
'0'
=>
if
(
trig_synced_edge
(
i
)
=
'1'
)
then
if
(
pulse_outp_r_edge_p
(
i
)
=
'1'
)
then
pulse_leds
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
...
...
@@ -673,6 +767,7 @@ begin
end
if
;
end
process
;
end
generate
gen_ttl_pulse_generators
;
-----------------------------------------------------------------------------
-- Pulse status LED output assignments
pulse_front_led_n_o
<=
(
not
pulse_leds
)
when
(
ttl_oe
=
'1'
)
else
...
...
@@ -688,10 +783,6 @@ begin
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in
(
c_slv_multiboot
)
.
int
<=
'0'
;
xbar_master_in
(
c_slv_multiboot
)
.
rty
<=
'0'
;
xbar_master_in
(
c_slv_multiboot
)
.
err
<=
'0'
;
cmp_multiboot
:
wb_xil_multiboot
port
map
(
...
...
@@ -734,7 +825,7 @@ begin
-- I2C
bicolor_led_state
(
13
downto
12
)
<=
c_LED_GREEN
when
(
led_i2c
=
'1'
)
else
c_LED_RED
when
(
i2c_err_led
=
'1'
)
else
c_LED_RED
when
(
led_i2c_err
=
'1'
)
else
c_LED_OFF
;
-- State of TTL/TTL_N switch
...
...
@@ -816,3 +907,6 @@ begin
fpga_sfp_tx_disable_o
<=
'Z'
;
end
behav
;
--==============================================================================
-- architecture end
--==============================================================================
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