Maximum pulse repetition frequency for blocking channels
The thermal properties of the BSH103 power MOSFET and their limiting values, are directly responsible for the achievable repetition frequency on the CONV-TTL-BLO. This has been discussed in depth as part of the blocking output circuit protection work.
In V3 boards and above, current limitation and pulse width-liming trigger circuit (maximum 8us) have been implemented to provide more adequate hardware protection.
However, the FPGA gateware will still be responsible for implementing ceilings on frequency repetition and fixed pulse width values.
For this ceilings to be chosen a direct experimental approach will be taken, informed by:
- MOSFET datasheet parameters.
- Methods and calculations described in an application note from the manufacturer.
- Measurements of the new V3 board prototypes (note 1) performance.
Aim of stress tests
Two modes of operation are foreseen for the new version of the CONV-TTL-BLO board. The aim of these tests will be slightly different depending on the mode of operation:
-
Continuous mode: Pulses in this mode are 1.2us long and can be
repeated continuously, provided their rate at the input is below the
stated maximum frequency for the continuous mode. For higher input
rates, pulses will be missed on the output and a flag will be
raised.
> Aim of tests: Identify maximum pulse frequency supported by the blocking output stage for continuous operation. -
Fast mode: The CONV-TTL-BLO board can support higher frequencies
than the maximum defined in the continuous mode, provided it is for
a limited amount of time. This mode of operation is also known as
burst mode.
> Identify the maximum repetition frequency that can be achieved and how long before this frequency can cause irreversible damage to the board.
The outcome of these tests can take a number of forms:
- The amount of time the board can sustain maximum rate of repetition, without being damaged.
- The number of pulses that can be repeated at a given rate without causing damage to the board.
- A target average frequency over a time period.
- A relationship between repetition frequencies and the time for which the board can sustain it safely.
Minimal pulse definition in the fast repetition mode:
- Pulse width: It shall be specified as 1.2us in the continuous mode and 250ns for the fast mode. The short 250ns pulse is long enough to match exisisting CERN pulse repeaters (Fast versions), and short enough to cause as little temperature rise in the power MOSFET as manageable.
-
Maximum allowable frequency: This is equivalent to the maximum
duty cycle allowed for 250ns pulses. An initial maximum 12.5% duty
cycle will be assumed. This corresponds to maximum 500kHz pulses.
> This Duty cycle might be increased during further tests to 50% corresponding to 2MHz frequency to see how much it impacts on transistor life.
Test procedure and requirements
The diagram below summarises the test procedure.
Diagram describing the test system components and the flow of control
and output data.
Hardware
- CONV-TTL-BLO V3 and RTM (Rear Transition Module) board plugged on VME64x ELMA crate and reachable via telnet.
- Oscilloscope to check for pulse shape one channel at a time.
- Computer on same network as ELMA crate and running the necessary software (Python) scripts.
- Lemo cables and appropriate termination to be used to connect the different ports.
Gateware & Software
- The on-board FPGA will be programmed with the *
Pulsetest
bitsream, a special gateware release for long-term testing. It
provides the user with the possibility of setting pulse repetition
parameters, by writing into a set of registers. Performance of the
board can also be read from another set of registers. Some of the
functionality is to:
- Set pulse width, repetition frequency and delay.
- Read Input counters.
- Read Output counters.
- Software script to write into board registers and set the output for a particular channel to the desired parameters. The program will also read relevant channel counters and output these as log files at the end of tests.
Procedure:
- In hardware:
In the Elma crate, plug in one CONV-TTL-BLO Front module board and one RTM module.
There are six available channels on the board with equal performance. Two channels will be used, as shown in Figure 1, above:- A Channel under tests (CUD): This channel output circuit will be tested for performance with incrementally increasing repetition frequency, until it is irreversibly damaged. The point at which this occurs needs to be recorded and used as a time to failure figure. If the same test is repeated on multiple channels than a mean time to failure figure may also be calculated.
- A monitoring channel (MC): This can be any one of the other 5 remaining channels that are left on the board. The blocking output pulse of the CUT is fed to the blocking input of the MC. This channel will be used for counting pulses at its input and not for repetition.
- In software:
- Set pulse width to 250ns.
- Each test will run a chosen repetition frequency, from list, Eg: 1kHz, 5kHz, 10kHz, 50kHz, 100kHz, 150kHz, 200kHz, 300kHz, 400kHz, 500kHz.
- The test must be stopped when the blocking output fails. This is
detected when:
- When the blocking output pulse disappears from the Oscilloscope screen (Or when the damage to blocking output is seen... or smelt). The test must be stopped.
- The Python scripts should be able to detect this by comparing the read out from the MC channel counter, with that of the CUT. If the MC count is smaller than the CUT count, or the MC count stops incrementing, then the blocking output must be damaged.
- The outcome of tests will be recorded on a log sheet.
Note 1: As a minor bug has been identified in V3 boards, which has been described in issue #1404. The V3 prototypes used in these stress tests will have the missing resistor manually added, before being permanently added in V4 boards.