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Conv TTL Blocking - Testing
Commit 097e9f8e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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fm-doc: Added support for PTS regs and other changes to HDL guide

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fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
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......@@ -5,11 +5,15 @@
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{longtable}
\usepackage{color}
\usepackage[toc,page]{appendix}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Header and footer customization
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
......@@ -156,6 +160,8 @@ on a computer writes and reads registers implemented in the PTS HDL running on t
on-board FPGA. As described in the following sections, writing and reading to specific registers
in the HDL result in the running of the steps necessary to test a CONV-TTL-BLO device under test.
For a complete reference of the registers accessible in the PTS HDL, see Appendix~\ref{app:memmap}.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/hdl-bd}}
\caption{\label{fig:hdl-bd} HDL block diagram}
......@@ -175,14 +181,14 @@ in the HDL result in the running of the steps necessary to test a CONV-TTL-BLO d
The logic for this test is shown in Figure~\ref{fig:dac-test}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/dac-test}}
\centerline{\includegraphics[width=1.1\textwidth]{fig/dac-test}}
\caption{\label{fig:dac-test} DAC and clocks test logic}
\end{figure}
The way this test runs can be summarized as follows:
\begin{itemize}
\item the PTS software controls (via the SPI master) the two DACs (IC17, IC18) on-board the
\item the PTS software controls (via OpenCores SPI master modules~\cite{spi}) the two DACs on the
CONV-TTL-BLO
\item the DACs control the tuning inputs of the on-board oscillators, which are input to
the FPGA
......@@ -196,10 +202,12 @@ The way this test runs can be summarized as follows:
%--------------------------------------------------------------------------------------
% SUBSEC: Test 02
%--------------------------------------------------------------------------------------
\pagebreak
\subsection{Test 02 -- Front panel LEDs test}
The PTS software sets bits SLDEN and PLDEN in the PTS CSR, which starts a sequence
counter; each pulse or status LED is turned on based on the value of this counter.
The PTS software sets the CHLEDT and STLEDT bits in the PTS control and status register
(CSR -- see Appendix~\ref{app:pts-regs-csr}), which starts a sequence counter inside the
HDL. Each pulse or status LED is turned on based on the value of this counter.
%--------------------------------------------------------------------------------------
% SUBSEC: Test 02
......
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