hdl: Added the HDL files to this repo, but didn't test yet

1f2dd42c · Theodor-Adrian Stana · 88464154 · 1f2dd42c · dc4bfb25 · 3fbaa93c
Commit 1f2dd42c authored Nov 14, 2014 by Theodor-Adrian Stana
17 changed files
--- a/.gitmodules
+++ b/.gitmodules
 [submodule "rtm/hdl/ip_cores/general-cores"]
 	path = rtm/hdl/ip_cores/general-cores
 	url = git@ohwr.org:hdl-core-lib/general-cores.git
+[submodule "fm/hdl/ip_cores/conv-common-gw"]
+	path = fm/hdl/ip_cores/conv-common-gw
+	url = git@ohwr.org:level-conversion/conv-common-gw.git
+[submodule "fm/hdl/ip_cores/wr-cores"]
+	path = fm/hdl/ip_cores/wr-cores
+	url = git@ohwr.org:hdl-core-lib/wr-cores.git
--- a/conv-common-gw @ dc4bfb25
+++ b/conv-common-gw @ dc4bfb25
+Subproject commit dc4bfb2545abd9c8cc3851a33839804afd470116
--- a/wr-cores @ 3fbaa93c
+++ b/wr-cores @ 3fbaa93c
+Subproject commit 3fbaa93c1094e98c7f0f841251825462f7ee71ce
--- a/fm/hdl/modules/Manifest.py
+++ b/fm/hdl/modules/Manifest.py
+files = [
+      "pts_regs.vhd",
+      "pulse_cnt_wb.vhd",
+      "incr_counter.vhd",
+      "clk_info_wb_slave.vhd",
+      "pulse_gen_gp.vhd"
+    ]
--- a/fm/hdl/modules/clk_info_wb_slave.vhd
+++ b/fm/hdl/modules/clk_info_wb_slave.vhd
--- a/fm/hdl/modules/incr_counter.vhd
+++ b/fm/hdl/modules/incr_counter.vhd
+--_________________________________________________________________________________________________
+--                                                                                                |
+--                                           |TDC core|                                           |
+--                                                                                                |
+--                                         CERN,BE/CO-HT                                          |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+--                                                                                                |
+--                                         incr_counter                                           |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+-- File         incr_counter.vhd                                                                  |
+--                                                                                                |
+-- Description  Stop counter. Configurable counter_top_i and width.                               |
+--				Current count value and done signal available.                                    |
+--				Done signal asserted simultaneous to value = counter_top_i.                       |
+--				Needs a rst_i to restart.                                                         |
+--                                                                                                |
+--                                                                                                |
+-- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
+--              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+-- Date         04/2012                                                                           |
+-- Version      v0.11                                                                             |
+-- Depends on                                                                                     |
+--                                                                                                |
+----------------                                                                                  |
+-- Last changes                                                                                   |
+--     05/2011  v0.1  GP  First version                                                           |
+--     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
+--                              ------------------------------------                              |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
+-- version 2.1 of the License, or (at your option) any later version.                             |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
+-- See the GNU Lesser General Public License for more details.                                    |
+-- You should have received a copy of the GNU Lesser General Public License along with this       |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
+---------------------------------------------------------------------------------------------------
+
+
+
+--=================================================================================================
+--                                       Libraries & Packages
+--=================================================================================================
+
+-- Standard library
+library IEEE;
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions
+
+
+--=================================================================================================
+--                            Entity declaration for incr_counter
+--=================================================================================================
+
+entity incr_counter is
+  generic
+    (width             : integer := 32); -- default size
+  port
+  -- INPUTS
+     -- Signals from the clk_rst_manager
+    (clk_i             : in std_logic;
+     rst_i             : in std_logic;
+
+     -- Signals from any unit
+     counter_top_i     : in std_logic_vector(width-1 downto 0); -- max value to be counted; when reached
+                                                                -- counter stays at it, until a reset
+     counter_incr_en_i : in std_logic;   -- enables counting
+
+  -- OUTPUTS
+     -- Signals to any unit
+     counter_o         : out std_logic_vector(width-1 downto 0);
+     counter_is_full_o : out std_logic); -- counter reahed counter_top_i value
+
+  end incr_counter;
+
+--=================================================================================================
+--                                    architecture declaration
+--=================================================================================================
+architecture rtl of incr_counter is
+
+  constant zeroes : unsigned(width-1 downto 0) := (others=>'0');
+  signal counter  : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
+
+
+--=================================================================================================
+--                                       architecture begin
+--=================================================================================================
+begin
+	
+  incr_counting: process (clk_i)
+  begin
+    if rising_edge (clk_i) then
+      if rst_i = '1' then
+        counter_is_full_o   <= '0';
+        counter             <= zeroes;
+
+      elsif counter = unsigned (counter_top_i) then
+        counter_is_full_o   <= '1';
+        counter             <= unsigned (counter_top_i);
+
+      elsif counter_incr_en_i ='1' then
+
+        if counter = unsigned(counter_top_i) - "1" then
+          counter_is_full_o <= '1';
+          counter           <= counter + "1";
+        else
+          counter_is_full_o <= '0';
+          counter           <= counter + "1";
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+  counter_o                 <= std_logic_vector(counter);
+
+
+end architecture rtl;
+--=================================================================================================
+--                                        architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                      E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
--- a/fm/hdl/modules/pts_regs.vhd
+++ b/fm/hdl/modules/pts_regs.vhd
--- a/fm/hdl/modules/pts_regs.wb
+++ b/fm/hdl/modules/pts_regs.wb
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- CONV-TTL-BLO PTS registers wbgen2 description file
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- version: 1.0
+--
+-- description:
+--    This file contains the register description for the converter board
+--    registers and is to be used as input to the wbgen2 tool for generating
+--    an appropriate VHDL file.
+--
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    11-11-2014   Theodor Stana     Added GPL header
+--==============================================================================
+-- TODO: -
+--==============================================================================
+
+peripheral {
+  name        = "PTS control and status registers";
+  description = "Registers of the PTS firmware";
+  hdl_entity  = "pts_regs";
+  prefix      = "pts";
+
+  -- Board ID register
+  reg {
+    name = "BIDR";
+    description = "Board ID Register";
+    prefix = "bidr";
+    reset_value = "g_board_id";
+    field {
+      name = "ID register bits";
+      reset_value = "g_board_id";
+      type = SLV;
+      size = 32;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+  };
+
+  -- Control & Status Register
+  reg {
+    name = "CSR";
+    description = "Control and Status Register";
+    prefix = "csr";
+
+    field {
+      name = "Front pulse LED enable";
+      prefix = "fledt";
+      description = "1 -- Enable front panel LED sequencing \ 0 -- No effect";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Rear pulse LED enable";
+      prefix = "rledt";
+      description = "1 -- Enable rear panel LED sequencing \ 0 -- No effect";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Status LED enable";
+      prefix = "stledt";
+      description = "1 -- Enable front panel bicolor LED sequencing \ 0 -- No effect";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "TTL test enable";
+      prefix = "ttlpt";
+      description = "1 -- Enable pulse generation from CH1 \ 0 -- No effect";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Blocking test enable";
+      prefix = "blopt";
+      description = "1 -- Enable blocking pulse generation \ 0 -- No effect";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Reset unlock bit";
+      description = "1 -- Reset bit unlocked \ 0 -- Reset bit locked";
+      prefix = "rst_unlock";
+      type = BIT;
+      align = 14;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load = LOAD_EXT;
+    };
+    field {
+      name = "Reset bit";
+      description = "1 -- initiate logic reset \ 0 -- no reset";
+      prefix = "rst";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+
+    field {
+      name = "switches";
+      prefix = "switch";
+      type = SLV;
+      align = 16;
+      size = 8;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "RTM";
+      prefix = "rtm";
+      type = SLV;
+      align = 24;
+      size = 6;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "I2C communication error";
+      description = "1 -- attempted to address non-existing address \
+                     0 -- idle \
+                     This bit can be cleared by writing a '1' to it";
+      prefix = "i2c_err";
+      type = BIT;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load = LOAD_EXT;
+    };
+
+    field {
+      name = "I2C communication watchdog timeout error";
+      description = "1 -- timeout occured \
+                     0 -- no timeout \
+                     This bit can be cleared by writing a '1' to it";
+      prefix     = "i2c_wdto";
+      type       = BIT;
+      size       = 1;
+      access_dev = READ_WRITE;
+      access_bus = READ_WRITE;
+      load       = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "LSR";
+    description = "Line Status Register";
+    prefix = "lsr";
+    field {
+      name = "Front panel channel input state";
+      description = "Line state at board input\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "front";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Front panel INV-TTL input state";
+      description = "Line state at board input\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "frontinv";
+      type = SLV;
+      size = 4;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Rear panel input state";
+      description = "Line state at board input\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "rear";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+  };
+
+};
--- a/fm/hdl/modules/pulse_cnt_wb.vhd
+++ b/fm/hdl/modules/pulse_cnt_wb.vhd
--- a/fm/hdl/modules/pulse_cnt_wb.wb
+++ b/fm/hdl/modules/pulse_cnt_wb.wb
+peripheral {
+  name = "Pulse counter registers";
+  description = "Registers containing the values for input and output generated pulses";
+  hdl_entity = "pulse_cnt_wb";
+  prefix     = "pulse_cnt";
+
+  reg {
+    name = "TTLCH1OCR";
+    prefix = "ttlch1o";
+    description = "TTL CH1 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH1ICR";
+    prefix = "ttlch1i";
+    description = "TTL CH1 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH2OCR";
+    prefix = "ttlch2o";
+    description = "TTL CH2 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH2ICR";
+    prefix = "ttlch2i";
+    description = "TTL CH2 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH3OCR";
+    prefix = "ttlch3o";
+    description = "TTL CH3 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH3ICR";
+    prefix = "ttlch3i";
+    description = "TTL CH3 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH4OCR";
+    prefix = "ttlch4o";
+    description = "TTL CH4 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH4ICR";
+    prefix = "ttlch4i";
+    description = "TTL CH4 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH5OCR";
+    prefix = "ttlch5o";
+    description = "TTL CH5 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH5ICR";
+    prefix = "ttlch5i";
+    description = "TTL CH5 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH6OCR";
+    prefix = "ttlch6o";
+    description = "TTL CH6 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "TTLCH6ICR";
+    prefix = "ttlch6i";
+    description = "TTL CH6 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "INVTTLCHAOCR";
+    prefix = "invttlchao";
+    description = "INV-TTL CHA output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "INVTTLCHAICR";
+    prefix = "invttlchai";
+    description = "INV-TTL CHA input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "INVTTLCHBOCR";
+    prefix = "invttlchbo";
+    description = "INV-TTL CHB output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "INVTTLCHBICR";
+    prefix = "invttlchbi";
+    description = "INV-TTL CHB input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "INVTTLCHCOCR";
+    prefix = "invttlchco";
+    description = "INV-TTL CHC output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "INVTTLCHCICR";
+    prefix = "invttlchci";
+    description = "INV-TTL CHC input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "INVTTLCHDOCR";
+    prefix = "invttlchdo";
+    description = "INV-TTL CHD output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "INVTTLCHDICR";
+    prefix = "invttlchdi";
+    description = "INV-TTL CHD input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH1OCR";
+    prefix = "rearch1o";
+    description = "Rear CH1 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH1ICR";
+    prefix = "rearch1i";
+    description = "Rear CH1 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH2OCR";
+    prefix = "rearch2o";
+    description = "Rear CH2 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH2ICR";
+    prefix = "rearch2i";
+    description = "Rear CH2 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH3OCR";
+    prefix = "rearch3o";
+    description = "Rear CH3 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH3ICR";
+    prefix = "rearch3i";
+    description = "Rear CH3 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH4OCR";
+    prefix = "rearch4o";
+    description = "Rear CH4 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "REARCH4ICR";
+    prefix = "rearch4i";
+    description = "Rear CH4 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "REARCH5OCR";
+    prefix = "rearch5o";
+    description = "Rear CH5 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "REARCH5ICR";
+    prefix = "rearch5i";
+    description = "Rear CH5 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH6OCR";
+    prefix = "rearch6o";
+    description = "Rear CH6 output counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+   };
+  };
+
+  reg {
+    name = "REARCH6ICR";
+    prefix = "rearch6i";
+    description = "Rear CH6 input counter register";
+    field {
+      name = "Pulse counter value";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+      load = LOAD_EXT;
+    };
+  };
+
+};
--- a/fm/hdl/modules/pulse_gen_gp.vhd
+++ b/fm/hdl/modules/pulse_gen_gp.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- General-purpose pulse generator
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 2.0
+--
+-- description:
+--
+--   This module generates pulses with configurable frequency, width and delay.
+--
+--   In order to generate pulses, the module must be enabled via the en_i port.
+--   Once en_i is high, pulses are generated at the frequency specified via
+--   freq_i, with the width specified via pwidth_i.
+--
+--   An optional delay can be added before the start of the pulse, via the delay_i
+--   port.
+--
+--   Note that this delay can be set only before the module is enabled.
+--
+--   freq_i, pwidth_i and delay_i are given in clk_i cycles.
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--    2013 08-15   Theodor Stana     t.stana@cern.ch     v2.0, delay, pwidth, freq
+--                                                       now controllable via
+--                                                       inputs (regs, etc.)
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity pulse_gen_gp is
+  port
+  (
+    -- Input clock and active-low reset
+    clk_i    : in  std_logic;
+    rst_n_i  : in  std_logic;
+
+    -- Active high enable signal
+    en_i     : in  std_logic;
+    
+    -- Delay, pulse width and frequency inputs, in number of clk_i cycles
+    delay_i  : in  std_logic_vector(31 downto 0);
+    pwidth_i : in  std_logic_vector(31 downto 0);
+    freq_i   : in  std_logic_vector(31 downto 0);
+
+    -- Output pulse signal
+    pulse_o  : out std_logic
+  );
+end entity pulse_gen_gp;
+
+
+architecture behav of pulse_gen_gp is
+
+  --============================================================================
+  -- Function and procedure declarations
+  --============================================================================
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal delay_int  : unsigned(31 downto 0);
+  signal pwidth_int : unsigned(31 downto 0);
+  signal freq_int   : unsigned(31 downto 0);
+
+  signal pulse_cnt  : unsigned(31 downto 0);
+  signal delay_cnt  : unsigned(31 downto 0);
+
+  signal delay_en   : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- Convert std_logic_vector inputs to unsigned
+  --============================================================================
+  delay_int  <= unsigned(delay_i);
+  pwidth_int <= unsigned(pwidth_i);
+  freq_int   <= unsigned(freq_i);
+
+  --============================================================================
+  -- Delay logic
+  --============================================================================
+  p_delay: process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') or (en_i = '0') then
+        delay_en  <= '1';
+        delay_cnt <= (others => '0');
+      else
+        if (delay_int = (delay_int'range => '0')) then
+          delay_en <= '0';
+        elsif (delay_en = '1') then
+          delay_cnt <= delay_cnt + 1;
+          if (delay_cnt = delay_int) then
+            delay_en  <= '0';
+            delay_cnt <= (others => '0');
+          end if;
+        end if;
+      end if;
+    end if;
+  end process p_delay;
+
+  --============================================================================
+  -- Pulse generation logic
+  --============================================================================
+  p_gen_pulse: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') or (en_i = '0') then
+        pulse_cnt <= (others => '0');
+        pulse_o   <= '0';
+      elsif (delay_en = '0') then
+        pulse_cnt <= pulse_cnt + 1;
+        pulse_o   <= '0';
+        if (pulse_cnt < pwidth_int) then
+          pulse_o <= '1';
+        elsif (pulse_cnt = freq_int-1) then
+          pulse_cnt <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process p_gen_pulse;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/fm/hdl/syn/Makefile
+++ b/fm/hdl/syn/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := pts.xise
+ISE_CRAP := *.b pts_summary.html *.tcl pts.bld pts.cmd_log *.drc pts.lso *.ncd pts.ngc pts.ngd pts.ngr pts.pad pts.par pts.pcf pts.prj pts.ptwx pts.stx pts.syr pts.twr pts.twx pts.gise pts.unroutes pts.ut pts.xpi pts.xst pts_bitgen.xwbt pts_envsettings.html pts_guide.ncd pts_map.map pts_map.mrp pts_map.ncd pts_map.ngm pts_map.xrpt pts_ngdbuild.xrpt pts_pad.csv pts_pad.txt pts_par.xrpt pts_summary.xml pts_usage.xml pts_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
+		xtclsh run.tcl
+
+
+#target for cleaing all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+    
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
--- a/fm/hdl/syn/Manifest.py
+++ b/fm/hdl/syn/Manifest.py
+target = "xilinx"
+action = "synthesis"
+syn_device  = "xc6slx45t"
+syn_grade   = "-3"
+syn_package = "fgg484"
+syn_top     = "pts"
+syn_project = "pts.xise"
+
+modules = {
+    "local" : [
+      "../top"
+      ]
+    }
--- a/fm/hdl/syn/pts.xise
+++ b/fm/hdl/syn/pts.xise
--- a/fm/hdl/top/Manifest.py
+++ b/fm/hdl/top/Manifest.py
+files = [
+      "pts.ucf",
+      "pts.vhd"
+    ]
+
+modules = {
+  "local" : [
+    "../modules",
+    "../ip_cores/conv-common-gw",
+    "../ip_cores/wr-cores"
+    ],
+  }
+
--- a/fm/hdl/top/pts.ucf
+++ b/fm/hdl/top/pts.ucf
--- a/fm/hdl/top/pts.vhd
+++ b/fm/hdl/top/pts.vhd