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Conv TTL Blocking - Testing
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Conv TTL Blocking - Testing
Commits
9bc70502
Commit
9bc70502
authored
Dec 12, 2014
by
Theodor-Adrian Stana
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fm-doc: Some corrections and rewording in the HDL guide
parent
62b0b0d2
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59 deletions
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-59
clk_info.tex
fm/doc/hdlg/clk_info.tex
+3
-3
dac-test.svg
fm/doc/hdlg/fig/dac-test.svg
+26
-20
ttl-test.svg
fm/doc/hdlg/fig/ttl-test.svg
+15
-13
hdlg-pts-conv-ttl-blo.tex
fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
+35
-22
pts_regs.tex
fm/doc/hdlg/pts_regs.tex
+1
-1
No files found.
fm/doc/hdlg/clk_info.tex
View file @
9bc70502
...
...
@@ -27,7 +27,7 @@ Base address (20-MHz counter): 0x120
\end{longtable}
}
\subsubsection
{
CNTFULLR
}
\subsubsection
{
CNTFULLR
-- Counter full register
}
\label
{
app:clk-info-cntfullr
}
\vspace
{
11pt
}
...
...
@@ -141,7 +141,7 @@ CNTVAL
\end{small}
\end{itemize}
\subsubsection
{
CNTRSTR
}
\subsubsection
{
CNTRSTR
-- Counter reset register
}
\label
{
app:clk-info-cntrstr
}
\vspace
{
11pt
}
...
...
@@ -180,7 +180,7 @@ CNTRST
\end{small}
\end{itemize}
\subsubsection
{
CNTENR
}
\subsubsection
{
CNTENR
-- Counter enable register
}
\label
{
app:clk-info-cntenr
}
\vspace
{
11pt
}
...
...
fm/doc/hdlg/fig/dac-test.svg
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9bc70502
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fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
View file @
9bc70502
...
...
@@ -2,7 +2,13 @@
% Document header
%==============================================================================
\documentclass
[a4paper,11pt]
{
article
}
\usepackage
[pdfborder= 0 0 0 1]
{
hyperref
}
\usepackage
[
colorlinks = true,
linkcolor = black,
citecolor = black,
urlcolor = blue,
]
{
hyperref
}
\usepackage
{
graphicx
}
\usepackage
{
multirow
}
\usepackage
{
longtable
}
...
...
@@ -77,6 +83,7 @@ work, see \\
\pdfbookmark
[1]
{
\contentsname
}{
toc
}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
...
...
@@ -101,7 +108,7 @@ work, see \\
\section
{
Introduction
}
\label
{
sec:intro
}
Production Test Suite (PTS) is the environment designed for running functionality tests
on boards at the manufacturing site right after production. It assures that boards comply
on boards at the manufacturing site
,
right after production. It assures that boards comply
with a minimum set of quality rules in terms of soldering, mounting and PCB fabrication
process.
...
...
@@ -130,7 +137,8 @@ the PTS gateware, which can be obtained by cloning the git repository for the PT
The PTS system (Figure~
\ref
{
fig:pts-sys
}
) is contained within a rack containing an ELMA
crate, the laptop with the PTS software installed on it and all other accessories necessary
for running tests. More information about the PTS system can be found in
\cite
{
pts-userguide
}
.
for running tests. More information about the PTS system can be found in the PTS user
guide~
\cite
{
pts-userguide
}
.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=.9\textwidth]
{
fig/pts-sys
}}
...
...
@@ -139,10 +147,10 @@ for running tests. More information about the PTS system can be found in \cite{p
\end{figure}
The ELMA crate within the PTS contains a system monitor (SysMon) board that monitors
voltage levels, temperatures and controls fan speeds for the crate fans. The
crate
voltage levels, temperatures and controls fan speeds for the crate fans. The
SysMon
can be accessed via Telnet to send commands to the VME boards inside the crate.
Using
these
commands, the CONV-TTL-BLO board can be accessed through the serial
Using
such
commands, the CONV-TTL-BLO board can be accessed through the serial
(I
$^
2
$
C) interface on the VME P1 connector. The PTS software on the PTS laptop connects
to the crate through Telnet and sends
\textit
{
readreg
}
and
\textit
{
writereg
}
commands to the crate; the commands are translated by the SysMon to I
$^
2
$
C transfers
...
...
@@ -160,7 +168,8 @@ on a computer writes and reads registers implemented in the PTS gateware running
on-board FPGA. As described in the following sections, writing and reading to specific registers
in the gateware result in the running of the steps necessary to test a CONV-TTL-BLO device under test.
For a complete reference of the registers accessible in the PTS gateware, see Appendix~
\ref
{
app:memmap
}
.
For a complete reference of the registers accessible in the PTS gateware, see the complete memory map
for the gateware in Appendix~
\ref
{
app:memmap
}
.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=1.1\textwidth]
{
fig/hdl-bd
}}
...
...
@@ -215,21 +224,23 @@ The logic for this test is shown in Figure~\ref{fig:ttl-test} and can be summari
\begin{itemize}
\item
the PTS software sets the TTLPT bit in the PTS control and status register (CSR -- see Appendix~
\ref
{
app:pts-regs-csr
}
)
\item
this enables
the
\textit
{
pulse
\_
gen
\_
gp
}
component on TTL CH1 to generate
\item
this enables
a general-purpose pulse generator
component on TTL CH1 to generate
1~
$
\mu
$
s pulses with a period of 500~ms
\item
the pulses are replicated through the channel daisy-chain~
\cite
{
pts-userguide
}
from
CH1 to
CH10
\item
CH2 through INV-TTL CH D (CH10 in VHDL) have
\textit
{
conv
\_
pulse
\_
gen
}
components~
\cite
{
conv-common-gw-ohwr
}
CH1 to
INV-TTL CH D
\item
CH2 through INV-TTL CH D (CH10 in VHDL) have
pulse generator
components~
\cite
{
conv-common-gw-ohwr
}
which generate 1~
$
\mu
$
s pulses when there is a pulse on the input
\item
each channel has one input and output pulse counter; each counter gets incremented when
there is a rising edge on the input or output
\item
the current values of these counters can be read by the PTS software from the pulse counter
registers (see Appendix~
\ref
{
app:pulse-cnt
}
)
\item
for the switch test
\begin{itemize}
\item
the user sets the switches as indicated in the CONV-TTL-BLO PTS User Guide~
\cite
{
pts-userguide
}
\item
the PTS software reads the CSR.SWITCH field (see Appendix~
\ref
{
app:pts-regs-csr
}
)
\end{itemize}
\end{itemize}
For the switch test:
\begin{itemize}
\item
the user sets the switches as indicated in the CONV-TTL-BLO PTS User Guide~
\cite
{
pts-userguide
}
\item
the PTS software reads the CSR.SWITCH field (see Appendix~
\ref
{
app:pts-regs-csr
}
) to
confirm proper switch setting
\end{itemize}
\begin{figure}
[h]
...
...
@@ -262,8 +273,9 @@ each channel generates a pulse 100~ms after the previous, with 600~ms period:
blocking inputs via the RTM Interface Tester
\cite
{
pts-hwguide
}
\item
each channel has one input and output pulse counter; each counter gets incremented when
there is a rising edge on the input or output
\item
the current values of these counters can be read by the PTS software from the pulse counter
(Section~
\ref
{
app:pulse-cnt
}
) registers
\item
the PTS software reads the pulse counter registers (Section~
\ref
{
app:pulse-cnt
}
) to check
that the number of pulses that are sent at outputs are received back at inputs, according
to the connection diagram on the RTM Interface Tester
\end{itemize}
\begin{figure}
[hbtp]
...
...
@@ -277,7 +289,7 @@ For testing the RTM detection lines and rear-panel LED lines (Figure~\ref{fig:rt
\item
this bit sets all rear LED lines
\item
the rear LED lines are looped back to the RTM detection lines through the RTM
Interface Tester~
\cite
{
pts-hwguide
}
\item
the PTS software reads the RTM field in the PTS CSR to check for correct value
\item
the PTS software reads the RTM field in the PTS CSR to check for
the
correct value
\end{itemize}
\begin{figure}
[h]
...
...
@@ -288,7 +300,7 @@ For testing the RTM detection lines and rear-panel LED lines (Figure~\ref{fig:rt
%--------------------------------------------------------------------------------------
% SUBSEC: Test 05
%--------------------------------------------------------------------------------------
\subsection
{
Test 05
}
\subsection
{
Test 05
-- Thermometer chip test
}
The PTS software interacts with the OpenCores one-wire master core~
\cite
{
onewire
}
to access the DS18B20U+ temperature chip for retrieving the unique board ID and the
...
...
@@ -297,19 +309,19 @@ temperature at the time the test is run.
%--------------------------------------------------------------------------------------
% SUBSEC: Test 06
%--------------------------------------------------------------------------------------
\subsection
{
Test 06
}
\subsection
{
Test 06
-- SFP EEPROM test
}
An OpenCores I
$^
2
$
C master component~
\cite
{
i2c-master
}
communicates to the SFP and retrieves
An OpenCores I
$^
2
$
C master component~
\cite
{
i2c-master
}
communicates to the SFP
connector
and retrieves
its internal identifier. The PTS software drives this communication by interacting with the
I
$^
2
$
C master and checks the SFP identifier for correct value.
%--------------------------------------------------------------------------------------
% SUBSEC: Test 07
%--------------------------------------------------------------------------------------
\subsection
{
Test 07
}
\subsection
{
Test 07
-- SPF link test
}
The PTS software communicates with MiniNIC and endpoint components~
\cite
{
wr-cores
}
to
initialize them and check whether the link goes up through
an
SFP loopback connector.
initialize them and check whether the link goes up through
the
SFP loopback connector.
%======================================================================================
% SEC: Folder structure
...
...
@@ -320,6 +332,7 @@ initialize them and check whether the link goes up through an SFP loopback conne
The folder structure is shown in Table~
\ref
{
tbl:fold-struct
}
.
\begin{table}
[h]
\rowcolors
{
2
}{
white
}{
gray!25
}
\caption
{
\label
{
tbl:fold-struct
}
Folder structure for the PTS gateware
}
\centerline
{
\begin{tabular}
{
l p
{
.7
\textwidth
}}
...
...
fm/doc/hdlg/pts_regs.tex
View file @
9bc70502
...
...
@@ -154,7 +154,7 @@ SWITCH
RTM
}
[
\emph
{
read-only
}
]: RTM detection lines
\\
1 - line activ
at
e
\\
0 - line inactive
1 - line active
\\
0 - line inactive
\end{small}
\item
\begin{small}
{
\bf
...
...
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