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C
Conv TTL Blocking - Testing
Commit b7322e85 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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sw-fm: Updated CSR bit names

parent 44b21c5d
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Showing with 46 additions and 33 deletions
fm/pts/python/leds.py
View file @ b7322e85
......@@ -76,7 +76,7 @@ def main(bus,tname,inf,log):
try:
# First phase of LED test, enable pulse LED sequencing
bus.vv_write(CSR, 1 << CSR_FRONT_LED_EN_OFS)
bus.vv_write(CSR, 1 << CSR_CHLEDT_OFS)
# The firmware should blink the LEDs, ask the operator for input
inp = raw_input("--> Are the channel LEDs blinking one by one? yes/no: ")
......@@ -92,7 +92,7 @@ def main(bus,tname,inf,log):
inp = raw_input('Please type "yes" or "no" to continue:')
# Second phase of LED test, enable status LED sequencing
bus.vv_write(CSR, 1 << CSR_STAT_LED_EN_OFS)
bus.vv_write(CSR, 1 << CSR_STLEDT_OFS)
# The firmware should blink the LEDs, ask the operator for input
inp = raw_input("--> Are the status LEDs blinking one by one? yes/no: ")
......@@ -114,3 +114,10 @@ def main(bus,tname,inf,log):
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
finally:
# Clean-up -- clear status and front LED test bits
val = bus.vv_read(CSR)
val &= ~((1 << CSR_CHLEDT_OFS) | (1 << CSR_STLEDT_OFS))
bus.vv_write(CSR, val)
fm/pts/python/ptsdefine.py
View file @ b7322e85
#===============================================================================
# CERN (BE-CO-HT)
# PTS memory map
# PTS definitions file
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
#
# date of creation: 2013-04-12
# date of creation: 2013-10-31
#
# version: 1.0
#
......@@ -34,11 +34,13 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2013-04-12 Theodor Stana t.stana@cern.ch File created
# 2014-10-31 Theodor Stana t.stana@cern.ch File created
#===============================================================================
# TODO: -
#===============================================================================
BOARD = "$BOARD"
# ELMA crate definitions
ELMAIP = "$ELMAIP"
ELMAPWD = "$ELMAPWD"
......@@ -49,49 +51,53 @@ BIDR = 0x000
BIDR_ARR = [ "TBLO", "T485" ]
# Registers used across all test programs
CSR = 0x004
CSR_FRONT_LED_EN_OFS = 0
CSR_REAR_LED_EN_OFS = 1
CSR_STAT_LED_EN_OFS = 2
CSR_TTL_EN_OFS = 3
CSR_REAR_EN_OFS = 4
CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15
CSR_SWITCHES_OFS = 16
CSR_RTM_OFS = 24
CSR_I2C_ERR_OFS = 30
CSR_I2C_WDTO_OFS = 31
# Control and Status Register
CSR = 0x004
CSR_CHLEDT_OFS = 0
CSR_STLEDT_OFS = 1
CSR_RLEDT_OFS = 2
CSR_TTLPT_OFS = 3
CSR_REARPT_OFS = 4
CSR_TSTCVCC_OFS = 5
CSR_TSTCMUXEN_OFS = 6
CSR_TSTCS0_OFS = 7
CSR_TSTCS1_OFS = 8
CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15
CSR_SWITCH_OFS = 16
CSR_RTM_OFS = 24
CSR_I2C_ERR_OFS = 30
CSR_I2C_WDTO_OFS = 31
# Line Status Register
LSR = 0x008
LSR_FRONT_OFS = 0
LSR_FRONTINV_OFS = 6
LSR_REAR_OFS = 10
LSR_REARFS_OFS = 26
# 1-Wire base address, used in therm_id.py
TEMP_1WIRE_BASE = 0x010
TEMP_1WIRE_BASE = 0x010
# DAC and clock info registers and offsets, used in dac_vcxo_pll.py
PLL_DAC_BASE = 0X020
VCXO_DAC_BASE = 0x080
PLL_DAC_BASE = 0X020
VCXO_DAC_BASE = 0x080
PLL_CLKINFO_BASE = 0x100
VCXO_CLKINFO_BASE = 0x120
CLKINFO_RST_OFS = 0x014
CLKINFO_ENABLE_OFS = 0x018
CLKINFO_VALUE_OFS = 0x010
PLL_CLKINFO_BASE = 0x100
VCXO_CLKINFO_BASE = 0x120
CLKINFO_RST_OFS = 0x014
CLKINFO_ENABLE_OFS = 0x018
CLKINFO_VALUE_OFS = 0x010
# SFP I2C master base address, used in sfp_eeprom.py
SFP_EEPROM_BASE = 0x140
SFP_EEPROM_BASE = 0x140
# SFP endpoint, miniNIC and buffer RAM base addresses and offsets,
# used in sfp_test.py
SFP_BASE = 0x200
SFP_ENDPOINT_OFS = 0x000
SFP_MINIC_OFS = 0x200
SFP_DPRAM_OFS = 0x600
SFP_BASE = 0x200
SFP_ENDPOINT_OFS = 0x000
SFP_MINIC_OFS = 0x200
SFP_DPRAM_OFS = 0x600
# Pulse counter base address
PULSE_CNT_BASE = 0xc00
PULSE_CNT_BASE = 0xc00
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