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Conv TTL Blocking - Testing
Commit d7d6789e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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fm-doc: Finished HDL guide

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fm/doc/hdlg/Makefile
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FILE=hdlg-pts-conv-ttl-blo
all:
make -C fig
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
......@@ -10,4 +10,5 @@ all:
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
$(MAKE) -C fig clean
fm/doc/hdlg/cern-title.tex
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......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill\today
\hfill December 11, 2014
\vspace*{3cm}
......
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fm/doc/hdlg/fig/rtm-test.svg 0 → 100644
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fm/doc/hdlg/fig/ttl-test.svg 0 → 100644
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fm/doc/hdlg/hdlg-pts-conv-ttl-blo.bib
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......@@ -22,40 +22,31 @@
@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{ctb-ug,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO User Guide}},
day = 05,
month = 08,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/263}}
}
@misc{ctb-hwguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO Hardware Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/282}}
}
@misc{ctb-hdlguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO HDL Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/attachments/2326/hdlguide-conv-ttl-blo-v1.02.pdf}}
howpublished = {\url{http://www.ohwr.org/documents/290}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
howpublished = {\url{www.ohwr.org/attachments/download/2324/ELMA_SNMP_specification.pdf}}
}
@misc{pts-repo,
......@@ -68,7 +59,7 @@
title = {{CONV-TTL-BLO PTS User Guide}},
month = 06,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/291}}
howpublished = {\url{http://www.ohwr.org/documents/388}}
}
@misc{pts-hwguide,
......@@ -76,5 +67,17 @@
title = {{CONV-TTL-BLO PTS Hardware Guide}},
month = 08,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/291}}
howpublished = {\url{http://www.ohwr.org/documents/388}}
}
@misc{conv-common-gw-ohwr,
title = {{Converter board common gateware project page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-common-gw}}
}
@misc{wr-cores,
title = {{White Rabbit core collection on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/wr-cores/wiki/wrpc_core}}
}
fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
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fm/doc/hdlg/pulse_cnt_wb.tex
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\subsection{Pulse counter registers}
\label{subsec:wbgen:pulse_cnt}
Registers containing the values for input and output generated pulses
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
\label{app:pulse-cnt}
Base address: 0xc00
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\begin{longtable}{l l l p{.35\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endhead
\hline
\endfoot
0x0 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH1OCR & TTL CH1 output counter register\\
0x4 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH1ICR & TTL CH1 input counter register\\
0x8 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH2OCR & TTL CH2 output counter register\\
0xc & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH2ICR & TTL CH2 input counter register\\
0x10 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH3OCR & TTL CH3 output counter register\\
0x14 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH3ICR & TTL CH3 input counter register\\
0x18 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH4OCR & TTL CH4 output counter register\\
0x1c & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH4ICR & TTL CH4 input counter register\\
0x20 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH5OCR & TTL CH5 output counter register\\
0x24 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH5ICR & TTL CH5 input counter register\\
0x28 & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH6OCR & TTL CH6 output counter register\\
0x2c & 0xf{}f{}f{}f{}f{}f{}f{}f & TTLCH6ICR & TTL CH6 input counter register\\
0x30 & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHAOCR & INV-TTL CHA output counter register\\
0x34 & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHAICR & INV-TTL CHA input counter register\\
0x38 & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHBOCR & INV-TTL CHB output counter register\\
0x3c & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHBICR & INV-TTL CHB input counter register\\
0x40 & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHCOCR & INV-TTL CHC output counter register\\
0x44 & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHCICR & INV-TTL CHC input counter register\\
0x48 & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHDOCR & INV-TTL CHD output counter register\\
0x4c & 0xf{}f{}f{}f{}f{}f{}f{}f & INVTTLCHDICR & INV-TTL CHD input counter register\\
0x50 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH1OCR & Rear CH1 output counter register\\
0x54 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH1ICR & Rear CH1 input counter register\\
0x58 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH2OCR & Rear CH2 output counter register\\
0x5c & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH2ICR & Rear CH2 input counter register\\
0x60 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH3OCR & Rear CH3 output counter register\\
0x64 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH3ICR & Rear CH3 input counter register\\
0x68 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH4OCR & Rear CH4 output counter register\\
0x6c & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH4ICR & Rear CH4 input counter register\\
0x70 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH5OCR & Rear CH5 output counter register\\
0x74 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH5ICR & Rear CH5 input counter register\\
0x78 & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH6OCR & Rear CH6 output counter register\\
0x7c & 0xf{}f{}f{}f{}f{}f{}f{}f & REARCH6ICR & Rear CH6 input counter register\\
0x00 & 0x00000000 & TTLCH1OCR & TTL CH1 output counter register\\
0x04 & 0x00000000 & TTLCH1ICR & TTL CH1 input counter register\\
0x08 & 0x00000000 & TTLCH2OCR & TTL CH2 output counter register\\
0x0c & 0x00000000 & TTLCH2ICR & TTL CH2 input counter register\\
0x10 & 0x00000000 & TTLCH3OCR & TTL CH3 output counter register\\
0x14 & 0x00000000 & TTLCH3ICR & TTL CH3 input counter register\\
0x18 & 0x00000000 & TTLCH4OCR & TTL CH4 output counter register\\
0x1c & 0x00000000 & TTLCH4ICR & TTL CH4 input counter register\\
0x20 & 0x00000000 & TTLCH5OCR & TTL CH5 output counter register\\
0x24 & 0x00000000 & TTLCH5ICR & TTL CH5 input counter register\\
0x28 & 0x00000000 & TTLCH6OCR & TTL CH6 output counter register\\
0x2c & 0x00000000 & TTLCH6ICR & TTL CH6 input counter register\\
0x30 & 0x00000000 & INVTTLCHAOCR & INV-TTL CHA output counter register\\
0x34 & 0x00000000 & INVTTLCHAICR & INV-TTL CHA input counter register\\
0x38 & 0x00000000 & INVTTLCHBOCR & INV-TTL CHB output counter register\\
0x3c & 0x00000000 & INVTTLCHBICR & INV-TTL CHB input counter register\\
0x40 & 0x00000000 & INVTTLCHCOCR & INV-TTL CHC output counter register\\
0x44 & 0x00000000 & INVTTLCHCICR & INV-TTL CHC input counter register\\
0x48 & 0x00000000 & INVTTLCHDOCR & INV-TTL CHD output counter register\\
0x4c & 0x00000000 & INVTTLCHDICR & INV-TTL CHD input counter register\\
0x50 & 0x00000000 & REARCH1OCR & Rear CH1 output counter register\\
0x54 & 0x00000000 & REARCH1ICR & Rear CH1 input counter register\\
0x58 & 0x00000000 & REARCH2OCR & Rear CH2 output counter register\\
0x5c & 0x00000000 & REARCH2ICR & Rear CH2 input counter register\\
0x60 & 0x00000000 & REARCH3OCR & Rear CH3 output counter register\\
0x64 & 0x00000000 & REARCH3ICR & Rear CH3 input counter register\\
0x68 & 0x00000000 & REARCH4OCR & Rear CH4 output counter register\\
0x6c & 0x00000000 & REARCH4ICR & Rear CH4 input counter register\\
0x70 & 0x00000000 & REARCH5OCR & Rear CH5 output counter register\\
0x74 & 0x00000000 & REARCH5ICR & Rear CH5 input counter register\\
0x78 & 0x00000000 & REARCH6OCR & Rear CH6 output counter register\\
0x7c & 0x00000000 & REARCH6ICR & Rear CH6 input counter register\\
\end{longtable}
}
......
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