HDL: Added timetags and ID of repeated pulses. Removed glitches that affected FIFO storage. Complete testbench for the wishbone register addresses of trigger.vhd. Alarm is working ok so as to let the transformer draining the magnetizing current out. Covered functionality of every channel, moving to testbenching the RAM storage --loggerRAM.vhd
TODO: I2C master/serial wishbone wrapper, loggerRAM_test.vhd.