Waveform used in modelsim for debugging

01ed5238 · gilsoriano · e2f7693e · 01ed5238
Commit 01ed5238 authored Mar 30, 2012 by gilsoriano
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wave.do hdl/i2c_slave_wb_master/project/modelsim/wave.do +110 -0

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--- a/hdl/i2c_slave_wb_master/project/modelsim/wave.do
+++ b/hdl/i2c_slave_wb_master/project/modelsim/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /i2c_slave_top_tb/wb_clk
+add wave -noupdate /i2c_slave_top_tb/wb_rst_i
+add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_oen
+add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_o
+add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_i
+add wave -noupdate -group I2C /i2c_slave_top_tb/uut/scl_i
+add wave -noupdate -group i2c_bit -height 16 /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/i2c_bit_fsm
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_sda_dGLITCH_d1
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_dGLITCH_d1
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_rising
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_falling
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/done
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_done_d1
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_done_d2
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/start_o
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/pause_o
+add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/rcved_o
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/pf_wb_addr_o
+add wave -noupdate -group wishbone_MASTER -height 16 /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_master_WB_BASIC_fsm
+add wave -noupdate -group wishbone_MASTER /i2c_slave_top_tb/uut/wb_master_cyc_o
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_stb_o
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_sel_o
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_we_o
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_data_i
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_data_o
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_addr_o
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_ack_i
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_rty_i
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_err_i
+add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_cyc_o
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_cyc_i
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_stb_i
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_sel_i
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_we_i
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_data_i
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_data_o
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_addr_i
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_ack_o
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_rty_o
+add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_err_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/PRE_i
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/CTR0_i
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/CTR1_i
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/STA_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX0_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX1_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX2_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX3_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX4_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX5_o
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX0_i
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX1_i
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX2_i
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX3_i
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_next
+add wave -noupdate -height 16 /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_previous
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_previous_start
+add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_byte_cnt
+add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/Q
+add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/C
+add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/CLR
+add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/D
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rx_fifo_flush
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_i2c_addr
+add wave -noupdate -radix binary /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rx_fifo_din
+add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/clk_i
+add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/rst_i
+add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/en_i
+add wave -noupdate -group {bit count} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/cnt_o
+add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/clk_i
+add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/rst_i
+add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/en_i
+add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/cnt_o
+add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_i
+add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/clk
+add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/push
+add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/flush
+add wave -noupdate -group {rx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_o
+add wave -noupdate -group {rx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_int
+add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_i
+add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/clk
+add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/load
+add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/flush
+add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/oen_i
+add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_o
+add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_int
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/rd_done_o
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/wr_done_o
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rcved_o
+add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_tx_fifo_reg_o
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {471826715 ps} 0}
+configure wave -namecolwidth 193
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {455785207 ps} {503379726 ps}