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Conv TTL Blocking
Commit 1182da16 authored by gilsoriano's avatar gilsoriano
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SPI master functional test passed! To add proper assertions and log of them. Syntehsizable.

parent 7e1f2435
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Showing with 396 additions and 209 deletions
hdl/ctdah_lib/rtl/FIFO_dispatcher.vhd
View file @ 1182da16
......@@ -62,6 +62,7 @@ begin
if flush = '1' then
flushLoop: for i in 0 to g_dispatcher_depth-1 loop
reg_int(i) <= (others => '0');
reg_o <= (others => '0');
end loop;
elsif rising_edge(clk) then
if load = '1' then
......
hdl/ctdah_lib/rtl/gc_clk_divider.vhd
View file @ 1182da16
......@@ -61,19 +61,25 @@ signal s_clk_o : STD_LOGIC;
signal clk_i_count : UNSIGNED(g_clk_division_logSize - 1 downto 0);
begin
clk_o <= s_clk_o;
p_div: process(clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
clk_o <= '0';
clk_i_count <= unsigned(divider_i);
elsif oe_n_i = '1' then
clk_o <= '0';
s_clk_o <= '0';
clk_i_count <= unsigned(divider_i);
-- clk_i_count <= to_unsigned(1, g_clk_division_logSize);
else
if clk_i_count = unsigned(divider_i) then
s_clk_o <= not(s_clk_o);
if oe_n_i = '0' then
clk_i_count <= clk_i_count + 1;
if clk_i_count = unsigned(divider_i) then
s_clk_o <= not(s_clk_o);
clk_i_count <= to_unsigned(1, g_clk_division_logSize);
else
end if;
else
s_clk_o <= '0';
end if;
end if;
else
......
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @ 1182da16
......@@ -39,19 +39,15 @@ entity spi_master_regs is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_o : out STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_o : out STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
SPI0_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0)
);
end spi_master_regs;
architecture Behavioral of spi_master_regs is
signal s_SPI0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (31 downto 0);
signal s_wb_ack : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
......@@ -63,8 +59,8 @@ begin
wb_rty_o <= s_wb_rty;
wb_err_o <= s_wb_err;
SPI0_o <= s_SPI0 ;
SPI1_o <= s_SPI1 ;
SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1;
p_wb: process (wb_clk_i)
begin
......@@ -76,9 +72,9 @@ begin
s_wb_rty <= '0';
s_wb_err <= '0';
else
s_wb_ack <= '0';
s_wb_rty <= '0';
s_wb_err <= '0';
s_wb_ack <= '0';
s_wb_rty <= '0';
s_wb_err <= '0';
case wb_we_i is
when '1' =>
case wb_addr_i is
......
hdl/spi_master_multifield/rtl/spi_master_top.vhd
View file @ 1182da16
......@@ -26,24 +26,28 @@ use work.spi_master_pkg.ALL;
entity spi_master_top is
port(
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
spi_cs_n_o : out STD_LOGIC
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
spi_cs_n_o : out STD_LOGIC
);
end spi_master_top;
......@@ -64,9 +68,9 @@ architecture Behavioral of spi_master_top is
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
......@@ -91,21 +95,15 @@ architecture Behavioral of spi_master_top is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_o : out STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_o : out STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
SPI0_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
signal s_inst : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
signal s_addr : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
signal s_data : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
signal s_SPI0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (15 downto 0);
begin
......@@ -114,11 +112,12 @@ begin
rst_i => wb_rst_i,
clk_i => wb_clk,
inst_i => s_inst,
addr_i => s_addr,
data_i => s_data,
inst_i => inst_i,
addr_i => addr_i,
data_i => data_i,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
SPI2_o => s_SPI2,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
......@@ -142,9 +141,6 @@ begin
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
inst_o => s_inst,
addr_o => s_addr,
data_o => s_data,
SPI0_o => s_SPI0,
SPI1_o => s_SPI1
);
......
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