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Conv TTL Blocking
Commit 15106c52 authored by gilsoriano's avatar gilsoriano
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Solved minor issues in clk_fsm

parent 3372ecf3
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Showing with 56 additions and 45 deletions
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @ 15106c52
......@@ -447,50 +447,54 @@ begin
begin
if rising_edge(clk_i) then
if s_STATUS.spi_clk_fsm = S1_START_SPI_CLK
and ( s_SPI1.SEND_INST = '1'
or s_SPI1.SEND_ADDR = '1'
or s_SPI1.SEND_DATA = '1') then
mosi_update;
end if;
case s_SPI0.CPOL is
when '0' =>
if s_SPI0.CPHA = '0' then
--! Sampling is done in rising edge, we must output in falling
--! As it will happen first a rising edge that a falling one in
--! the first clock, we have to place the correct value time
--! before in mosi line, for instance when CS is asserted
if ((s_spi_clk = '0') and (s_spi_clk_d0 = '1')) then
mosi_update;
if rst_i = '1' then
spi_mosi_o <= '0';
else
if s_STATUS.spi_clk_fsm = S1_START_SPI_CLK
and ( s_SPI1.SEND_INST = '1'
or s_SPI1.SEND_ADDR = '1'
or s_SPI1.SEND_DATA = '1') then
mosi_update;
end if;
case s_SPI0.CPOL is
when '0' =>
if s_SPI0.CPHA = '0' then
--! Sampling is done in rising edge, we must output in falling
--! As it will happen first a rising edge that a falling one in
--! the first clock, we have to place the correct value time
--! before in mosi line, for instance when CS is asserted
if ((s_spi_clk = '0') and (s_spi_clk_d0 = '1')) then
mosi_update;
else
end if;
else
--! Sampling is done in falling edge, we must output in rising
if ((s_spi_clk = '1') and (s_spi_clk_d0 = '0')) then
mosi_update;
end if;
end if;
else
when others =>
if s_SPI0.CPHA = '0' then
--! Sampling is done in falling edge, we must output in rising
if ((s_spi_clk = '1') and (s_spi_clk_d0 = '0')) then
mosi_update;
end if;
end if;
when others =>
if s_SPI0.CPHA = '0' then
--! Sampling is done in falling edge, we must output in rising
--! As it will happen first a falling edge that a rising one in
--! the first clock, we have to place the correct value time
--! before in mosi line, for instance when CS is asserted
if ( ((s_STATUS.PULL_INST = '1') or (s_STATUS.PULL_ADDR = '1')
or (s_STATUS.PULL_DATA = '1'))
and (unsigned(s_spi_counter_cnt) = 0))
or ((s_spi_clk = '1') and (s_spi_clk_d0 = '0')) then
--! As it will happen first a falling edge that a rising one in
--! the first clock, we have to place the correct value time
--! before in mosi line, for instance when CS is asserted
if ( ((s_STATUS.PULL_INST = '1') or (s_STATUS.PULL_ADDR = '1')
or (s_STATUS.PULL_DATA = '1'))
and (unsigned(s_spi_counter_cnt) = 0))
or ((s_spi_clk = '1') and (s_spi_clk_d0 = '0')) then
mosi_update;
else
end if;
else
--! Sampling is done in rising edge, we must output in falling
if (s_spi_clk = '0') and (s_spi_clk_d0 = '1') then
mosi_update;
else
end if;
else
--! Sampling is done in rising edge, we must output in falling
if (s_spi_clk = '0') and (s_spi_clk_d0 = '1') then
mosi_update;
end if;
end if;
end if;
end case;
end case;
end if;
else
end if;
end process;
......@@ -610,9 +614,12 @@ begin
if s_SPI1.SEND_OP = '1' then
case s_STATUS.clk_fsm is
when S0_IDLE =>
if (s_SPI1.SEND_INST = '1' and s_BINST /= 0)
or (s_SPI1.SEND_ADDR = '1' and s_BADDR /= 0)
or (s_SPI1.SEND_DATA = '1' and s_BDATA /= 0) then
if ( (s_SPI1.SEND_INST = '1' and s_BINST /= 0)
or (s_SPI1.SEND_ADDR = '1' and s_BADDR /= 0)
or (s_SPI1.SEND_DATA = '1' and s_BDATA /= 0))
--! We add this condition to let one clock between
--! consecutive writes
and (s_SPI2.SENT_OP ='0') then
s_STATUS.clk_fsm <= S1_SETUP;
else
end if;
......
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @ 15106c52
......@@ -132,6 +132,8 @@ package spi_master_pkg is
constant c_ADDR_LENGTH : NATURAL := 3;
constant c_DATA_LENGTH : NATURAL := 256;
constant c_CLK_DIV : UNSIGNED (15 downto 12) := to_unsigned( 2,
r_SPI1.CLK_DIV'length);
constant c_SPI0_default : r_SPI0 := (CPOL => '0',
CPHA => '0',
x => (others => '0'),
......@@ -148,7 +150,7 @@ package spi_master_pkg is
SEND_INST => '0',
SEND_OP => '0',
y => (others => '0'),
CLK_DIV => X"2",
CLK_DIV => c_CLK_DIV,
z => (others => '0'));
constant c_SPI2_default : r_SPI2 := (SENT_DATA => '0',
......@@ -269,7 +271,8 @@ package body spi_master_pkg is
--! @brief SPI2 record type translation to STD_LOGIC_VECTOR
--! @param r_register r_SPI2 record type to be translated
-----------------------------------------------------------------------------
function f_STD_LOGIC_VECTOR (r_register : in r_SPI2) return STD_LOGIC_VECTOR is
function f_STD_LOGIC_VECTOR (r_register : in r_SPI2)
return STD_LOGIC_VECTOR is
begin
return ( std_logic_vector(r_register.CLK_DIV)
& r_register.x
......@@ -284,7 +287,8 @@ package body spi_master_pkg is
--! @brief Translation from STD_LOGIC_VECTOR to r_SPI2 record
--! @param r_register STD_LOGIC_VECTOR to be translated
-----------------------------------------------------------------------------
function f_SPI2 (signal r_register : in STD_LOGIC_VECTOR(15 downto 0)) return r_SPI2 is
function f_SPI2 (signal r_register : in STD_LOGIC_VECTOR(15 downto 0))
return r_SPI2 is
variable v_SPI2 : r_SPI2;
begin
v_SPI2.SENT_DATA := r_register(0);
......
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