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Conv TTL Blocking
Commit 224a9757 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added INV_TTL functionality, tested in operation; cleaned up pulse_generator and made it more KISS.

parent 93fd7399
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Showing with 206 additions and 1091 deletions
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ 224a9757
......@@ -41,17 +41,15 @@ use ieee.numeric_std.all;
entity pulse_generator is
generic
(
g_pulse_len_nr_bits : natural := 9;
g_glitch_filt_len : natural := 6
g_pulse_width : natural := 15;
g_glitch_filt_len : natural := 6
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_len_i : in std_logic_vector(g_pulse_len_nr_bits-1 downto 0);
level_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
);
end entity pulse_generator;
......@@ -59,29 +57,29 @@ end entity pulse_generator;
architecture behav of pulse_generator is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
--============================================================================
-- Component declarations
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal len_cnt : unsigned(g_pulse_len_nr_bits-1 downto 0);
signal reject_cnt : unsigned(g_pulse_len_nr_bits-1 downto 0);
signal pulse_len : unsigned(g_pulse_len_nr_bits-1 downto 0);
signal pulse : std_logic;
signal pulse_reject : std_logic;
signal trig : std_logic;
signal level, level_n : std_logic;
signal level_arr : std_logic_vector(g_glitch_filt_len downto 0);
signal glitch_filt : std_logic_vector(g_glitch_filt_len downto 0);
-- Pulse length counter
signal width_cnt : unsigned(f_log2_size(g_pulse_width)-1 downto 0);
-- Pulse and trigger
signal pulse : std_logic;
-- Glitch filter
signal glitch_filt : std_logic_vector(g_glitch_filt_len downto 0);
signal glitch_filt_d0 : std_logic;
--==============================================================================
......@@ -90,23 +88,14 @@ architecture behav of pulse_generator is
begin
--============================================================================
-- I/O logic
-- Output logic
--============================================================================
-- Inputs
trig <= trig_i;
level <= level_i;
level_n <= not level;
level_arr <= (others => level);
pulse_len <= unsigned(pulse_len_i);
-- Output
pulse_o <= pulse or trig when (level = '1') else
pulse or (not trig);
pulse_o <= pulse or trig_i;
--============================================================================
-- Glitch filtration logic
--============================================================================
glitch_filt(0) <= trig;
glitch_filt(0) <= trig_i;
gen_glitch_filt: if (g_glitch_filt_len > 0) generate
p_glitch_filt: process (clk_i)
begin
......@@ -127,42 +116,36 @@ begin
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
len_cnt <= (others => '0');
reject_cnt <= (others => '0');
pulse <= '0';
pulse_reject <= '0';
width_cnt <= (others => '0');
pulse <= '0';
glitch_filt_d0 <= '0';
else
-- FF to detect rising edge on glitch filter output
glitch_filt_d0 <= glitch_filt(g_glitch_filt_len);
if (glitch_filt = level_arr) and (glitch_filt_d0 = level_n) then -- (pulse_reject = '0') then
-- Start outputting pulse with controlled length once the glitch filter
-- has stabilized
if (glitch_filt = (glitch_filt'range => '1')) and (glitch_filt_d0 = '0') then
pulse <= '1';
end if;
if (pulse = '1') then
len_cnt <= len_cnt + 1;
-- Reset pulse length counter when reached max length. The max length
-- is given by the module input, minus the glitch filter length (due
-- to the flip-flops the pulse goes through).
width_cnt <= width_cnt + 1;
-- Reset pulse length counter and clear output pulse when reached max
-- length. The max length is given by the module input, minus the
-- glitch filter length (due to the flip-flops the pulse goes through).
--
-- The "-2" is first because the counter starts from zero, thus the max
-- length should be pulse_len-1, and second because the pulse is set
-- on the clock edge following the glitch filter output settling to all
-- ones.
if (len_cnt = pulse_len-g_glitch_filt_len-2) then
len_cnt <= (others => '0');
pulse <= '0';
pulse_reject <= '1';
if (width_cnt = g_pulse_width-g_glitch_filt_len-2) then
width_cnt <= (others => '0');
pulse <= '0';
end if;
end if;
if (pulse_reject = '1') then
reject_cnt <= reject_cnt + 1;
if (reject_cnt = pulse_len-1) then
reject_cnt <= (others => '0');
pulse_reject <= '0';
end if;
end if;
end if;
end if;
end process p_gen_pulse;
......
hdl/pulse_generator/sim/testbench.vhd
View file @ 224a9757
......@@ -52,7 +52,7 @@ architecture behav of testbench is
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 5 ns;
constant c_clk_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
......@@ -62,15 +62,13 @@ architecture behav of testbench is
component pulse_generator is
generic
(
g_pulse_len_nr_bits : natural := 9;
g_pulse_width : natural := 15;
g_glitch_filt_len : natural := 6
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_len_i : in std_logic_vector(g_pulse_len_nr_bits-1 downto 0);
level_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
);
......@@ -94,6 +92,7 @@ architecture behav of testbench is
--============================================================================
signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
signal actual_trig : std_logic := '0';
signal actual_pulse : std_logic := '0';
--==============================================================================
-- architecture begin
......@@ -104,15 +103,13 @@ begin
DUT: pulse_generator
generic map
(
g_pulse_len_nr_bits => 9,
g_glitch_filt_len => 6
g_pulse_width => 125,
g_glitch_filt_len => 6
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_len_i => std_logic_vector(to_unsigned(200,9)),
level_i => lvl_n,
trig_i => actual_trig,
pulse_o => pulse
);
......@@ -153,13 +150,13 @@ begin
rst_n_i => rst_n,
pulse_o => trig
);
actual_trig <= not trig; --trig when lvl = '0' else not trig;
actual_trig <= trig; -- when lvl = '0' else not trig;
actual_pulse <= pulse; -- when lvl = '0' else not pulse;
lvl_n <= not lvl;
lvl <= '0';
lvl <= '1';
--trig <= '1';
......
hdl/pulse_generator/sim/transcript
View file @ 224a9757
This diff is collapsed.
hdl/pulse_generator/sim/wave.do
View file @ 224a9757
......@@ -2,8 +2,10 @@ onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/actual_pulse
add wave -noupdate -divider internal
add wave -noupdate /testbench/DUT/pulse_len_i
add wave -noupdate /testbench/DUT/len_cnt
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 224a9757
......@@ -76,36 +76,37 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1362588051" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1362588051">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1362648727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362588051" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1362588051">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1362648727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362588051" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1362588051">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1362648727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362568903" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1362568903">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1362648727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362588051" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1362588051">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1362648727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362568903" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1362568903">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1362648727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362588051" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1362588051">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1362648727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362590372" xil_pn:in_ck="-1985142147321250132" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1362590361">
<transform xil_pn:end_ts="1362654810" xil_pn:in_ck="-4590833482063591864" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1362654798">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
......@@ -121,11 +122,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1362590372" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1362590372">
<transform xil_pn:end_ts="1362651935" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1362651935">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362590377" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1362590372">
<transform xil_pn:end_ts="1362654831" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1362654825">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,7 +135,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362590404" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1362590377">
<transform xil_pn:end_ts="1362654860" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1362654831">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
......@@ -149,7 +150,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1362590433" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1362590404">
<transform xil_pn:end_ts="1362654888" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1362654860">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -163,7 +164,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362590451" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1362590433">
<transform xil_pn:end_ts="1362654907" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1362654888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -174,15 +175,13 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1362590451" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1362590451">
<transform xil_pn:end_ts="1362654919" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1362654919">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1362590433" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1362590425">
<transform xil_pn:end_ts="1362654888" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1362654881">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 224a9757
......@@ -346,10 +346,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
......@@ -360,6 +360,10 @@
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../old_rep_test/rtl/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
<bindings/>
......
hdl/release/top/conv_ttl_blo_v2.ucf
View file @ 224a9757
......@@ -141,28 +141,28 @@ NET "FPGA_OUT_TTL[5]" IOSTANDARD = LVCMOS33;
NET "FPGA_OUT_TTL[6]" LOC = H2;
NET "FPGA_OUT_TTL[6]" IOSTANDARD = LVCMOS33;
###-------------------
###-- Inverted TTL I/O
###--
###-- Schematics name: INV_IN_*
###---- renamed to INV_IN[*]
###-------------------
#NET "INV_IN_N[1]" LOC = V2;
#NET "INV_IN_N[1]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[2]" LOC = W3;
#NET "INV_IN_N[2]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[3]" LOC = Y2;
#NET "INV_IN_N[3]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[4]" LOC = AA2;
#NET "INV_IN_N[4]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[1]" LOC = J3;
#NET "INV_OUT[1]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[2]" LOC = L3;
#NET "INV_OUT[2]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[3]" LOC = M3;
#NET "INV_OUT[3]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[4]" LOC = P2;
#NET "INV_OUT[4]" IOSTANDARD = LVCMOS33;
##-------------------
##-- Inverted TTL I/O
##--
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
NET "INV_IN_N[1]" LOC = V2;
NET "INV_IN_N[1]" IOSTANDARD = LVCMOS33;
NET "INV_IN_N[2]" LOC = W3;
NET "INV_IN_N[2]" IOSTANDARD = LVCMOS33;
NET "INV_IN_N[3]" LOC = Y2;
NET "INV_IN_N[3]" IOSTANDARD = LVCMOS33;
NET "INV_IN_N[4]" LOC = AA2;
NET "INV_IN_N[4]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[1]" LOC = J3;
NET "INV_OUT[1]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[2]" LOC = L3;
NET "INV_OUT[2]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[3]" LOC = M3;
NET "INV_OUT[3]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[4]" LOC = P2;
NET "INV_OUT[4]" IOSTANDARD = LVCMOS33;
##======================================
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 224a9757
......@@ -40,7 +40,8 @@ use work.bicolor_led_ctrl_pkg.all;
entity conv_ttl_blo_v2 is
generic
(
g_nr_chan : natural := 6
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
......@@ -62,14 +63,14 @@ entity conv_ttl_blo_v2 is
LED_WR_OWNADDR_I2C : out std_logic;
-- I/Os for pulses
PULSE_FRONT_LED_N : out std_logic_vector(g_nr_chan downto 1);
PULSE_REAR_LED_N : out std_logic_vector(g_nr_chan downto 1);
FPGA_INPUT_TTL_N : in std_logic_vector(g_nr_chan downto 1);
FPGA_OUT_TTL : out std_logic_vector(g_nr_chan downto 1);
FPGA_BLO_IN : in std_logic_vector(g_nr_chan downto 1);
FPGA_TRIG_BLO : out std_logic_vector(g_nr_chan downto 1);
-- INV_IN_N : in std_logic_vector(4 downto 1);
-- INV_OUT : out std_logic_vector(4 downto 1);
PULSE_FRONT_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
PULSE_REAR_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
FPGA_INPUT_TTL_N : in std_logic_vector(g_nr_ttl_chan downto 1);
FPGA_OUT_TTL : out std_logic_vector(g_nr_ttl_chan downto 1);
FPGA_BLO_IN : in std_logic_vector(g_nr_ttl_chan downto 1);
FPGA_TRIG_BLO : out std_logic_vector(g_nr_ttl_chan downto 1);
INV_IN_N : in std_logic_vector(g_nr_inv_chan downto 1);
INV_OUT : out std_logic_vector(g_nr_inv_chan downto 1);
-- -- Lines for the i2c_slave
-- SCL_I : in std_logic;
......@@ -135,17 +136,15 @@ architecture behav of conv_ttl_blo_v2 is
component pulse_generator is
generic
(
g_pulse_len_nr_bits : natural := 9;
g_glitch_filt_len : natural := 6
g_pulse_width : natural := 15;
g_glitch_filt_len : natural := 6
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_len_i : in std_logic_vector(g_pulse_len_nr_bits-1 downto 0);
level_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_generator;
......@@ -161,6 +160,20 @@ architecture behav of conv_ttl_blo_v2 is
);
end component rtm_detector;
component pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen;
--============================================================================
-- Signal declarations
--============================================================================
......@@ -180,17 +193,20 @@ architecture behav of conv_ttl_blo_v2 is
signal rtmm_ok, rtmp_ok : std_logic;
-- Signals for pulse generation triggers
signal trig : std_logic_vector(g_nr_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_chan downto 1);
-- Temporary signal for pulse outputs
signal lvl : std_logic;
signal pulse_outputs : std_logic_vector(g_nr_chan downto 1);
signal trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
-- Pulse status LED signals
signal front_led_en : std_logic_vector(g_nr_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_chan downto 1);
signal front_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
-- Output enable signals
signal oe, ttl_oe, blo_oe, inv_oe : std_logic;
......@@ -198,6 +214,9 @@ architecture behav of conv_ttl_blo_v2 is
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
signal tmp_pulse : std_logic;
begin
--============================================================================
......@@ -223,6 +242,7 @@ begin
cmp_reset_gen: reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
......@@ -264,27 +284,25 @@ begin
FPGA_INV_OE <= inv_oe;
--============================================================================
-- Pulse generation logic
-- TTL and blocking pulse generation logic
--============================================================================
trig_ttl <= not FPGA_INPUT_TTL_N; -- when (LEVEL = '0') else FPGA_INPUT_TTL_N;
lvl <= not LEVEL;
trig_ttl <= not FPGA_INPUT_TTL_N when (LEVEL = '0') else
FPGA_INPUT_TTL_N;
trig_blo <= FPGA_BLO_IN;
trig <= trig_ttl or trig_blo;
gen_pulse_generators: for i in 1 to g_nr_chan generate
gen_ttl_pulse_generators: for i in 1 to g_nr_ttl_chan generate
-- Output pulse generators
cmp_outp_pulse_gen: pulse_generator
cmp_ttl_pulse_gen: pulse_generator
generic map
(
g_pulse_len_nr_bits => 7,
g_glitch_filt_len => 4
g_pulse_width => 125,
g_glitch_filt_len => 4
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
pulse_len_i => std_logic_vector(to_unsigned(125,7)),
level_i => lvl,
trig_i => trig(i),
pulse_o => pulse_outputs(i)
);
......@@ -293,30 +311,68 @@ begin
cmp_led_pulse_gen: pulse_generator
generic map
(
g_pulse_len_nr_bits => 25,
g_glitch_filt_len => 4
g_pulse_width => 12*(10**6),
g_glitch_filt_len => 4
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
pulse_len_i => std_logic_vector(to_unsigned(12*(10**6),25)),
level_i => lvl,
trig_i => trig(i),
pulse_o => pulse_leds(i)
);
end generate gen_pulse_generators;
end generate gen_ttl_pulse_generators;
cmp_tmp_pulse_gen: pulse_gen
generic map
(
g_pwidth => 125,
g_freq => 125*(10**6)
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
pulse_o => tmp_pulse
);
-- Pulse outputs assignment
FPGA_OUT_TTL <= pulse_outputs;
FPGA_TRIG_BLO <= pulse_outputs;
FPGA_TRIG_BLO <= (others => '0'); -- pulse_outputs;
-- Pulse status LEDs assignments
PULSE_FRONT_LED_N <= (not pulse_leds) when (ttl_oe = '1') else
(others => '1');
(others => '0');
PULSE_REAR_LED_N <= (not pulse_leds) when (blo_oe = '1') else
(others => '1');
(others => '0');
--============================================================================
-- Inverted TTL pulse generation logic
--============================================================================
-- Trigger for pulse generators
trig_inv <= not INV_IN_N when (LEVEL = '0') else
INV_IN_N;
-- Instantiate the necessary number of pulse generator components
gen_inv_pulse_generators: for i in 1 to g_nr_inv_chan generate
cmp_inv_pulse_gen: pulse_generator
generic map
(
g_pulse_width => 125,
g_glitch_filt_len => 4
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
trig_i => trig_inv(i),
pulse_o => inv_outputs(i)
);
end generate gen_inv_pulse_generators;
-- Output assignment
INV_OUT <= not inv_outputs;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......
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