Removed some latches in FIFOs.

26d6e6d1 · gilsoriano · ceebd503 · 26d6e6d1 · 26d6e6d1 · 26d6e6d1
Commit 26d6e6d1 authored Sep 30, 2012 by gilsoriano
Showing with 24 additions and 10 deletions

m25p32_core.vhd hdl/m25p32/rtl/m25p32_core.vhd +19 -7

m25p32_regs.vhd hdl/m25p32/rtl/m25p32_regs.vhd +1 -2

spi_master_core.vhd hdl/spi_master_multifield/rtl/spi_master_core.vhd +4 -1

No files found.
--- a/hdl/m25p32/rtl/m25p32_core.vhd
+++ b/hdl/m25p32/rtl/m25p32_core.vhd
@@ -98,6 +98,7 @@ signal s_SPI0              : r_SPI0;
 signal s_SPI0_d0           : r_SPI0;
 signal s_SPI0_slv          : STD_LOGIC_VECTOR (31 downto 0);
 signal s_SPI1              : r_SPI1;
+signal s_SPI1_d0           : r_SPI1;
 signal s_SPI1_slv          : STD_LOGIC_VECTOR (31 downto 0);
 signal s_SPI2              : r_SPI2;
 signal s_SPI2_slv          : STD_LOGIC_VECTOR (15 downto 0);
@@ -108,7 +109,9 @@ signal s_inst_spi          : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
 signal s_addr_spi          : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
 signal s_data_i_spi        : STD_LOGIC_VECTOR (8*g_PAGE_SIZE - 1   downto 0);

-signal s_data_o_spi        : STD_LOGIC_VECTOR (31  downto 0);
+signal s_inst_spi_d0       : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
+signal s_addr_spi_d0       : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
+signal s_data_i_spi_d0     : STD_LOGIC_VECTOR (8*g_PAGE_SIZE - 1   downto 0);


 begin
@@ -142,7 +145,7 @@ begin
       addr_i      => s_addr_spi, 
       data_i      => s_data_i_spi, 

-       data_o      => s_data_o_spi, 
+       data_o      => rd_data_o, 

       SPI0_i      => s_SPI0_slv,
       SPI1_i      => s_SPI1_slv,
@@ -157,7 +160,11 @@ begin
   p_delays : process (wb_clk)
   begin
      if rising_edge(wb_clk) then
-         s_SPI0_d0 <= s_SPI0;
+         s_SPI0_d0       <= s_SPI0;
+         s_SPI1_d0       <= s_SPI1;
+         s_inst_spi_d0   <= s_inst_spi;
+         s_addr_spi_d0   <= s_addr_spi;
+         s_data_i_spi_d0 <= s_data_i_spi;
      end if;
   end process;

@@ -212,8 +219,9 @@ begin
      end procedure;

      procedure place_inst (operation : t_operations) is
-         variable v_inst_spi  : STD_LOGIC_VECTOR(7 downto 0);
+         variable v_inst_spi  : STD_LOGIC_VECTOR(8*g_INST_LENGTH - 1 downto 0);
      begin
+         v_inst_spi := (others => '0');
         case operation is
            when RDID   =>
               v_inst_spi := c_RDID_INST;
@@ -230,7 +238,7 @@ begin
            when BE     =>
               v_inst_spi := c_BE_INST;
            when others =>
-               v_inst_spi := (others => '0');
+               null;
         end case;
         s_inst_spi(s_inst_spi'length - 1 downto
                    s_inst_spi'length - 1 - (v_inst_spi'length- 1))
@@ -271,8 +279,12 @@ begin
      end procedure;

   begin
-      s_SPI0 <= s_SPI0_d0;
-      s_SPI1 <= c_SPI1_IDLE;
+      s_SPI0       <= s_SPI0_d0;
+      s_SPI1       <= c_SPI1_IDLE;
+
+      s_inst_spi   <= s_inst_spi_d0;
+      s_addr_spi   <= s_addr_spi_d0;
+      s_data_i_spi <= s_data_i_spi_d0;

      if s_MEM_fsm_d0 /= s_MEM_fsm then
         case s_MEM_fsm is

--- a/hdl/m25p32/rtl/m25p32_regs.vhd
+++ b/hdl/m25p32/rtl/m25p32_regs.vhd
@@ -116,7 +116,6 @@ begin
            s_wb_err_o   <= '0'; 

         else
-      
            --! We never retry
            s_wb_rty_o  <= '0';

@@ -171,7 +170,7 @@ begin
                                 wb_data_o(31 downto r_SR_m25p32'a_length)
                                                                <= (others => '0');
                              when "10"   => 
-                                 wb_data_o <= f_STD_LOGIC_VECTOR(s_rd_word);
+                                 wb_data_o <= rd_data_i;
                              when others =>
                                 s_wb_ack_o  <= '0';
                                 s_wb_err_o  <= '1';

--- a/hdl/spi_master_multifield/rtl/spi_master_core.vhd
+++ b/hdl/spi_master_multifield/rtl/spi_master_core.vhd
@@ -366,7 +366,7 @@ begin
         if (to_integer(s_SPI0.BREAD) <= to_unsigned(c_READ_LENGTH, 3)) then 
            s_SPI0_core.BREAD <= s_SPI0.BREAD;
         else
-            s_SPI0_core.BREAD <= to_unsigned(c_READ_LENGTH, 9);
+            s_SPI0_core.BREAD <= to_unsigned(c_READ_LENGTH, 3);
         end if;

      end if;
@@ -402,6 +402,9 @@ begin
         s_SPI1_core.CLK_DIV     <= s_SPI1_core_d0.CLK_DIV;
         s_SPI1_core.z           <= s_SPI1_core_d0.z;

+         s_PUSH_INST_tmp         <= c_SPI1_default.PUSH_INST;
+         s_PUSH_ADDR_tmp         <= c_SPI1_default.PUSH_ADDR;
+         s_PUSH_DATA_tmp         <= c_SPI1_default.PUSH_DATA;
         --! SPI1 in case we don't have a running operation in the
         --! SPI bus, we can attend writes into SPI1
         --! As there is a running operation, we DON'T GENERATE an