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Conv TTL Blocking
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User guide complete with FPGA logic information

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doc/ug-conv-ttl-blo.pdf
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doc/ug/ug-conv-ttl-blo.tex
View file @ 26f027ea
......@@ -33,8 +33,8 @@ BE-CO-HT\\
\end{figure}
\begin{abstract}
This document describes the CONV-TTL-BLO board, a Blocking pulse repeater
board in double height VME format. It replaces all the following boards:
This document describes the CONV-TTL-BLO board, a blocking pulse repeater
board in double height VME format, intended to replace the following boards:
\begin{itemize}
\item 8 channel repeater
\item 16 channel repeater
......@@ -60,6 +60,11 @@ board in double height VME format. It replaces all the following boards:
\listoftables
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\thispagestyle{empty}
\section*{List of abbreviations}
\begin{tabular}{l l}
\textit{FPGA} & Field-Programmable Gate Array \\
......@@ -70,9 +75,6 @@ board in double height VME format. It replaces all the following boards:
\end{tabular}
\pagenumbering{arabic}
\setcounter{page}{1}
%======================================================================================
% SEC: Intro
%======================================================================================
......@@ -211,8 +213,9 @@ be followed in order to test the board.
\item Disconnect the LEMO cable from the front panel and configure the pulse generator for 15~V pulse amplitude, keeping
the pulse width to approx. 1~$\mu$s.
\item Connect the LEMO cable to the input port of channel 1 on the rear panel. Measure that the output pulse on
channel 1 is a blocking level pulse with approx. 1~${\mu}$s pulse width and 24~V in amplitude.
\item Connect the LEMO cable to the input port of channel 1 on the rear panel. The channel 1 LEDs on both front and rear panels
should be lit for 96~ms. Measure that the output pulse on channel 1 is a blocking level pulse with approx. 1~${\mu}$s pulse
width and 24~V in amplitude.
\item \label{item:pulse-last}Finally, measure on the front panel of the front module that on channel 1 the output pulse is 1~${\mu}$s long and 3.3~V.
......@@ -229,7 +232,7 @@ be followed in order to test the board.
Two panels exist in the context of the pulse repeater boards. The first of these is the
\textit{front panel}, which corresponds to CONV-TTL-BLO boards and offers various status
LEDs, as well as various connectors for TTL and INV-TTL pulses and White Rabbit.
LEDs, as well as various connectors for TTL and INV-TTL (see Sec.~\ref{sec:pulse-def}) pulses and White Rabbit.
The second is the \textit{rear panel}, located on the other side of the backplane and
corresponding to CONV-TTL-RTM-BLO boards. The rear panel offers blocking pulse connectors
and status LEDs for pulse arrival confirmation.
......@@ -356,13 +359,13 @@ the pulse signal.
\label{tbl:pulse-levels}
\centerline
{
\begin{tabular}{l c p{.3\textwidth}}
\begin{tabular}{l c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Type}} & \textbf{Pk-pk amplitude} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
TTL & 3.3~V & \\
INV-TTL & 3.3~V & Inverted version of TTL pulse \\
Blocking & 24~V & \\
Blocking & 24~V & Same as TTL, but different level and rise and fall times \\
\hline
\end{tabular}
}
......@@ -396,119 +399,253 @@ Blocking & 24~V & \\
%======================================================================================
% SEC: Boards
%======================================================================================
\section{Converter Boards}
\label{sec:boards}
This section gives further information about the three boards which when coupled together
can be used to replicate blocking-level pulses.
\subsection{CONV-TTL-BLO}
\label{sec:conv-ttl-blo}
A picture of the CONV-TTL-BLO mainboard is presented in Fig.~\ref{fig:conv-ttl-blo}.
This board represents the main part of the converter system; all of the active circuitry
involved in pulse repetition is present on this board. The Spartan-6 FPGA is the core part
of the board, reacting to pulses at either the TTL inputs arriving on front panels, or
blocking pulses arriving on rear panels through the RTM system, and generating pulses for
the output channels, both blocking and TTL.
\textcolor{red}{\textbf{board picture}}
\subsubsection{TTL and INV-TTL inputs}
\label{sec:ttl-inp}
TTL and INV-TTL level pulses arrive through the LEMO connectors. The pulses are passed
through a Schmitt trigger buffer circuit to smooth out transitions and then passed to the FPGA.
The buffer circuit is shown in Fig.~\ref{fig:ttl-inp} and is common to the six TTL input channels
and the four INV-TTL input channels.
%\section{Converter Boards}
%\label{sec:boards}
%This section gives further information about the three boards which when coupled together
%can be used to replicate blocking-level pulses.
%
%\subsection{CONV-TTL-BLO}
%\label{sec:conv-ttl-blo}
%A picture of the CONV-TTL-BLO mainboard is presented in Fig.~\ref{fig:conv-ttl-blo}.
%This board represents the main part of the converter system; all of the active circuitry
%involved in pulse repetition is present on this board. The Spartan-6 FPGA is the core part
%of the board, reacting to pulses at either the TTL inputs arriving on front panels, or
%blocking pulses arriving on rear panels through the RTM system, and generating pulses for
%the output channels, both blocking and TTL.
%
%\textcolor{red}{\textbf{board picture}}
%
%\subsubsection{TTL and INV-TTL inputs}
%\label{sec:ttl-inp}
%
%TTL and INV-TTL level pulses arrive through the LEMO connectors. The pulses are passed
%through a Schmitt trigger buffer circuit to smooth out transitions and then passed to the FPGA.
%The buffer circuit is shown in Fig.~\ref{fig:ttl-inp} and is common to the six TTL input channels
%and the four INV-TTL input channels.
%
%\begin{figure}[h]
%\begin{center}
% \includegraphics[width=.85\textwidth]{Figures/ttl-inp.png}
% \caption{TTL and INV-TTL input circuit}
% \label{fig:ttl-inp}
%\end{center}
%\end{figure}
%
%Since a signal at the input can be both TTL and INV-TTL, a switch (called the \textit{LEVEL} switch)
%is provided on the board to select between the two. The switch (shown in Fig.~\ref{fig:level-switch})
%is checked in the FPGA logic and the output pulse per each channel is adjusted according to its status.
%
%As can be seen in Fig.~\ref{fig:level-switch}, when the switch is in the upper position, it indicates
%that the signal on TTL and INV-TTL inputs is TTL level. When the switch is in the lower position,
%this indicates an INV-TTL level at TTL and INV-TTL inputs.
%
%\textcolor{red}{\textbf{LEVEL switch pic}}
%
%A board can only have TTL \textit{or} INV-TTL inputs at one time on \textit{any} channel, not both.
%The LEVEL switch indicates which of the two it is. Since there is only one LEVEL switch on CONV-TTL-BLO
%boards, it is not possible to set the type of signal per each channel.
%
%\subsubsection{Blocking inputs}
%\label{sec:blo-inp}
%
%After their arrival in the rear panel through the RTMP LEMO connectors, blocking pulses pass through an
%input circuit, shown in Fig.~\ref{fig:blo-inp}. This circuit's function is to adjust the voltage level
%of the blocking pulse to a level more suitable for input to the FPGA. A transient voltage suppressing
%diode at the input offers protection against any voltage spikes at the input, while the optocoupler
%provides the voltage adjustment.
%
%\begin{figure}[h]
%\begin{center}
% \includegraphics[width=\textwidth]{Figures/blo-inp.png}
% \caption{Blocking input circuit}
% \label{fig:blo-inp}
%\end{center}
%\end{figure}
%
%Signal levels expected at the input match those of the blocking standard definition \cite{StandardBlocking}.
%\textcolor{red}{\textbf{The minimum signal level that the optocoupler is sensitive to is 5~V.}}
%
%The output of this circuit is further passed through a Schmitt-trigger buffer to smooth out transitions.
%Since the buffer is the same inverting buffer present in the TTL input circuits, the inverted pulse signal
%coming out of the circuit in Fig.~\ref{fig:blo-inp} is once again inverted, and the FPGA receives the
%recovered pulse signal in normal polarity.
%
%\subsubsection{Blocking outputs}
%\label{sec:blo-outp}
%The blocking output circuit is shown in Fig.~\ref{fig:blo-outp}. The circuit is a typical flyback topology \cite{flyback},
%with the Coilcraft inductor providing a galvanically isolated pulse at the output. Rise and fall times of
%the pulse signals are controlled mainly by the resistors at the gate of the MOSFET transistor.
%
%\textcolor{red}{\textbf{operation}}
%
%\textcolor{red}{\textbf{snubber circuit design}}
%
%\textcolor{red}{\textbf{max pulse length on the circuit}}
%
%\begin{figure}[h]
% \begin{center}
% \includegraphics[width=\textwidth]{Figures/blo-outp.png}
% \caption{Blocking output circuit}
% \label{fig:blo-outp}
% \end{center}
%\end{figure}
\begin{figure}[h]
\begin{center}
\includegraphics[width=.85\textwidth]{Figures/ttl-inp.png}
\caption{TTL and INV-TTL input circuit}
\label{fig:ttl-inp}
\end{center}
%======================================================================================
% SEC: FPGA Logic
%======================================================================================
\section{FPGA Logic}
\label{sec:fpga}
\subsection{Block diagram}
\label{sec:fpga-bd}
A block diagram of the FPGA design is presented in Fig.~\ref{fig:fpga-bd}. First, an internal clock signal
is generated from the on-board differential 125~MHz clock oscillator. This internal clock signal is used as
the clock for all synchronous logic internal to the FPGA.
\begin{figure}
\begin{center}
\includegraphics[width=\textwidth]{Figures/fpga-bd}
\caption{Block diagram of FPGA logic design}
\label{fig:fpga-bd}
\end{center}
\end{figure}
Since a signal at the input can be both TTL and INV-TTL, a switch (called the \textit{LEVEL} switch)
is provided on the board to select between the two. The switch (shown in Fig.~\ref{fig:level-switch})
is checked in the FPGA logic and the output pulse per each channel is adjusted according to its status.
The \textit{reset\_gen} module generates an internal active-low reset signal that is input to all
synchronous with reset. RTM presence is detected via the \textit{rtm\_detector} module. Signals
generated by this module can be used in various ways in the design; in the current version of the design,
they are used as control signals for one of the bicolor LEDs on the board (the \textit{ERR} LED).
As can be seen in Fig.~\ref{fig:level-switch}, when the switch is in the upper position, it indicates
that the signal on TTL and INV-TTL inputs is TTL level. When the switch is in the lower position,
this indicates an INV-TTL level at TTL and INV-TTL inputs.
Bicolor LEDs on the board are controlled via the \textit{bicolor\_led\_ctrl} module. Based on input
control signals, this module generates signals at a preset refresh rate to light the various status LEDs
on board.
\textcolor{red}{\textbf{LEVEL switch pic}}
Finally, the \textit{pulse\_generator} modules generate predefined-width pulses to be transmitted on the
blocking, TTL and INV-TTL channels. The same \textit{pulse\_generator} module with a different pulse width
is used to light the pulse arrival LEDs on front an rear panels.
A board can only have TTL \textit{or} INV-TTL inputs at one time on \textit{any} channel, not both.
The LEVEL switch indicates which of the two it is. Since there is only one LEVEL switch on CONV-TTL-BLO
boards, it is not possible to set the type of signal per each channel.
\subsection{Reset generation}
\label{sec:fpga-rst}
The reset generator module (\textit{reset\_gen}) implemented inside the FPGA is responsible with generating
a predefined-width reset signal when power is applied to the FPGA.
\subsubsection{Blocking inputs}
\label{sec:blo-inp}
\begin{table}[h]
\centerline
{
\begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port/generic}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{g\_reset\_time} & Reset time, in number of \textit{clk\_i} clock cycles \\
\textit{clk\_i} & Input clock signal \\
\textit{rst\_n\_o} & Output reset signal, active-low \\
\hline
\end{tabular}
}
\end{table}
After their arrival in the rear panel through the RTMP LEMO connectors, blocking pulses pass through an
input circuit, shown in Fig.~\ref{fig:blo-inp}. This circuit's function is to adjust the voltage level
of the blocking pulse to a level more suitable for input to the FPGA. A transient voltage suppressing
diode at the input offers protection against any voltage spikes at the input, while the optocoupler
provides the voltage adjustment.
When a power-on reset occurs on the Xilinx FPGA, a counter inside the \textit{reset\_gen} module starts
counting up. While this counter is counting up, the active-low reset signal is kept low, resetting
synchronous logic inside the FPGA. When the counter reaches the value of the reset width (specified via the
\textit{g\_reset\_time} generic at synthesis time), the reset signal is de-asserted, the counter is
disabled and the \textit{reset\_gen} module remains inactive until the next power-on reset.
\begin{figure}[h]
\begin{center}
\includegraphics[width=\textwidth]{Figures/blo-inp.png}
\caption{Blocking input circuit}
\label{fig:blo-inp}
\end{center}
\end{figure}
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different FPGA architecture is not
guaranteed to provide the same results. The \textit{reset\_gen} module has an initial value set for the counter
signal after power-up, which is guaranteed by XST to be set after the FPGA's GSR signal is de-asserted.
Signal levels expected at the input match those of the blocking standard definition \cite{StandardBlocking}.
\textcolor{red}{\textbf{The minimum signal level that the optocoupler is sensitive to is 5~V.}}
By default, the reset time is set to 96~ms.
The output of this circuit is further passed through a Schmitt-trigger buffer to smooth out transitions.
Since the buffer is the same inverting buffer present in the TTL input circuits, the inverted pulse signal
coming out of the circuit in Fig.~\ref{fig:blo-inp} is once again inverted, and the FPGA receives the
recovered pulse signal in normal polarity.
\subsection{RTM detection}
\label{sec:fpga-rtm-det}
A simple RTM detection mechanism is employed on CONV-TTL-BLO boards. Three lines on the VME P2 connector are dedicated
for RTMM detection, and three lines for RTMP detection. On the CONV-TTL-BLO side, these lines are pulled up to VCC with
pull-up resistors. Thus, when no RTMM is plugged in, all six lines (RTMM and RTMP) are logic high due to the pull-up.
When an RTM is plugged in, the lines corresponding to the RTMM/P is connected to ground and a logic low will be detected
at the FPGA input.
\subsubsection{Blocking outputs}
\label{sec:blo-outp}
The blocking output circuit is shown in Fig.~\ref{fig:blo-outp}. The circuit is a typical flyback topology \cite{flyback},
with the Coilcraft inductor providing a galvanically isolated pulse at the output. Rise and fall times of
the pulse signals are controlled mainly by the resistors at the gate of the MOSFET transistor.
\begin{table}[h]
\centerline
{
\begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port/generic}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{rtmm\_i} & Input from RTMM detection lines \\
\textit{rtmp\_i} & Input from RTMP detection lines \\
\textit{rtmm\_ok\_o} & Status of RTMM lines (\textit{high} means RTMM plugged in) \\
\textit{rtmp\_ok\_o} & Status of RTMP lines (\textit{high} means RTMP plugged in) \\
\hline
\end{tabular}
}
\end{table}
\textcolor{red}{\textbf{operation}}
The \textit{rtm\_detector} module simply sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the \textit{rtmm\_i} and
\textit{rtmp\_i} input signals are respectively all-ones.
\textcolor{red}{\textbf{snubber circuit design}}
While more advanced RTM detection can be employed if need be, the RTM signals are currently used to signal an error via the
\textit{ERR} status LED on the CONV-TTL-BLO front panel. The \textit{ERR} led is lit when both \textit{rtmp\_ok} and \textit{rtmm\_ok}
outputs are low.
\textcolor{red}{\textbf{max pulse length on the circuit}}
\subsection{Pulse generation}
\label{sec:fpga-pulse-gen}
\begin{figure}[h]
\begin{center}
\includegraphics[width=\textwidth]{Figures/blo-outp.png}
\caption{Blocking output circuit}
\label{fig:blo-outp}
\end{center}
\end{figure}
The \textit{pulse\_generator} module is used to generate pulses of predefined width based on a trigger input.
To avoid glitches on the input, the trigger input is taken through a variable-length glitch filter (set by
the user at synthesis time via the \textit{g\_glitch\_filt\_len} generic). The glitch filter consists of a
series of flip-flops that, when all high, trigger the generation of a variable-width pulse at the output.
The width of the pulse is set via the \textit{g\_pulse\_width} generic.
%======================================================================================
% SEC: FPGA Logic
%======================================================================================
\section{FPGA Logic}
\label{sec:fpga}
\begin{table}[h]
\centerline
{
\begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port/generic}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{g\_pulse\_width} & Width of the pulse, in number of \textit{clk\_i} clock cycles \\
\textit{g\_glitch\_filt\_len} & Length of glitch filter. A length of \textit{1} means the
pulse generator block is sensitive to glitches of more than one
clock cycle \\
\textit{clk\_i} & Clock input \\
\textit{rst\_n\_i} & Active-low reset signal \\
\textit{trig\_i} & Trigger signal, must be active-high \\
\textit{pulse\_o} & Active-high pulse signal \\
\hline
\end{tabular}
}
\end{table}
\subsection{Block diagram}
\label{sec:fpga-bd}
A block diagram of the FPGA design is presented in Fig.~\ref{fig:fpga-bd}.
Assuming active-high triggers arrive at the \textit{pulse\_generator} module trigger input, high-level active pulses
are generated at the pulse output of the module (Fig.~\ref{fig:pulse-gen-sigs}). In order to avoid output jitter,
the pulse output is selected between the trigger input and the internally-generated pulse signal. The latter
is generated using an internal counter, which starts counting once the glitch filter has settled to all-ones.
When a trigger arrives at the input it is directed to the output; when the glitch filter settles to all-ones,
the pulse signal at the input is extended to the pulse width value set by the \textit{g\_pulse\_width} generic.
\begin{figure}
\begin{center}
\includegraphics[width=\textwidth]{Figures/fpga-bd}
\caption{Block diagram of FPGA logic design}
\label{fig:fpga-bd}
\includegraphics{Figures/pulse-gen-sigs}
\caption{Pulse generator trigger and output polarity}
\label{fig:pulse-gen-sigs}
\end{center}
\end{figure}
\textcolor{red}{\textbf{details about logic}}
\textcolor{red}{\textbf{pulse generator}}
Finally, because the \textit{pulse\_generator} module is used to drive the transformers generating the blocking pulses, a
pulse rejection mechanism is employed. This mechanism rejects pulses longer than the desired output pulse width by setting
a signal that is used to select the signal routed to the output. The pulse rejection signal is set as soon as a pulse is
generated via the internal counter, thus once the input has passed through the glitch filter successfully. The pulse
rejection signal is cleared when the trigger input settles back to zero and the cycle restarts when a new input pulse
arrives. It is assumed that the input pulse frequency is sufficiently low to allow the transformer to
give away all the energy stored in its magnetic field.
Multiple \textit{pulse\_generator} modules are instantiated in the design and used to generate pulse signals. Six of these
are configured to output 1~$\mu$s pulses on both TTL and blocking outputs based on a trigger signal which is the \textit{OR}
of TTL and blocking level input pulses. Four are configured to output 1~$\mu$s pulses based on a trigger from the INV-TTL channels.
Finally, six \textit{pulse\_generator} modules are configured to output 96~ms pulses to light the pulse status LEDs corresponding to the six
blocking and TTL channels; they are sensitive to the same trigger input as the TTL and blocking pulse generators.
All pulse generator modules instantiated in the design have glitch filters with length four, thus the input trigger pulse
has to have a width of at least 32~ns, considering the 125~MHz clock input.
%======================================================================================
% SEC: Internal regs
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 26f027ea
......@@ -406,7 +406,7 @@ begin
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
......
hdl/reset_gen/rtl/reset_gen.vhd
View file @ 26f027ea
......@@ -43,7 +43,7 @@ entity reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
g_reset_time : positive := 12_000_000
);
port
(
......
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