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Conv TTL Blocking
Commit 271a30e4 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Fixed active file indentations & some naming.

parent 494c7f90
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hdl/IMAGES/image1/project/image1.gise
View file @ 271a30e4
...@@ -76,6 +76,7 @@ ...@@ -76,6 +76,7 @@
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1361359864"> <transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1361359864"> <transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
...@@ -101,7 +102,7 @@ ...@@ -101,7 +102,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359880" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361359864"> <transform xil_pn:end_ts="1361383048" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361383029">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -123,7 +124,7 @@ ...@@ -123,7 +124,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359886" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361359880"> <transform xil_pn:end_ts="1361383079" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361383072">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -133,11 +134,9 @@ ...@@ -133,11 +134,9 @@
<outfile xil_pn:name="image1_top.ngd"/> <outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/> <outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359919" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361359886"> <transform xil_pn:end_ts="1361383118" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361383079">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="image1_top.pcf"/> <outfile xil_pn:name="image1_top.pcf"/>
<outfile xil_pn:name="image1_top_map.map"/> <outfile xil_pn:name="image1_top_map.map"/>
...@@ -148,7 +147,7 @@ ...@@ -148,7 +147,7 @@
<outfile xil_pn:name="image1_top_summary.xml"/> <outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/> <outfile xil_pn:name="image1_top_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359953" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361359919"> <transform xil_pn:end_ts="1361383152" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361383118">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -163,7 +162,7 @@ ...@@ -163,7 +162,7 @@
<outfile xil_pn:name="image1_top_pad.txt"/> <outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/> <outfile xil_pn:name="image1_top_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359972" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361359953"> <transform xil_pn:end_ts="1361383171" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361383152">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
...@@ -174,15 +173,13 @@ ...@@ -174,15 +173,13 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359976" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361359976"> <transform xil_pn:end_ts="1361383284" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361383284">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/> <outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/> <outfile xil_pn:name="ise_impact.cmd"/>
</transform> </transform>
<transform xil_pn:end_ts="1361359953" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361359944"> <transform xil_pn:end_ts="1361383152" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361383144">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 271a30e4
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hdl/IMAGES/image1/top/image1_top.vhd
View file @ 271a30e4
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hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ 271a30e4
...@@ -24,19 +24,25 @@ use IEEE.NUMERIC_STD.ALL; ...@@ -24,19 +24,25 @@ use IEEE.NUMERIC_STD.ALL;
use work.ctdah_pkg.ALL; use work.ctdah_pkg.ALL;
entity basic_trigger_core is entity basic_trigger_core is
generic(g_CLK_PERIOD : TIME; generic
g_OUTPUT_PULSE_LENGTH : TIME; (
g_LED_BLINKING_LENGTH : TIME); g_CLK_PERIOD : TIME;
port (wb_rst_i : in STD_LOGIC; g_OUTPUT_PULSE_LENGTH : TIME;
wb_clk_i : in STD_LOGIC; g_LED_BLINKING_LENGTH : TIME
);
port
(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC; pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC; pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC; pulse_n_o : out STD_LOGIC;
crop_o : out STD_LOGIC; crop_o : out STD_LOGIC;
led_o : out STD_LOGIC); led_o : out STD_LOGIC
);
end basic_trigger_core; end basic_trigger_core;
architecture Behavioral of basic_trigger_core is architecture Behavioral of basic_trigger_core is
...@@ -59,44 +65,60 @@ architecture Behavioral of basic_trigger_core is ...@@ -59,44 +65,60 @@ architecture Behavioral of basic_trigger_core is
-- return v; -- return v;
-- end ledlen; -- end ledlen;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD; signal s_pulse : STD_LOGIC;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
signal s_pulse : STD_LOGIC;
signal s_deglitched_pulse : STD_LOGIC;
signal s_deglitched_pulse_d0 : STD_LOGIC;
signal s_pulse_parity : STD_LOGIC; signal s_deglitched_pulse : STD_LOGIC;
signal s_deglitched_pulse_d0 : STD_LOGIC;
signal s_pulse_parity : STD_LOGIC;
begin begin
s_pulse <= pulse_i; s_pulse <= pulse_i;
inst_debo: gc_debouncer cmp_debouncer: gc_debouncer
generic map( g_LENGTH => 2) generic map
port map(rst => wb_rst_i, (
clk => wb_clk_i, g_LENGTH => 2
input => s_pulse, )
output => s_deglitched_pulse, port map
glitch_mask => "11"); (
rst => wb_rst_i,
pulse_monostable : gc_simple_monostable clk => wb_clk_i,
generic map (g_PULSE_LENGTH => c_PULSE_LENGTH) input => s_pulse,
port map (rst => wb_rst_i, output => s_deglitched_pulse,
clk => wb_clk_i, glitch_mask => "11"
input => s_deglitched_pulse, );
output => pulse_o,
output_n => pulse_n_o); cmp_pulse_monostable : gc_simple_monostable
generic map
led_monostable : gc_simple_monostable (
generic map (g_PULSE_LENGTH => c_LED_LENGTH) g_PULSE_LENGTH => c_PULSE_LENGTH
port map (rst => wb_rst_i, )
clk => wb_clk_i, port map
input => s_deglitched_pulse, (
output => led_o, rst => wb_rst_i,
output_n => open); clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o
);
cmp_led_monostable : gc_simple_monostable
generic map
(
g_PULSE_LENGTH => c_LED_LENGTH
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o,
output_n => open
);
end Behavioral; end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 271a30e4
...@@ -29,11 +29,15 @@ use IEEE.NUMERIC_STD.ALL; ...@@ -29,11 +29,15 @@ use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL; use UNISIM.VCOMPONENTS.ALL;
entity basic_trigger_top is entity basic_trigger_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6; generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns; g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns; g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns); g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns
port ( );
port
(
clk_i : in STD_LOGIC; clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC; rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC; led_ttl_o : out STD_LOGIC;
...@@ -41,7 +45,7 @@ entity basic_trigger_top is ...@@ -41,7 +45,7 @@ entity basic_trigger_top is
fpga_o_ttl_en : out STD_LOGIC; fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC; fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC; fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC; level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given --! 24V rail after a security given
...@@ -61,40 +65,44 @@ end basic_trigger_top; ...@@ -61,40 +65,44 @@ end basic_trigger_top;
architecture Behavioral of basic_trigger_top is architecture Behavioral of basic_trigger_top is
signal s_pulse_i : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); signal s_pulse_i : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); signal s_pulse_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_n_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); signal s_pulse_n_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_led : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); signal s_led : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_crop : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1) signal s_crop : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1) := (others => '0');
:= (others => '0'); signal s_level : STD_LOGIC;
signal s_level : STD_LOGIC;
signal s_fpga_o_en : STD_LOGIC;
signal s_fpga_o_en : STD_LOGIC; signal s_fpga_o_ttl_en : STD_LOGIC;
signal s_fpga_o_ttl_en : STD_LOGIC; signal s_fpga_o_inv_en : STD_LOGIC;
signal s_fpga_o_inv_en : STD_LOGIC; signal s_fpga_o_blo_en : STD_LOGIC;
signal s_fpga_o_blo_en : STD_LOGIC;
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1) of STD_LOGIC_VECTOR(3 downto 0);
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1) signal s_pulse_i_reg : delay_array;
of STD_LOGIC_VECTOR(3 downto 0);
signal s_pulse_i_reg : delay_array; component basic_trigger_core is
generic
component basic_trigger_core is (
generic(g_CLK_PERIOD : TIME := g_CLK_PERIOD; g_CLK_PERIOD : TIME := g_CLK_PERIOD;
g_OUTPUT_PULSE_LENGTH : TIME := g_OUTPUT_PULSE_LENGTH; g_OUTPUT_PULSE_LENGTH : TIME := g_OUTPUT_PULSE_LENGTH;
g_LED_BLINKING_LENGTH : TIME := g_LED_BLINKING_LENGTH); g_LED_BLINKING_LENGTH : TIME := g_LED_BLINKING_LENGTH
port (wb_rst_i : in STD_LOGIC; );
wb_clk_i : in STD_LOGIC; port
(
pulse_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
pulse_o : out STD_LOGIC; wb_clk_i : in STD_LOGIC;
pulse_n_o : out STD_LOGIC;
pulse_i : in STD_LOGIC;
crop_o : out STD_LOGIC; pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
led_o : out STD_LOGIC);
end component; crop_o : out STD_LOGIC;
led_o : out STD_LOGIC
);
end component;
begin begin
...@@ -109,7 +117,7 @@ begin ...@@ -109,7 +117,7 @@ begin
not pulse_i_front; not pulse_i_front;
s_pulse_i <= s_pulse_i_front or pulse_i_rear; s_pulse_i <= s_pulse_i_front or pulse_i_rear;
fpga_o_en <= s_fpga_o_en when switch_i = '0' else '0'; fpga_o_en <= s_fpga_o_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= s_fpga_o_ttl_en; fpga_o_ttl_en <= s_fpga_o_ttl_en;
fpga_o_inv_en <= s_fpga_o_inv_en; fpga_o_inv_en <= s_fpga_o_inv_en;
fpga_o_blo_en <= s_fpga_o_blo_en; fpga_o_blo_en <= s_fpga_o_blo_en;
...@@ -121,47 +129,47 @@ begin ...@@ -121,47 +129,47 @@ begin
not s_pulse_o; not s_pulse_o;
pulse_o_rear <= s_pulse_o; pulse_o_rear <= s_pulse_o;
inv_o <= inv_i;--! As we have one Schmitt inverter in the input, --! As we have one Schmitt inverter in the input,
--! and a buffer in the output, there's no need --! and a buffer in the output, there's no need
--! to invert here. --! to invert here.
inv_o <= inv_i;
i_repetitors: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin gen_trig_cores: for i in 1 to g_NUMBER_OF_CHANNELS generate
trigger: basic_trigger_core trigger: basic_trigger_core
port map port map
( (
wb_rst_i => rst_i, wb_rst_i => rst_i,
wb_clk_i => clk_i, wb_clk_i => clk_i,
pulse_i => s_pulse_i(i), pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i), pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i), pulse_n_o => s_pulse_n_o(i),
crop_o => open, crop_o => open,
led_o => s_led(i) led_o => s_led(i)
); );
end generate i_repetitors; end generate gen_trig_cores;
--! @brief Process to lock the enables so to avoid output glitches --! @brief Process to lock the enables so to avoid output glitches
--! on the startup. --! on the startup.
--! @param clk_i Main clock used in this clock domain. --! @param clk_i Main clock used in this clock domain.
p_reset_chain : process(clk_i) is p_reset_chain : process(clk_i) is
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_i = '1' then if rst_i = '1' then
--! First we reset the FPGA general output enable --! First we reset the FPGA general output enable
--! Then we let one clock delay for the rest of signals --! Then we let one clock delay for the rest of signals
manual_rst_n_o <= '0'; manual_rst_n_o <= '0';
s_fpga_o_en <= '0'; s_fpga_o_en <= '0';
s_fpga_o_ttl_en <= '0'; s_fpga_o_ttl_en <= '0';
s_fpga_o_inv_en <= '0'; s_fpga_o_inv_en <= '0';
s_fpga_o_blo_en <= '0'; s_fpga_o_blo_en <= '0';
else else
manual_rst_n_o <= '1'; manual_rst_n_o <= '1';
s_fpga_o_en <= '1'; s_fpga_o_en <= '1';
s_fpga_o_ttl_en <= s_fpga_o_en; s_fpga_o_ttl_en <= s_fpga_o_en;
s_fpga_o_inv_en <= s_fpga_o_en; s_fpga_o_inv_en <= s_fpga_o_en;
s_fpga_o_blo_en <= s_fpga_o_en; s_fpga_o_blo_en <= s_fpga_o_en;
end if; end if;
end if; end if;
end process p_reset_chain; end process p_reset_chain;
end Behavioral; end Behavioral;
hdl/ctdah_lib/rtl/gc_counter.vhd
View file @ 271a30e4
...@@ -41,15 +41,17 @@ use IEEE.STD_LOGIC_1164.ALL; ...@@ -41,15 +41,17 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
entity gc_counter is entity gc_counter is
generic( generic
g_DATA_WIDTH: NATURAL (
); g_DATA_WIDTH: NATURAL
port ( );
clk_i : in STD_LOGIC; port
rst_i : in STD_LOGIC; (
en_i : in STD_LOGIC; clk_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0) rst_i : in STD_LOGIC;
); en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end gc_counter; end gc_counter;
architecture Behavioral of gc_counter is architecture Behavioral of gc_counter is
...@@ -57,24 +59,17 @@ architecture Behavioral of gc_counter is ...@@ -57,24 +59,17 @@ architecture Behavioral of gc_counter is
begin begin
main_proc: process(clk_i, rst_i) p_main: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0);
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0); begin
if rst_i = '1' then
begin cnt_s := (others => '0');
elsif rising_edge(clk_i) then
if rst_i = '1' then if en_i = '1' then
cnt_s := (others => '0'); cnt_s := cnt_s + 1;
elsif rising_edge(clk_i) then
if en_i = '1' then
-- Increment the counter if counting is enabled
cnt_s := cnt_s + 1;
else
end if;
else
end if; end if;
cnt_o <= std_logic_vector(cnt_s); end if;
cnt_o <= std_logic_vector(cnt_s);
end process; end process p_main;
end Behavioral; end Behavioral;
hdl/ctdah_lib/rtl/gc_debouncer.vhd
View file @ 271a30e4
...@@ -35,49 +35,51 @@ entity gc_debouncer is ...@@ -35,49 +35,51 @@ entity gc_debouncer is
end gc_debouncer; end gc_debouncer;
architecture Behavioral of gc_debouncer is architecture Behavioral of gc_debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
signal meta_ff1 : std_logic; component gc_ff
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0); port
(
component gc_ff Q : out STD_LOGIC;
port ( C : in STD_LOGIC;
Q : out STD_LOGIC; CLR : in STD_LOGIC;
C : in STD_LOGIC; D : in STD_LOGIC
CLR : in STD_LOGIC; );
D : in STD_LOGIC end component;
);
end component;
begin begin
ff1: gc_ff ff1: gc_ff
port map( port map
Q => meta_ff1, (
C => clk, Q => meta_ff1,
CLR => rst, C => clk,
D => input CLR => rst,
); D => input
);
ff2: gc_ff ff2: gc_ff
port map( port map
Q => delay_s(0), (
C => clk, Q => delay_s(0),
CLR => rst, C => clk,
D => meta_ff1 CLR => rst,
); D => meta_ff1
);
-- Metastability solved here
delay_line: for i in 1 to g_LENGTH-1 generate -- Metastability solved here
gen_delay_line: for i in 1 to g_LENGTH-1 generate
D_Flip_Flop : gc_ff D_Flip_Flop : gc_ff
port map ( port map
Q => delay_s(i), (
C => clk, Q => delay_s(i),
CLR => rst, C => clk,
D => delay_s(i-1)); CLR => rst,
end generate delay_line; D => delay_s(i-1)
);
end generate gen_delay_line;
process (clk) process (clk)
begin begin
......
hdl/ctdah_lib/rtl/gc_ff.vhd
View file @ 271a30e4
...@@ -23,12 +23,13 @@ use IEEE.NUMERIC_STD.ALL; ...@@ -23,12 +23,13 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_ff is entity gc_ff is
port( port
Q : out STD_LOGIC; (
C : in STD_LOGIC; Q : out STD_LOGIC;
CLR : in STD_LOGIC; C : in STD_LOGIC;
D : in STD_LOGIC CLR : in STD_LOGIC;
); D : in STD_LOGIC
);
end gc_ff; end gc_ff;
architecture Behavioral of gc_ff is architecture Behavioral of gc_ff is
...@@ -43,7 +44,6 @@ begin ...@@ -43,7 +44,6 @@ begin
else else
Q <= D; Q <= D;
end if; end if;
else
end if; end if;
end process; end process;
......
hdl/ctdah_lib/rtl/gc_simple_monostable.vhd
View file @ 271a30e4
...@@ -23,71 +23,74 @@ use IEEE.NUMERIC_STD.ALL; ...@@ -23,71 +23,74 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_simple_monostable is entity gc_simple_monostable is
generic(g_PULSE_LENGTH : NATURAL := 20); generic
port ( (
rst : in STD_LOGIC; g_PULSE_LENGTH : NATURAL := 20
clk : in STD_LOGIC; );
input : in STD_LOGIC; port
output : out STD_LOGIC; (
output_n : out STD_LOGIC); rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
output_n : out STD_LOGIC
);
end gc_simple_monostable; end gc_simple_monostable;
architecture Behavioral of gc_simple_monostable is architecture Behavioral of gc_simple_monostable is
constant c_count_max : UNSIGNED (63 downto 0) := constant c_count_max : UNSIGNED (63 downto 0) := to_unsigned(g_PULSE_LENGTH, 64);
to_unsigned(g_PULSE_LENGTH, 64);
signal s_count : UNSIGNED (63 downto 0) := to_unsigned(0, 64); signal s_count : UNSIGNED (63 downto 0) := to_unsigned(0, 64);
signal s_input : STD_LOGIC := '0'; signal s_input : STD_LOGIC := '0';
signal s_input_d0 : STD_LOGIC := '0'; signal s_input_d0 : STD_LOGIC := '0';
signal s_running : STD_LOGIC := '0'; signal s_running : STD_LOGIC := '0';
signal s_output : STD_LOGIC := '0'; signal s_output : STD_LOGIC := '0';
signal s_output_n : STD_LOGIC := '1'; signal s_output_n : STD_LOGIC := '1';
begin begin
s_input <= input; s_input <= input;
output <= s_output; output <= s_output;
output_n <= s_output_n; output_n <= s_output_n;
p_mono: process(clk) p_mono: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
s_count <= to_unsigned(0, 64); s_count <= to_unsigned(0, 64);
s_running <= '0'; s_running <= '0';
s_input_d0 <= '0'; s_input_d0 <= '0';
s_output <= '0'; s_output <= '0';
s_output_n <= '1'; s_output_n <= '1';
else else
s_input_d0 <= s_input; s_input_d0 <= s_input;
s_output <= '0'; s_output <= '0';
s_output_n <= '1'; s_output_n <= '1';
s_count <= to_unsigned(0, 64); s_count <= to_unsigned(0, 64);
s_running <= '0'; s_running <= '0';
if (s_input = '1') if (s_input = '1') and (s_input_d0 = '0') then
and (s_input_d0 = '0') then s_count <= s_count + 1;
s_count <= s_count + 1; s_running <= '1';
s_running <= '1'; s_output <= '1';
s_output <= '1'; s_output_n <= '0';
s_output_n <= '0'; elsif (s_running = '1') then
elsif s_running = '1' then if (s_count < c_count_max) then
if s_count < c_count_max then s_count <= s_count + 1;
s_count <= s_count + 1; s_running <= '1';
s_running <= '1'; s_output <= '1';
s_output <= '1'; s_output_n <= '0';
s_output_n <= '0'; else
else s_count <= to_unsigned(0, 64);
s_count <= to_unsigned(0, 64); s_running <= '0';
s_running <= '0'; end if;
end if;
end if;
end if; end if;
end if; end if;
end if;
end process; end process;
end Behavioral; end Behavioral;
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
View file @ 271a30e4
This diff is collapsed.
hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd
View file @ 271a30e4
...@@ -30,61 +30,73 @@ use work.i2c_slave_pkg.ALL; ...@@ -30,61 +30,73 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL; use work.ctdah_pkg.ALL;
entity i2c_debouncer is entity i2c_debouncer is
generic (g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH); generic
port (rst : in STD_LOGIC; (
clk : in STD_LOGIC; g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH
input : in STD_LOGIC; );
output : out STD_LOGIC; port
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)); (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer; end i2c_debouncer;
architecture Behavioral of i2c_debouncer is architecture Behavioral of i2c_debouncer is
signal s_input_d0 : STD_LOGIC; signal s_input_d0 : STD_LOGIC;
--! The first of this signal is already stable (ff'ed two times at [0]) -- The first of this signal is already stable (ff'ed two times at [0])
signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0); signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin begin
ff1: gc_ff cmp_ff1: gc_ff
port map( port map
Q => s_input_d0, (
C => clk, Q => s_input_d0,
CLR => rst, C => clk,
D => input); CLR => rst,
D => input
);
ff2: gc_ff cmp_ff2: gc_ff
port map( port map
Q => s_delay(0), (
C => clk, Q => s_delay(0),
CLR => rst, C => clk,
D => s_input_d0); CLR => rst,
D => s_input_d0
);
sync_delay_line: for i in 1 to g_LENGTH - 1 generate gen_sync_delay_line: for i in 1 to g_LENGTH - 1 generate
D_Flip_Flop : gc_ff cmp_ff: gc_ff
port map ( port map
Q => s_delay(i), (
C => clk, Q => s_delay(i),
CLR => rst, C => clk,
D => s_delay(i-1)); CLR => rst,
end generate sync_delay_line; D => s_delay(i-1)
);
end generate gen_sync_delay_line;
p_output : process (clk) p_output: process (clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if (rst = '1') then
output <= '1'; output <= '1';
else else
--! We can deglitch either zeros or ones -- We can deglitch either zeros or ones
if ( (s_delay and glitch_mask) = glitch_mask if ( (s_delay and glitch_mask) = glitch_mask
or (not(s_delay)and glitch_mask) = glitch_mask) then or (not(s_delay) and glitch_mask) = glitch_mask) then
output <= s_delay(0); output <= s_delay(0);
else else
--! Internall pull-up of the pin -- Internall pull-up of the pin
output <= '1'; output <= '1';
end if; end if;
end if; end if;
end if; end if;
end process p_output; end process p_output;
end Behavioral; end Behavioral;
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 271a30e4
This diff is collapsed.
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 271a30e4
...@@ -26,148 +26,153 @@ use work.i2c_slave_pkg.ALL; ...@@ -26,148 +26,153 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL; use work.ctdah_pkg.ALL;
entity i2c_slave_top is entity i2c_slave_top is
generic (g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns generic
(
g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD -- Specify in ns
);
port port
( (
sda_oen : out STD_LOGIC; sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC; sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC; sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC; scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC; scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC; scl_o : out STD_LOGIC;
wb_clk_i : in STD_LOGIC; wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC; wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC; wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0); wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC; wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0); wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0); wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0); wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC; wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC; wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC; wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC; wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC; wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0); wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC; wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0); wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0); wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0); wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC; wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC; wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC; wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC; pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC; rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC; wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0) i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
); );
end i2c_slave_top; end i2c_slave_top;
architecture Behavioral of i2c_slave_top is architecture Behavioral of i2c_slave_top is
signal s_CTR0_slv : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0); signal ctr0 : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
signal s_CTR0 : r_CTR0; signal lt : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal s_LT_slv : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal drxa : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal drxb : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal s_DRXA : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0); signal pf_wb_addr : STD_LOGIC;
signal s_DRXB : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0); signal pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal rd_done : STD_LOGIC;
signal wr_done : STD_LOGIC;
signal s_pf_wb_addr : STD_LOGIC; signal s_clk_i2c : STD_LOGIC;
signal s_pf_wb_data : STD_LOGIC_VECTOR(31 downto 0); signal rst_i2c : STD_LOGIC;
signal s_rd_done : STD_LOGIC; signal reset_extender: STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1 downto 0) := (others => '1');
signal s_wr_done : STD_LOGIC;
signal s_clk_i2c : STD_LOGIC;
signal s_rst_i2c : STD_LOGIC;
signal s_reset_extensor : STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1
downto 0) := (others => '1');
begin begin
pf_wb_addr_o <= s_pf_wb_addr; pf_wb_addr_o <= pf_wb_addr;
rd_done_o <= s_rd_done; rd_done_o <= rd_done;
wr_done_o <= s_wr_done; wr_done_o <= wr_done;
--! Added for simulation
s_CTR0 <= f_CTR0(s_CTR0_slv); cmp_i2c_slave_core: i2c_slave_core
port map
inst_i2c_slave_core: i2c_slave_core (
port map(clk_i => wb_clk_i, clk_i => wb_clk_i,
rst_i => wb_rst_i, rst_i => wb_rst_i,
sda_oen => sda_oen, sda_oen => sda_oen,
sda_i => sda_i, sda_i => sda_i,
sda_o => sda_o, sda_o => sda_o,
scl_oen => scl_oen, scl_oen => scl_oen,
scl_i => scl_i, scl_i => scl_i,
scl_o => scl_o, scl_o => scl_o,
CTR0_i => s_CTR0_slv, CTR0_i => ctr0,
LT_o => s_LT_slv, LT_o => lt,
DRXA_o => s_DRXA, DRXA_o => drxa,
DRXB_o => s_DRXB, DRXB_o => drxb,
pf_wb_addr_o => s_pf_wb_addr, pf_wb_addr_o => pf_wb_addr,
pf_wb_data_i => s_pf_wb_data, pf_wb_data_i => pf_wb_data,
rd_done_o => s_rd_done, rd_done_o => rd_done,
wr_done_o => s_wr_done); wr_done_o => wr_done
);
inst_i2c_regs: i2c_regs
port map(pf_wb_addr_i => s_pf_wb_addr, cmp_i2c_regs: i2c_regs
pf_wb_data_o => s_pf_wb_data, port map
rd_done_i => s_rd_done, (
wr_done_i => s_wr_done, pf_wb_addr_i => pf_wb_addr,
pf_wb_data_o => pf_wb_data,
wb_rst_i => wb_rst_i, rd_done_i => rd_done,
wb_clk_i => wb_clk_i, wr_done_i => wr_done,
wb_master_we_o => wb_master_we_o, wb_rst_i => wb_rst_i,
wb_master_stb_o => wb_master_stb_o, wb_clk_i => wb_clk_i,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o, wb_master_we_o => wb_master_we_o,
wb_master_data_i => wb_master_data_i, wb_master_stb_o => wb_master_stb_o,
wb_master_data_o => wb_master_data_o, wb_master_cyc_o => wb_master_cyc_o,
wb_master_addr_o => wb_master_addr_o, wb_master_sel_o => wb_master_sel_o,
wb_master_ack_i => wb_master_ack_i, wb_master_data_i => wb_master_data_i,
wb_master_rty_i => wb_master_rty_i, wb_master_data_o => wb_master_data_o,
wb_master_err_i => wb_master_err_i, wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i,
wb_slave_we_i => wb_slave_we_i, wb_master_rty_i => wb_master_rty_i,
wb_slave_stb_i => wb_slave_stb_i, wb_master_err_i => wb_master_err_i,
wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_sel_i => wb_slave_sel_i, wb_slave_we_i => wb_slave_we_i,
wb_slave_data_i => wb_slave_data_i, wb_slave_stb_i => wb_slave_stb_i,
wb_slave_data_o => wb_slave_data_o, wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_addr_i => wb_slave_addr_i, wb_slave_sel_i => wb_slave_sel_i,
wb_slave_ack_o => wb_slave_ack_o, wb_slave_data_i => wb_slave_data_i,
wb_slave_rty_o => wb_slave_rty_o, wb_slave_data_o => wb_slave_data_o,
wb_slave_err_o => wb_slave_err_o, wb_slave_addr_i => wb_slave_addr_i,
wb_slave_ack_o => wb_slave_ack_o,
CTR0_o => s_CTR0_slv, wb_slave_rty_o => wb_slave_rty_o,
LT_i => s_LT_slv, wb_slave_err_o => wb_slave_err_o,
DRXA_i => s_DRXA,
DRXB_i => s_DRXB, CTR0_o => ctr0,
i2c_addr_i => i2c_addr_i); LT_i => lt,
DRXA_i => drxa,
DRXB_i => drxb,
s_rst_i2c <= s_reset_extensor(2**c_RST_EXTENSOR - 1); i2c_addr_i => i2c_addr_i
);
rst_i2c <= reset_extender(2**c_RST_EXTENSOR - 1);
--! A shift with reset, consumes just a few SLICEX in Spartan6. --! A shift with reset, consumes just a few SLICEX in Spartan6.
p_rst_extender : process(wb_clk_i) p_rst_extender : process(wb_clk_i)
begin begin
if rising_edge(wb_clk_i) then if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then if wb_rst_i = '1' then
s_reset_extensor <= (others => '1'); reset_extender <= (others => '1');
else else
s_reset_extensor(0) <= '0'; reset_extender(0) <= '0';
for i in 1 to 2**c_RST_EXTENSOR -1 loop for i in 1 to 2**c_RST_EXTENSOR -1 loop
s_reset_extensor(i) <= s_reset_extensor(i-1); reset_extender(i) <= reset_extender(i-1);
end loop; end loop;
end if;
end if; end if;
end process; end if;
end process;
end Behavioral; end Behavioral;
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