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Conv TTL Blocking
Commit 2b19b902 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Removed pcb folder, relevant files moved to hardware subproject

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pcb/EDA-02446-V2-1_project/EDA-02446-V2-1.Annotation deleted 100644 → 0
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pcb/EDA-02446-V2-1_project/EDA-02446-V2-1.PrjPcb deleted 100644 → 0
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pcb/EDA-02452-V2-0_project/EDA-02452-V2-0_project.Annotation deleted 100644 → 0
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[SheetNumberManager]
SheetNumberOrder=Display Order
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pcb/EDA-02453-V1-0_project/EDA-02453-V1-0_project.PrjPCBStructure deleted 100644 → 0
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Record=SheetSymbol|SourceDocument=RTMP_top.SchDoc|Designator=U_Panel|SchDesignator=U_Panel|FileName=Panel.SchDoc|SymbolType=Normal|RawFileName=Panel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=RTMP_top.SchDoc|Designator=U_SqConnector|SchDesignator=U_SqConnector|FileName=SqConnector.SchDoc|SymbolType=Normal|RawFileName=SqConnector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=RTMP_top.SchDoc
pcb/README.txt deleted 100644 → 0
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EDA-02446-V2-1 CONV-TTL-BLO (blocking front module)
EDA-02452-V2-0 CONV-TTL_RTM (rear transition module)
EDA-02453-V1-0 CONV-TTL-RTM-BLO (piggyback on RTM)
PDF schematics files for each board can be found in its respective directory.
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.DRL deleted 100644 → 0
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TT#v 2 s k #v 2 sk #v 2 sk #v 2 sk # 7 8 7 8 7 7 7 8 7 7 7 7 8 7 # 7 8 7 7 7 7  7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7  7 7 7 7 7 7 7 7 7 7 8 8 8  8 7 7 7 8  7 7 8 7 7 8 7 7 7 8 8  8 7 7 8  7 8 7 8 7 7 8 8  8 7 7 7  7 8  7  7 7 8 7 7  7 8 7  7 7 7 8 8  8 7 7 7 7 7 7 8  7 7 7 7 7 8 7 7 7 7 7 8 7 7 7 7 7 7 7 8 7 8  7 8 7 7 7 7  7 7 7 7 7 7 8  7 7 7 7 7 7  7 7 8 7 7  7 7 7 7 7 7 8 7 7 7 7 7 7  7 7 7 8 8  8 7 8  8 8 # 7 8 7 # 7 8 7 7 T
\ No newline at end of file
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.DRR deleted 100644 → 0
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---------------------------------------------------------------------------
NCDrill File Report For: RTM_Interface_Tester.PcbDoc 5/14/2013 12:53:44 PM
---------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : RTM_Interface_Tester.TXT
EIA File : RTM_Interface_Tester.DRL
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.5mm (19.685mil) Round 10 148.01 mm (5.83 Inch)
T2 1mm (39.37mil) Round 160 485.14 mm (19.10 Inch)
T3 2.8mm (110.236mil) Round 2 88.90 mm (3.50 Inch)
T4 3mm (118.11mil) Round 3 90.00 mm (3.54 Inch)
---------------------------------------------------------------------------
Totals 175 812.05 mm (31.97 Inch)
Total Processing Time (hh:mm:ss) : 00:00:00
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.EXTREP deleted 100644 → 0
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------------------------------------------------------------------------------------------
Gerber File Extension Report For: RTM_Interface_Tester.GBR 5/14/2013 12:53:31 PM
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL Top Layer
.GBL Bottom Layer
.GTO Top Overlay
.GTS Top Solder
.GBS Bottom Solder
.GM1 Mechanical 1
.GM7 Mechanical 7
------------------------------------------------------------------------------------------
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.LDP deleted 100644 → 0
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Layer Pairs Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=rtm_interface_tester.txt|LayerPairs=gtl,gbl
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.RUL deleted 100644 → 0
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DRC Rules Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc
RuleKind=Width|RuleName=Width_GND|Scope=Board|Minimum=10.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width_Normal|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=6.69
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/Status Report.Txt deleted 100644 → 0
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Output: Bill of Materials
Type : BOM
From : Variant [[No Variations]] of Project [RTM_Interface_Tester.PrjPCB]
Files Generated : 0
Documents Printed : 0
Finished Output Generation At 10:21:06 AM On 7/1/2013
pcb/RTM_Interface_Tester/RTM_Interface_Tester.Dat deleted 100644 → 0
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Field=Description~String~Description~100|Field=Comment~String~Comment~100|Field=Designator~String~Designator~416|Field=Quantity~Integer~Quantity~100|ReportField=Currency~<none>|ReportField=ProductionQuantity~1|ReportField=ProjectFileName~RTM_Interface_Tester.PrjPCB|ReportField=ProjectFullPath~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.PrjPCB|ReportField=Title~Bill of Materials For Project [RTM_Interface_Tester.PrjPCB] (No PCB Document Selected)|ReportField=TotalQuantity~25|ReportField=ReportTime~10:21:21 AM|ReportField=ReportDate~7/1/2013|ReportField=ReportDateTime~7/1/2013 10:21:21 AM|ReportField=OutputName~Bill of Materials|ReportField=OutputType~BOM_PartType|ReportField=GeneratorName~BOM|ReportField=GeneratorDescription~Bill of Materials|ReportField=VariantName~None|ReportField=Address1~|ReportField=Address2~|ReportField=Address3~|ReportField=Address4~|ReportField=ApprovedBy~|ReportField=Author~|ReportField=CheckedBy~|ReportField=CheckedDate~-|ReportField=CompanyName~|ReportField=CreateDate~4/24/2013|ReportField=CurrentDate~7/1/2013|ReportField=CurrentTime~10:21:13 AM|ReportField=Date~|ReportField=Designer~Theodor-Adrian Stana|ReportField=DivGrp~BE/CO|ReportField=DocumentFullPathAndName~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.SchDoc|ReportField=DocumentName~RTM_Interface_Tester.SchDoc|ReportField=DocumentNumber~|ReportField=DrawnBy~Theodor-Adrian Stana|ReportField=EDA_Number~|ReportField=Engineer~Theodor-Adrian Stana|ReportField=ImagePath~|ReportField=ModifiedBy~-|ReportField=ModifiedDate~7/1/2013|ReportField=Organization~|ReportField=ProjectName~RTM_Interface_Tester.PrjPCB|ReportField=Projet~Blocking Pulse Repeater PTS|ReportField=Revision~|ReportField=Rule~|ReportField=SheetNumber~|ReportField=SheetTotal~|ReportField=Time~|ReportField=Title~PTS|ReportField=Title2~RTM Interface Tester|ReportField=DataSourceFileName~RTM_Interface_Tester.PrjPCB|ReportField=DataSourceFullPath~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.PrjPCB
Resistor - 0.1%|51|R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18|18
Connector 160zabcd Female (5x32)|HAR-BUS 64|P2|1
Transient Voltage Suppressor Diode (Bi-Directional)|SMBJ30CA|D1, D2, D3, D4, D5, D6|6
pcb/RTM_Interface_Tester/RTM_Interface_Tester.OutJob deleted 100644 → 0
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pcb/RTM_Interface_Tester/RTM_Interface_Tester.PrjPCB deleted 100644 → 0
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pcb/RTM_Interface_Tester/RTM_Interface_Tester.PrjPCBStructure deleted 100644 → 0
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Record=TopLevelDocument|FileName=RTM_Interface_Tester.SchDoc
pcb/RTM_Interface_Tester/RTM_Interface_Tester.SchDoc deleted 100644 → 0
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pcb/RTM_Interface_Tester/RTM_Interface_Tester_pcb-mat.pdf deleted 100644 → 0
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pcb/RTM_Interface_Tester/RTM_Interface_Tester_sch.pdf deleted 100644 → 0
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