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Conv TTL Blocking
Commit 3e012442 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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saving xise file

parent 6139b5e4
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hdl/IMAGES/FPGAbank.ucf
View file @ 3e012442
......@@ -7,10 +7,10 @@
#----------------------------------------
NET "CLK20_VCXO" LOC = E16;
NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
TIMESPEC TS_CLK20_VCXO = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
# NET "CLK20_VCXO" LOC = E16;
# NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
# NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
# TIMESPEC TS_CLK20_VCXO = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = G11;
NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
......
hdl/IMAGES/image1/project/image1.gise
View file @ 3e012442
......@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
......@@ -23,177 +23,58 @@
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="basic_trigger_top.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="i2c_slave_top.vhi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="image1_top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="image1_top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="image1_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="image1_top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="image1_top.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="image1_top.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="image1_top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="image1_top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="image1_top.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="image1_top_envsettings.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="image1_top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_ngdbuild.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="image1_top_summary.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="image1_top_tb.fdo"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="m25p32_top.vhi"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1355240543" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1355240543">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_top.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="239257099518693425" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3020523367752079697" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1355240543" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1355240543">
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_top.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1355302790" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1355302789">
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="image1_top_tb.fdo"/>
<outfile xil_pn:name="vsim.wlf"/>
<outfile xil_pn:name="work"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1353947909">
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354289325" xil_pn:in_ck="-545934943622296316" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1354289231">
<transform xil_pn:end_ts="1359734187" xil_pn:in_ck="-1823852009266447159" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1359734101">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="image1_top.lso"/>
<outfile xil_pn:name="image1_top.ngc"/>
......@@ -206,29 +87,23 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1354033300" xil_pn:in_ck="-7461616560160808584" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1354033300">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354033381" xil_pn:in_ck="4649869214785825988" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1354033375">
<transform xil_pn:end_ts="1359733124" xil_pn:in_ck="-6619133686387830372" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1359733124">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1354033402" xil_pn:in_ck="4649869214785825989" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1354033381">
<transform xil_pn:end_ts="1359734197" xil_pn:in_ck="5852800249754258408" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1359734187">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="image1_top.bld"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform>
</transforms>
......
hdl/IMAGES/image1/project/image1.xise
View file @ 3e012442
......@@ -9,86 +9,86 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../rtl/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
......@@ -96,73 +96,73 @@
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../constraints/FPGAbank.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../test/image1_top_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../test/image1_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../FPGAbank.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......@@ -280,6 +280,7 @@
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|image1_top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/image1_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/image1_top" xil_pn:valueState="non-default"/>
......@@ -320,6 +321,7 @@
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
......@@ -370,7 +372,7 @@
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="This is the project containing all the requiered functionality for Blocking board." xil_pn:valueState="non-default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -482,9 +484,7 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/image1_top" xil_pn:name="../constraints/FPGAbank.ucf"/>
</bindings>
<bindings/>
<libraries/>
......
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