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C
Conv TTL Blocking
Commit 3e012442 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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saving xise file

parent 6139b5e4
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hdl/IMAGES/FPGAbank.ucf
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......@@ -7,10 +7,10 @@
#----------------------------------------
NET "CLK20_VCXO" LOC = E16;
NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
TIMESPEC TS_CLK20_VCXO = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
# NET "CLK20_VCXO" LOC = E16;
# NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
# NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
# TIMESPEC TS_CLK20_VCXO = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = G11;
NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
......
hdl/IMAGES/image1/project/image1.gise
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hdl/IMAGES/image1/project/image1.xise
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