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Conv TTL Blocking
Commit 440a2d50 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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hdl/IMAGES/image1/constraints/V2/BloV2.ucf
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......@@ -7,17 +7,17 @@
##----------------------------------------
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVTTL";
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = "LVTTL";
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
NET "CLK20_VCXO" LOC = E16;
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "CLK20_VCXO" LOC = E16;
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
##======================================
......@@ -27,93 +27,93 @@ NET "FPGA_CLK_N" LOC = G11;
##--
##-- + UBT: LVTTL input
##-------------------
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = "LVTTL";
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = LVTTL;
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = LVTTL;
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = "LVTTL";
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = LVTTL;
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = LVTTL;
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = "LVTTL";
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = LVTTL;
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = "LVTTL";
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = LVTTL;
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = "LVTTL";
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = LVTTL;
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = LVTTL;
##-------------------
##-- Front channel LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_FRONT_LED_N[1]" LOC = H5;
NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[1]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[1]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[2]" LOC = J6;
NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[2]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[2]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[3]" LOC = K6;
NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[3]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[3]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[4]" LOC = K5;
NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[4]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[4]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[5]" LOC = M7;
NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[5]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[5]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[6]" LOC = M6;
NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[6]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[6]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[1]" LOC = H5;
NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[1]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[1]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[2]" LOC = J6;
NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[2]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[2]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[3]" LOC = K6;
NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[3]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[3]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[4]" LOC = K5;
NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[4]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[4]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[5]" LOC = M7;
NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[5]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[5]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[6]" LOC = M6;
NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[6]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[6]" SLEW = QUIETIO;
##-------------------
##-- Rear LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_REAR_LED_N[1]" LOC = AB17;
NET "PULSE_REAR_LED_N[1]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[1]" DRIVE = "4";
NET "PULSE_REAR_LED_N[1]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[2]" LOC = AB19;
NET "PULSE_REAR_LED_N[2]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[2]" DRIVE = "4";
NET "PULSE_REAR_LED_N[2]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[3]" LOC = AA16;
NET "PULSE_REAR_LED_N[3]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[3]" DRIVE = "4";
NET "PULSE_REAR_LED_N[3]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[4]" LOC = AA18;
NET "PULSE_REAR_LED_N[4]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[4]" DRIVE = "4";
NET "PULSE_REAR_LED_N[4]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[5]" LOC = AB16;
NET "PULSE_REAR_LED_N[5]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[5]" DRIVE = "4";
NET "PULSE_REAR_LED_N[5]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[6]" LOC = AB18;
NET "PULSE_REAR_LED_N[6]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[6]" DRIVE = "4";
NET "PULSE_REAR_LED_N[6]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[1]" LOC = AB17;
NET "PULSE_REAR_LED_N[1]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[1]" DRIVE = 4;
NET "PULSE_REAR_LED_N[1]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[2]" LOC = AB19;
NET "PULSE_REAR_LED_N[2]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[2]" DRIVE = 4;
NET "PULSE_REAR_LED_N[2]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[3]" LOC = AA16;
NET "PULSE_REAR_LED_N[3]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[3]" DRIVE = 4;
NET "PULSE_REAR_LED_N[3]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[4]" LOC = AA18;
NET "PULSE_REAR_LED_N[4]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[4]" DRIVE = 4;
NET "PULSE_REAR_LED_N[4]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[5]" LOC = AB16;
NET "PULSE_REAR_LED_N[5]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[5]" DRIVE = 4;
NET "PULSE_REAR_LED_N[5]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[6]" LOC = AB18;
NET "PULSE_REAR_LED_N[6]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[6]" DRIVE = 4;
NET "PULSE_REAR_LED_N[6]" SLEW = QUIETIO;
##-------------------
......@@ -121,30 +121,30 @@ NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "FPGA_INPUT_TTL_N[1]" LOC = T2;
NET "FPGA_INPUT_TTL_N[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[2]" LOC = U3;
NET "FPGA_INPUT_TTL_N[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[3]" LOC = V5;
NET "FPGA_INPUT_TTL_N[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[4]" LOC = W4;
NET "FPGA_INPUT_TTL_N[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[5]" LOC = T6;
NET "FPGA_INPUT_TTL_N[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[6]" LOC = T3;
NET "FPGA_INPUT_TTL_N[6]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[1]" LOC = C1;
NET "FPGA_OUT_TTL[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[2]" LOC = F2;
NET "FPGA_OUT_TTL[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[3]" LOC = F5;
NET "FPGA_OUT_TTL[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[4]" LOC = H4;
NET "FPGA_OUT_TTL[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[5]" LOC = J4;
NET "FPGA_OUT_TTL[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[6]" LOC = H2;
NET "FPGA_OUT_TTL[6]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[1]" LOC = T2;
NET "FPGA_INPUT_TTL_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_INPUT_TTL_N[2]" LOC = U3;
NET "FPGA_INPUT_TTL_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_INPUT_TTL_N[3]" LOC = V5;
NET "FPGA_INPUT_TTL_N[3]" IOSTANDARD = LVCMOS33;
NET "FPGA_INPUT_TTL_N[4]" LOC = W4;
NET "FPGA_INPUT_TTL_N[4]" IOSTANDARD = LVCMOS33;
NET "FPGA_INPUT_TTL_N[5]" LOC = T6;
NET "FPGA_INPUT_TTL_N[5]" IOSTANDARD = LVCMOS33;
NET "FPGA_INPUT_TTL_N[6]" LOC = T3;
NET "FPGA_INPUT_TTL_N[6]" IOSTANDARD = LVCMOS33;
NET "FPGA_OUT_TTL[1]" LOC = C1;
NET "FPGA_OUT_TTL[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_OUT_TTL[2]" LOC = F2;
NET "FPGA_OUT_TTL[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_OUT_TTL[3]" LOC = F5;
NET "FPGA_OUT_TTL[3]" IOSTANDARD = LVCMOS33;
NET "FPGA_OUT_TTL[4]" LOC = H4;
NET "FPGA_OUT_TTL[4]" IOSTANDARD = LVCMOS33;
NET "FPGA_OUT_TTL[5]" LOC = J4;
NET "FPGA_OUT_TTL[5]" IOSTANDARD = LVCMOS33;
NET "FPGA_OUT_TTL[6]" LOC = H2;
NET "FPGA_OUT_TTL[6]" IOSTANDARD = LVCMOS33;
##-------------------
##-- Bottomly allocated GPIOs
##--
......@@ -154,22 +154,22 @@ NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
NET "INV_IN_N[1]" LOC = V2;
NET "INV_IN_N[1]" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[2]" LOC = W3;
NET "INV_IN_N[2]" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[3]" LOC = Y2;
NET "INV_IN_N[3]" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[4]" LOC = AA2;
NET "INV_IN_N[4]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[1]" LOC = J3;
NET "INV_OUT[1]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[2]" LOC = L3;
NET "INV_OUT[2]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[3]" LOC = M3;
NET "INV_OUT[3]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[4]" LOC = P2;
NET "INV_OUT[4]" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[1]" LOC = V2;
NET "INV_IN_N[1]" IOSTANDARD = LVCMOS33;
NET "INV_IN_N[2]" LOC = W3;
NET "INV_IN_N[2]" IOSTANDARD = LVCMOS33;
NET "INV_IN_N[3]" LOC = Y2;
NET "INV_IN_N[3]" IOSTANDARD = LVCMOS33;
NET "INV_IN_N[4]" LOC = AA2;
NET "INV_IN_N[4]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[1]" LOC = J3;
NET "INV_OUT[1]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[2]" LOC = L3;
NET "INV_OUT[2]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[3]" LOC = M3;
NET "INV_OUT[3]" IOSTANDARD = LVCMOS33;
NET "INV_OUT[4]" LOC = P2;
NET "INV_OUT[4]" IOSTANDARD = LVCMOS33;
##======================================
......@@ -180,30 +180,30 @@ NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
NET "FPGA_BLO_IN[1]" LOC = Y9;
NET "FPGA_BLO_IN[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[2]" LOC = AA10;
NET "FPGA_BLO_IN[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[3]" LOC = W12;
NET "FPGA_BLO_IN[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[4]" LOC = AA6;
NET "FPGA_BLO_IN[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[5]" LOC = Y7;
NET "FPGA_BLO_IN[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[6]" LOC = AA8;
NET "FPGA_BLO_IN[6]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[1]" LOC = W9;
NET "FPGA_TRIG_BLO[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[2]" LOC = T10;
NET "FPGA_TRIG_BLO[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[3]" LOC = V7;
NET "FPGA_TRIG_BLO[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[4]" LOC = U9;
NET "FPGA_TRIG_BLO[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[5]" LOC = T8;
NET "FPGA_TRIG_BLO[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[6]" LOC = R9;
NET "FPGA_TRIG_BLO[6]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[1]" LOC = Y9;
NET "FPGA_BLO_IN[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_IN[2]" LOC = AA10;
NET "FPGA_BLO_IN[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_IN[3]" LOC = W12;
NET "FPGA_BLO_IN[3]" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_IN[4]" LOC = AA6;
NET "FPGA_BLO_IN[4]" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_IN[5]" LOC = Y7;
NET "FPGA_BLO_IN[5]" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_IN[6]" LOC = AA8;
NET "FPGA_BLO_IN[6]" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_BLO[1]" LOC = W9;
NET "FPGA_TRIG_BLO[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_BLO[2]" LOC = T10;
NET "FPGA_TRIG_BLO[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_BLO[3]" LOC = V7;
NET "FPGA_TRIG_BLO[3]" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_BLO[4]" LOC = U9;
NET "FPGA_TRIG_BLO[4]" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_BLO[5]" LOC = T8;
NET "FPGA_TRIG_BLO[5]" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_BLO[6]" LOC = R9;
NET "FPGA_TRIG_BLO[6]" IOSTANDARD = LVCMOS33;
##======================================
##-- VME CONNECTOR SIGNALS
......@@ -212,55 +212,55 @@ NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
##--
##-- + UBT: LVTTL input
##-------------------
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = "LVTTL";
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = "LVTTL";
NET "SCL_O" DRIVE = "4";
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = "LVTTL";
NET "SCL_OE" DRIVE = "4";
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = LVTTL;
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = LVTTL;
NET "SCL_O" DRIVE = 4;
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = LVTTL;
NET "SCL_OE" DRIVE = 4;
# NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = "LVTTL";
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = "LVTTL";
NET "SDA_O" SLEW = "FAST";
NET "SDA_O" DRIVE = "4";
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = LVTTL;
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = LVTTL;
NET "SDA_O" SLEW = FAST;
NET "SDA_O" DRIVE = 4;
# NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = "LVTTL";
NET "SDA_OE" SLEW = "FAST";
NET "SDA_OE" DRIVE = "4";
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = LVTTL;
NET "SDA_OE" SLEW = FAST;
NET "SDA_OE" DRIVE = 4;
# NET "SDA_OE" PULLDOWN;
##-------------------
##-- Geographical Address
##--
##-- + UBT: LVTTL input
##-------------------
NET "FPGA_GA[0]" LOC = H20;
NET "FPGA_GA[0]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[1]" LOC = J20;
NET "FPGA_GA[1]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[2]" LOC = K19;
NET "FPGA_GA[2]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[3]" LOC = K20;
NET "FPGA_GA[3]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[4]" LOC = L19;
NET "FPGA_GA[4]" IOSTANDARD = "LVTTL";
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = "LVTTL";
NET "FPGA_GA[0]" LOC = H20;
NET "FPGA_GA[0]" IOSTANDARD = LVTTL;
NET "FPGA_GA[1]" LOC = J20;
NET "FPGA_GA[1]" IOSTANDARD = LVTTL;
NET "FPGA_GA[2]" LOC = K19;
NET "FPGA_GA[2]" IOSTANDARD = LVTTL;
NET "FPGA_GA[3]" LOC = K20;
NET "FPGA_GA[3]" IOSTANDARD = LVTTL;
NET "FPGA_GA[4]" LOC = L19;
NET "FPGA_GA[4]" IOSTANDARD = LVTTL;
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = LVTTL;
##-------------------
##-- ROM memory
##-------------------
NET "FPGA_PROM_CCLK" LOC = Y20;
NET "FPGA_PROM_CCLK" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_CSO_B_N" LOC = AA3;
NET "FPGA_PROM_CSO_B_N" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_DIN" LOC = AA20;
NET "FPGA_PROM_DIN" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_MOSI" LOC = AB20;
NET "FPGA_PROM_MOSI" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_CCLK" LOC = Y20;
NET "FPGA_PROM_CCLK" IOSTANDARD = LVTTL;
NET "FPGA_PROM_CSO_B_N" LOC = AA3;
NET "FPGA_PROM_CSO_B_N" IOSTANDARD = LVTTL;
NET "FPGA_PROM_DIN" LOC = AA20;
NET "FPGA_PROM_DIN" IOSTANDARD = LVTTL;
NET "FPGA_PROM_MOSI" LOC = AB20;
NET "FPGA_PROM_MOSI" IOSTANDARD = LVTTL;
###======================================
......@@ -328,30 +328,30 @@ NET "FPGA_PROM_MOSI" LOC = AB20;
##--
##-- + HC CMOS 3.3V input
##-------------------
NET "FPGA_OE" LOC = R3;
NET "FPGA_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_OE" DRIVE = "4";
NET "FPGA_OE" SLEW = "QUIETIO";
NET "FPGA_BLO_OE" LOC = P5;
NET "FPGA_BLO_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_OE" DRIVE = "4";
NET "FPGA_BLO_OE" SLEW = "QUIETIO";
NET "FPGA_TRIG_TTL_OE" LOC = N3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_TTL_OE" DRIVE = "4";
NET "FPGA_TRIG_TTL_OE" SLEW = "QUIETIO";
NET "FPGA_INV_OE" LOC = P6;
NET "FPGA_INV_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_INV_OE" DRIVE = "4";
NET "FPGA_INV_OE" SLEW = "QUIETIO";
NET "FPGA_OE" LOC = R3;
NET "FPGA_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_OE" DRIVE = 4;
NET "FPGA_OE" SLEW = QUIETIO;
NET "FPGA_BLO_OE" LOC = P5;
NET "FPGA_BLO_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_OE" DRIVE = 4;
NET "FPGA_BLO_OE" SLEW = QUIETIO;
NET "FPGA_TRIG_TTL_OE" LOC = N3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_TTL_OE" DRIVE = 4;
NET "FPGA_TRIG_TTL_OE" SLEW = QUIETIO;
NET "FPGA_INV_OE" LOC = P6;
NET "FPGA_INV_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_INV_OE" DRIVE = 4;
NET "FPGA_INV_OE" SLEW = QUIETIO;
##-------------------
##-- Configuration Switches
##
##-- Schematics name EXTRA_SWITCH_*
##---- renamed to EXTRA_SWITCH[*]
##-------------------
NET "EXTRA_SWITCH[1]" LOC = F22;
NET "EXTRA_SWITCH[1]" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[1]" LOC = F22;
NET "EXTRA_SWITCH[1]" IOSTANDARD = LVCMOS33;
# NET "EXTRA_SWITCH[2]" LOC = G22;
# NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[3]" LOC = H21;
......@@ -364,25 +364,25 @@ NET "FPGA_INV_OE" LOC = P6;
# NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[7]" LOC = K22;
# NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVCMOS33";
NET "LEVEL" LOC = L22;
NET "LEVEL" IOSTANDARD = "LVCMOS33";
NET "LEVEL" LOC = L22;
NET "LEVEL" IOSTANDARD = LVCMOS33;
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
###-------------------
###-- General purpose
###--
......@@ -412,3 +412,174 @@ NET "LEVEL" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[5]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[6]" LOC = B20;
# NET "FPGA_HEADER_IN_N[6]" IOSTANDARD = "LVCMOS33";
NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[5]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[4]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[3]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[2]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[1]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[0]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[5]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[4]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[3]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[2]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[1]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[0]" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_cyc_i" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_stb_i" KEEP = "TRUE";
NET "inst_image1_core/cmp_test_trigleds/wb_we_i" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[31]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[30]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[29]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[28]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[27]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[26]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[25]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[24]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[23]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[22]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[21]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[20]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[19]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[18]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[17]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[16]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[15]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[14]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[13]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[12]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[11]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[10]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[9]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[8]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[7]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[6]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[5]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[4]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[3]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[2]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[1]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[0]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[31]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[30]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[29]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[28]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[27]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[26]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[25]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[24]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[23]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[22]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[21]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[20]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[19]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[18]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[17]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[16]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[15]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[14]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[13]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[12]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[11]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[10]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[9]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[8]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[7]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[6]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[5]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[4]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[3]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[2]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[1]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[0]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[3]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[2]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[1]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[0]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[31]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[30]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[29]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[28]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[27]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[26]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[25]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[24]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[23]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[22]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[21]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[20]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[19]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[18]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[17]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[16]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[15]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[14]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[13]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[12]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[11]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[10]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[9]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[8]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[7]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[6]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[5]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[4]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[3]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[2]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[1]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[0]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[15]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[14]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[13]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[12]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[11]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[10]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[9]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[8]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[7]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[6]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[5]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[4]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[3]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[2]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[1]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[0]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[31]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[30]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[29]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[28]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[27]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[26]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[25]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[24]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[23]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[22]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[21]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[20]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[19]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[18]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[17]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[16]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[15]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[14]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[13]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[12]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[11]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[10]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[9]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[8]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[7]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[6]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[5]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[4]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[3]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[2]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[1]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[0]" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_ack_i" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_cyc_o" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_stb_o" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_master_we_o" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_ack_o" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_cyc_i" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_stb_i" KEEP = "TRUE";
NET "inst_image1_core/inst_i2c_slave/wb_slave_we_i" KEEP = "TRUE";
hdl/IMAGES/image1/project/image1.gise
View file @ 440a2d50
......@@ -22,309 +22,9 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="image1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="i2c_master_driver.fdo"/>
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<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1360658811" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1360658804">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="image1_top.twr"/>
<outfile xil_pn:name="image1_top.twx"/>
</transform>
</transforms>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 440a2d50
......@@ -265,8 +265,10 @@ begin
-- !!!!!
led_front_n <= leds_from_trig or (not trigleds);
-- led_front_n <= leds_from_trig or (not trigleds);
led_front_n(1) <= not s_master_i(c_slave_trigleds_wb).ack;
led_front_n(2) <= not s_master_i(c_slave_i2c_slave).ack;
led_front_n(6 downto 3) <= (others => '1');
......
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