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Conv TTL Blocking
Commit 44b0a8e9 authored by gilsoriano's avatar gilsoriano
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Added all the SPI modes of operation. CPOL=1 CPHA=0 still needs work to do.

parent 470753fc
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Showing with 386 additions and 189 deletions
hdl/ctdah_lib/rtl/FIFO_dispatcher.vhd
View file @ 44b0a8e9
......@@ -74,9 +74,12 @@ begin
if oen_i = '1' then
reg_o <= reg_int(g_dispatcher_depth -1);
for i in 0 to g_dispatcher_depth - 2 loop
reg_int(i+1) <= reg_int(i);
end loop;
if g_dispatcher_depth > 1 then --
for i in 0 to g_dispatcher_depth - 2 loop
reg_int(i+1) <= reg_int(i);
end loop;
else --
end if; --
reg_int(0) <= (others => '0');
else
end if;
......
hdl/ctdah_lib/rtl/gc_clk_divider.vhd
View file @ 44b0a8e9
......@@ -79,7 +79,7 @@ begin
else
end if;
else
s_clk_o <= '0';
-- s_clk_o <= '0';
end if;
end if;
else
......
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @ 44b0a8e9
......@@ -50,14 +50,18 @@ package spi_master_pkg is
-- Wishbone access: Write-read
----------------------------------------
-- BIT NAME DESCRIPTION
-- 4-0 x Reserved
-- 0 CPOL Clock POLarity when idle
-- 1 CPHA Clock PHAse
-- 4-2 x Reserved
-- 13-5 BDATA Bytes of DATA to be sent
-- 22-14 BADDR Bytes of ADDRess to be sent
-- 31-23 BINST Bytes of INSTruction to be sent
----------------------------------------
type r_SPI0 is
record
x : STD_LOGIC_VECTOR (4 downto 0);
CPOL : STD_LOGIC;
CPHA : STD_LOGIC;
x : STD_LOGIC_VECTOR (4 downto 2);
BDATA : UNSIGNED (13 downto 5);
BADDR : UNSIGNED (22 downto 14);
BINST : UNSIGNED (31 downto 23);
......@@ -128,7 +132,9 @@ package spi_master_pkg is
constant c_ADDR_LENGTH : NATURAL := 3;
constant c_DATA_LENGTH : NATURAL := 256;
constant c_SPI0_default : r_SPI0 := (x => (others => '0'),
constant c_SPI0_default : r_SPI0 := (CPOL => '0',
CPHA => '0',
x => (others => '0'),
BDATA => to_unsigned(c_DATA_LENGTH, r_SPI0.BDATA'length),
BADDR => to_unsigned(c_ADDR_LENGTH, r_SPI0.BADDR'length),
BINST => to_unsigned(c_INST_LENGTH, r_SPI0.BINST'length));
......@@ -198,7 +204,9 @@ package body spi_master_pkg is
return ( std_logic_vector(r_register.BINST)
& std_logic_vector(r_register.BADDR)
& std_logic_vector(r_register.BDATA)
& r_register.x);
& r_register.x
& r_register.CPHA
& r_register.CPOL);
end f_STD_LOGIC_VECTOR;
......@@ -209,7 +217,9 @@ package body spi_master_pkg is
function f_SPI0 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0)) return r_SPI0 is
variable v_SPI0 : r_SPI0;
begin
v_SPI0.x := r_register(4 downto 0);
v_SPI0.CPOL := r_register(0);
v_SPI0.CPHA := r_register(1);
v_SPI0.x := r_register(4 downto 2);
v_SPI0.BDATA := unsigned(r_register(13 downto 5));
v_SPI0.BADDR := unsigned(r_register(22 downto 14));
v_SPI0.BINST := unsigned(r_register(31 downto 23));
......
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