Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL Blocking
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL Blocking
Commits
4c3d7df3
Commit
4c3d7df3
authored
May 28, 2013
by
Theodor-Adrian Stana
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Changed some formatting in top-level PTS and doc .gitignore
parent
706c104c
Show whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
61 additions
and
248 deletions
+61
-248
.gitignore
hdl/pts/doc/.gitignore
+0
-3
conv_ttl_blo_v2.bit
hdl/pts/syn/conv_ttl_blo_v2.bit
+0
-0
conv_ttl_blo_v2.gise
hdl/pts/syn/conv_ttl_blo_v2.gise
+14
-14
conv_ttl_blo_v2.vhd
hdl/pts/top/conv_ttl_blo_v2.vhd
+47
-49
conv_ttl_blo_v2.gise
hdl/release/syn/conv_ttl_blo_v2.gise
+0
-180
run.tcl
hdl/release/syn/run.tcl
+0
-2
No files found.
hdl/pts/doc/.gitignore
View file @
4c3d7df3
build/
fig/
*.tex
*.bib
hdl/pts/syn/conv_ttl_blo_v2.bit
View file @
4c3d7df3
No preview for this file type
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @
4c3d7df3
...
...
@@ -72,35 +72,35 @@
</files>
<transforms
xmlns=
"http://www.xilinx.com/XMLSchema"
>
<transform
xil_pn:end_ts=
"136
7594725"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807798"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594725"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"3482918740615751616"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807798"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"3482918740615751616"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594725"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-1032337062829449789"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807798"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-1032337062829449789"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594725"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807798"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594725"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"6739244360423696002"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807798"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"6739244360423696002"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594725"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807798"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594725"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"-5613713180460514355"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807798"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"-5613713180460514355"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594790"
xil_pn:in_ck=
"2106099442498953536"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"-5659100974288834190"
xil_pn:start_ts=
"1367594725
"
>
<transform
xil_pn:end_ts=
"136
8807863"
xil_pn:in_ck=
"2106099442498953536"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"-5659100974288834190"
xil_pn:start_ts=
"1368807798
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
...
...
@@ -118,11 +118,11 @@
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
<outfile
xil_pn:name=
"xst"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594790"
xil_pn:in_ck=
"9180755367508499589"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"1934330619683713069"
xil_pn:start_ts=
"1367594790
"
>
<transform
xil_pn:end_ts=
"136
8807863"
xil_pn:in_ck=
"9180755367508499589"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"1934330619683713069"
xil_pn:start_ts=
"1368807863
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7594804"
xil_pn:in_ck=
"618428940982703508"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"7619738475395271108"
xil_pn:start_ts=
"1367594790
"
>
<transform
xil_pn:end_ts=
"136
8807876"
xil_pn:in_ck=
"618428940982703508"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"7619738475395271108"
xil_pn:start_ts=
"1368807863
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_ngo"
/>
...
...
@@ -131,7 +131,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ngd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_ngdbuild.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7595026"
xil_pn:in_ck=
"-3184428132143472968"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1367594804
"
>
<transform
xil_pn:end_ts=
"136
8808087"
xil_pn:in_ck=
"-3184428132143472968"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1368807876
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
...
...
@@ -145,7 +145,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo_v2_summary.xml"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_usage.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7595128"
xil_pn:in_ck=
"-7407895592276768303"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1367595026
"
>
<transform
xil_pn:end_ts=
"136
8808177"
xil_pn:in_ck=
"-7407895592276768303"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1368808087
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
...
...
@@ -159,7 +159,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo_v2_pad.txt"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_par.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7595168"
xil_pn:in_ck=
"-7071212854459536945"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1367595128
"
>
<transform
xil_pn:end_ts=
"136
8808215"
xil_pn:in_ck=
"-7071212854459536945"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1368808177
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
...
...
@@ -171,7 +171,7 @@
<outfile
xil_pn:name=
"webtalk.log"
/>
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"136
7595128"
xil_pn:in_ck=
"-3184428132143473100"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1367595111
"
>
<transform
xil_pn:end_ts=
"136
8808177"
xil_pn:in_ck=
"-3184428132143473100"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1368808160
"
>
<status
xil_pn:value=
"FailedRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/trce.xmsgs"
/>
...
...
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @
4c3d7df3
...
...
@@ -165,15 +165,15 @@ architecture behav of conv_ttl_blo_v2 is
-- Constant declarations
--============================================================================
-- Test number constants
constant
c_test_
thermo
:
natural
:
=
2
;
constant
c_test_
ttl
:
natural
:
=
4
;
constant
c_test_
blo_1
:
natural
:
=
6
;
constant
c_test_
blo_2
:
natural
:
=
7
;
constant
c_test_
pll
:
natural
:
=
8
;
constant
c_test_
sfp_eeprom
:
natural
:
=
10
;
constant
c_test_
sfp
:
natural
:
=
12
;
constant
c_test_
led_1
:
natural
:
=
14
;
constant
c_test_
led_2
:
natural
:
=
15
;
constant
c_test_
led_1
:
natural
:
=
2
;
constant
c_test_
led_2
:
natural
:
=
3
;
constant
c_test_
thermo
:
natural
:
=
4
;
constant
c_test_
ttl
:
natural
:
=
6
;
constant
c_test_
blo_1
:
natural
:
=
8
;
constant
c_test_
blo_2
:
natural
:
=
9
;
constant
c_test_
pll
:
natural
:
=
10
;
constant
c_test_
sfp_eeprom
:
natural
:
=
12
;
constant
c_test_
sfp
:
natural
:
=
14
;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
...
...
@@ -746,7 +746,7 @@ begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf
:
IBUFDS
cmp_125_diff_buf
:
IBUFDS
generic
map
(
DIFF_TERM
=>
TRUE
,
...
...
@@ -763,7 +763,7 @@ begin
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen
:
reset_gen
cmp_reset_gen
:
reset_gen
generic
map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
...
...
@@ -784,7 +784,7 @@ begin
--============================================================================
i2c_addr
<=
"10"
&
fpga_ga_i
;
cmp_i2c_bridge
:
vme64x_i2c
cmp_i2c_bridge
:
vme64x_i2c
port
map
(
-- Clock, reset
...
...
@@ -820,7 +820,7 @@ begin
-- of the front module. The I2C_UP signal is permanently set once an
-- I2C transfer has successfully completed, as signaled by the RD_DONE
-- and WR_DONE outputs of the I2C slave.
p_i2c_up
:
process
(
clk125
)
is
p_i2c_up
:
process
(
clk125
)
is
begin
if
rising_edge
(
clk125
)
then
if
(
rst_n
=
'0'
)
then
...
...
@@ -837,7 +837,7 @@ begin
xbar_master_in
(
0
)
.
int
<=
'0'
;
xbar_master_in
(
0
)
.
err
<=
'0'
;
cmp_wb_crossbar
:
xwb_crossbar
cmp_wb_crossbar
:
xwb_crossbar
generic
map
(
g_num_masters
=>
c_nr_masters
,
...
...
@@ -864,7 +864,7 @@ begin
switches
<=
ttl_switch_n_i
&
extra_switch_n_i
;
-- Regs to test I2C operation
cmp_pts_regs
:
pts_regs
cmp_pts_regs
:
pts_regs
port
map
(
rst_n_i
=>
rst_n
,
...
...
@@ -910,7 +910,7 @@ begin
-- below:
--
-- test07 Increment LED sequence every time interval.
p_fsm
:
process
(
clk125
)
is
p_fsm
:
process
(
clk125
)
is
begin
if
rising_edge
(
clk125
)
then
if
(
rst_n
=
'0'
)
then
...
...
@@ -945,7 +945,7 @@ begin
end
if
;
end
if
;
when
ST_LEDTEST_2
=>
when
others
=>
cnt_halfsec
<=
cnt_halfsec
+
1
;
if
(
cnt_halfsec
=
62499999
)
then
cnt_halfsec
<=
(
others
=>
'0'
);
...
...
@@ -955,8 +955,6 @@ begin
end
if
;
end
if
;
when
others
=>
null
;
end
case
;
end
if
;
...
...
@@ -968,7 +966,7 @@ begin
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master
:
wb_onewire_master
cmp_onewire_master
:
wb_onewire_master
generic
map
(
g_interface_mode
=>
CLASSIC
,
...
...
@@ -1008,7 +1006,7 @@ begin
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe
:
process
(
clk125
)
p_oe
:
process
(
clk125
)
begin
if
rising_edge
(
clk125
)
then
if
(
rst_n
=
'0'
)
then
...
...
@@ -1040,7 +1038,7 @@ begin
-- width, to generate the output pulse from CH10 (INV-TTL CH4) to CH1
--
-- 1-us pulses are generated twice a second.
cmp_first_pulse_gen
:
pulse_gen
cmp_first_pulse_gen
:
pulse_gen
generic
map
(
g_pwidth
=>
125
,
...
...
@@ -1056,7 +1054,7 @@ begin
);
-- Assign the trigger inputs to internal signals
ttl_trigs
(
6
downto
1
)
<=
not
fpga_input_ttl_n_i
;
ttl_trigs
(
6
downto
1
)
<=
not
fpga_input_ttl_n_i
;
ttl_trigs
(
10
downto
7
)
<=
not
inv_in_n_i
;
-- Now, generate nine pulse generator blocks connected to the TTL outputs
...
...
@@ -1068,8 +1066,8 @@ begin
--
-- Type 1 pulses (non-glich-filtered) with 1us width will be generated by
-- the generator blocks.
gen_ttl_pulse_gens
:
for
i
in
1
to
9
generate
cmp_ttl_pulse_gen
:
pulse_generator
gen_ttl_pulse_gens
:
for
i
in
1
to
9
generate
cmp_ttl_pulse_gen
:
pulse_generator
generic
map
(
g_pulse_width
=>
125
,
...
...
@@ -1079,8 +1077,8 @@ begin
(
clk_i
=>
clk125
,
rst_n_i
=>
rst_n
,
pulse_type_i
=>
ttl_pulse_en
,
en_i
=>
'1'
,
pulse_type_i
=>
'1'
,
en_i
=>
ttl_pulse_en
,
trig_i
=>
ttl_trigs
(
i
),
pulse_o
=>
ttl_pulses
(
i
)
);
...
...
@@ -1094,7 +1092,7 @@ begin
-- Process to count input and output pulses. Since the pulses are generated
-- on the rising edge of the input pulse, the outputs from the pulse_generator
-- blocks need to be resynced.
p_cnt_ttl_pulses
:
process
(
clk125
)
is
p_cnt_ttl_pulses
:
process
(
clk125
)
is
begin
if
rising_edge
(
clk125
)
then
if
(
rst_n
=
'0'
)
then
...
...
@@ -1136,8 +1134,8 @@ begin
-- are time-domain multiplexed, each channel outputting a pulse 100 ms after
-- the other. Blocking CH1 will output a pulse at 0 ms, CH2 at 100 ms, CH3 at
-- 200 ms, and so on.
gen_blo_pulse_gen
:
for
i
in
1
to
6
generate
cmp_blo_pulse_gen
:
pulse_gen
gen_blo_pulse_gen
:
for
i
in
1
to
6
generate
cmp_blo_pulse_gen
:
pulse_gen
generic
map
(
g_pwidth
=>
125
,
...
...
@@ -1161,7 +1159,7 @@ begin
-- Process to count input and output pulses. Since the pulses are generated
-- on the rising edge of the input pulse, the outputs from the pulse_generator
-- blocks need to be resynced.
p_cnt_blo_pulses
:
process
(
clk125
)
is
p_cnt_blo_pulses
:
process
(
clk125
)
is
begin
if
rising_edge
(
clk125
)
then
if
(
rst_n
=
'0'
)
then
...
...
@@ -1196,8 +1194,8 @@ begin
end
process
p_cnt_blo_pulses
;
-- Uncomment following lines to debug BLO pulse output
-- gen_pulse_leds: for i in 1 to 6 generate
-- cmp_pulse_led_gen: pulse_gen
-- gen_pulse_leds
: for i in 1 to 6 generate
-- cmp_pulse_led_gen
: pulse_gen
-- generic map
-- (
-- g_pwidth => 12*(10**6),
...
...
@@ -1219,7 +1217,7 @@ begin
-- Pulse counter registers, holding values for pulse counters of both blocking
-- and TTL pulse repetition tests.
--============================================================================
cmp_pulse_cnt_wb
:
pulse_cnt_wb
cmp_pulse_cnt_wb
:
pulse_cnt_wb
port
map
(
rst_n_i
=>
rst_n
,
...
...
@@ -1282,7 +1280,7 @@ begin
cnt125_actual_rst
<=
cnt125_rst
or
rst
;
-- Instantiate increment counter for IC13
cmp_pll125_incr_counter
:
incr_counter
cmp_pll125_incr_counter
:
incr_counter
generic
map
(
width
=>
32
...
...
@@ -1298,7 +1296,7 @@ begin
);
-- Instantiate clock info slave
cmp_pll125_clk_info
:
clk_info_wb_slave
cmp_pll125_clk_info
:
clk_info_wb_slave
port
map
(
wb_clk_i
=>
clk125
,
...
...
@@ -1321,7 +1319,7 @@ begin
);
-- Instantate a Wishbone SPI module to control IC18 DAC operation
cmp_dac_125_spi
:
wb_spi
cmp_dac_125_spi
:
wb_spi
generic
map
(
g_interface_mode
=>
CLASSIC
,
...
...
@@ -1357,7 +1355,7 @@ begin
-- 20-MHz VCXO test
-----------------------------------------------------------------------------
-- First, synchronize the reset signal into the 20 MHz clock domain
p_sync_rst
:
process
(
clk20_vcxo_i
)
p_sync_rst
:
process
(
clk20_vcxo_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
cnt20_actual_rst_d0
<=
cnt20_rst
;
...
...
@@ -1366,7 +1364,7 @@ begin
end
process
p_sync_rst
;
-- Then, instantiate increment counter for VCXO OSC1
cmp_vcxo20_incr_counter
:
incr_counter
cmp_vcxo20_incr_counter
:
incr_counter
generic
map
(
width
=>
32
...
...
@@ -1382,7 +1380,7 @@ begin
);
-- Instantiate clock info slave
cmp_vcxo20_clk_info
:
clk_info_wb_slave
cmp_vcxo20_clk_info
:
clk_info_wb_slave
port
map
(
wb_clk_i
=>
clk125
,
...
...
@@ -1405,7 +1403,7 @@ begin
);
-- Instantate a Wishbone SPI module to control IC18 DAC operation
cmp_dac_20_spi
:
wb_spi
cmp_dac_20_spi
:
wb_spi
generic
map
(
g_interface_mode
=>
CLASSIC
,
...
...
@@ -1437,7 +1435,7 @@ begin
-- Finally, assign the SYNC_N output to the DAC
fpga_plldac2_sync_n_o
<=
plldac2_sync_n
(
0
);
p_shift_front_leds
:
process
(
clk125
)
is
p_shift_front_leds
:
process
(
clk125
)
is
begin
if
rising_edge
(
clk125
)
then
if
(
rst_n
=
'0'
)
then
...
...
@@ -1454,7 +1452,7 @@ begin
-- * test J1 SFP connector using an SFP loopback module
--============================================================================
-- First, instantiate an I2C master to handle SFP communication
cmp_sfp_eeprom_i2c
:
wb_i2c_master
cmp_sfp_eeprom_i2c
:
wb_i2c_master
generic
map
(
g_interface_mode
=>
CLASSIC
,
...
...
@@ -1492,7 +1490,7 @@ begin
-- * test J1 SFP connector using an SFP loopback module
--============================================================================
-- First, instantiate an IBUFGDS for MGT clock
cmp_mgt_clk_ibufds
:
IBUFDS
cmp_mgt_clk_ibufds
:
IBUFDS
generic
map
(
DIFF_TERM
=>
true
,
...
...
@@ -1507,7 +1505,7 @@ begin
);
-- Connect the MINIC module to the crossbar
cmp_sfp_minic
:
xwr_mini_nic
cmp_sfp_minic
:
xwr_mini_nic
generic
map
(
g_interface_mode
=>
CLASSIC
,
...
...
@@ -1537,7 +1535,7 @@ begin
);
-- Connect the endpoint buffer RAM
cmp_sfp_dpram
:
generic_dpram
cmp_sfp_dpram
:
generic_dpram
generic
map
(
g_data_width
=>
32
,
...
...
@@ -1567,7 +1565,7 @@ begin
xbar_master_out
(
c_slv_dpram
)
.
we
;
-- Connect the Endpoint module to the crossbar
cmp_sfp_endpoint
:
xwr_endpoint
cmp_sfp_endpoint
:
xwr_endpoint
generic
map
(
g_interface_mode
=>
CLASSIC
,
...
...
@@ -1616,7 +1614,7 @@ begin
);
-- Finally, connect the GTP transceiver to the endpoint signals
cmp_gtp_xceiver
:
wr_gtp_phy_spartan6
cmp_gtp_xceiver
:
wr_gtp_phy_spartan6
generic
map
(
g_simulation
=>
0
,
...
...
@@ -1718,7 +1716,7 @@ begin
-- Then, we instantiate the LED controller and control it via the LED state
-- vector.
cmp_bicolor_led_ctrl
:
bicolor_led_ctrl
cmp_bicolor_led_ctrl
:
bicolor_led_ctrl
generic
map
(
g_NB_COLUMN
=>
6
,
...
...
hdl/release/syn/conv_ttl_blo_v2.gise
deleted
100644 → 0
View file @
706c104c
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project
xmlns=
"http://www.xilinx.com/XMLSchema"
xmlns:xil_pn=
"http://www.xilinx.com/XMLSchema"
>
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version
xmlns=
"http://www.xilinx.com/XMLSchema"
>
11.1
</version>
<sourceproject
xmlns=
"http://www.xilinx.com/XMLSchema"
xil_pn:fileType=
"FILE_XISE"
xil_pn:name=
"conv_ttl_blo_v2.xise"
/>
<files
xmlns=
"http://www.xilinx.com/XMLSchema"
>
<file
xil_pn:fileType=
"FILE_DIRECTORY"
xil_pn:name=
"_ngo"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/bitgen.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/ngdbuild.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/trce.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/xst.xmsgs"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BITGEN_REPORT"
xil_pn:name=
"conv_ttl_blo_v2.bgn"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BIT"
xil_pn:name=
"conv_ttl_blo_v2.bit"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGDBUILD_LOG"
xil_pn:name=
"conv_ttl_blo_v2.bld"
/>
<file
xil_pn:fileType=
"FILE_CMD_LOG"
xil_pn:name=
"conv_ttl_blo_v2.cmd_log"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BITGEN_DRC"
xil_pn:name=
"conv_ttl_blo_v2.drc"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_LSO"
xil_pn:name=
"conv_ttl_blo_v2.lso"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NCD"
xil_pn:name=
"conv_ttl_blo_v2.ncd"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGC"
xil_pn:name=
"conv_ttl_blo_v2.ngc"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGD"
xil_pn:name=
"conv_ttl_blo_v2.ngd"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGR"
xil_pn:name=
"conv_ttl_blo_v2.ngr"
/>
<file
xil_pn:fileType=
"FILE_PAD_MISC"
xil_pn:name=
"conv_ttl_blo_v2.pad"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PAR_REPORT"
xil_pn:name=
"conv_ttl_blo_v2.par"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PCF"
xil_pn:name=
"conv_ttl_blo_v2.pcf"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST_PROJECT"
xil_pn:name=
"conv_ttl_blo_v2.prj"
/>
<file
xil_pn:fileType=
"FILE_TRCE_MISC"
xil_pn:name=
"conv_ttl_blo_v2.ptwx"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST_STX"
xil_pn:name=
"conv_ttl_blo_v2.stx"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST_REPORT"
xil_pn:name=
"conv_ttl_blo_v2.syr"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_TIMING_TXT_REPORT"
xil_pn:name=
"conv_ttl_blo_v2.twr"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_TIMING_XML_REPORT"
xil_pn:name=
"conv_ttl_blo_v2.twx"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_UNROUTES"
xil_pn:name=
"conv_ttl_blo_v2.unroutes"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BITGEN_REPORT"
xil_pn:name=
"conv_ttl_blo_v2.ut"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:fileType=
"FILE_XPI"
xil_pn:name=
"conv_ttl_blo_v2.xpi"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST"
xil_pn:name=
"conv_ttl_blo_v2.xst"
/>
<file
xil_pn:fileType=
"FILE_NCD"
xil_pn:name=
"conv_ttl_blo_v2_guide.ncd"
xil_pn:origination=
"imported"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_MAP_REPORT"
xil_pn:name=
"conv_ttl_blo_v2_map.map"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_MAP_REPORT"
xil_pn:name=
"conv_ttl_blo_v2_map.mrp"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NCD"
xil_pn:name=
"conv_ttl_blo_v2_map.ncd"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGM"
xil_pn:name=
"conv_ttl_blo_v2_map.ngm"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"conv_ttl_blo_v2_map.xrpt"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"conv_ttl_blo_v2_ngdbuild.xrpt"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PAD_EXCEL_REPORT"
xil_pn:name=
"conv_ttl_blo_v2_pad.csv"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PAD_TXT_REPORT"
xil_pn:name=
"conv_ttl_blo_v2_pad.txt"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"conv_ttl_blo_v2_par.xrpt"
/>
<file
xil_pn:fileType=
"FILE_FITTER_REPORT"
xil_pn:name=
"conv_ttl_blo_v2_summary.xml"
/>
<file
xil_pn:fileType=
"FILE_WEBTALK"
xil_pn:name=
"conv_ttl_blo_v2_usage.xml"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"conv_ttl_blo_v2_xst.xrpt"
/>
<file
xil_pn:fileType=
"FILE_LOG"
xil_pn:name=
"webtalk.log"
/>
<file
xil_pn:fileType=
"FILE_FITTER_REPORT"
xil_pn:name=
"webtalk_pn.xml"
/>
<file
xil_pn:fileType=
"FILE_DIRECTORY"
xil_pn:name=
"xlnx_auto_0_xdb"
/>
<file
xil_pn:fileType=
"FILE_DIRECTORY"
xil_pn:name=
"xst"
/>
</files>
<transforms
xmlns=
"http://www.xilinx.com/XMLSchema"
>
<transform
xil_pn:end_ts=
"1366620438"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620438"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"3482918740615751616"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620438"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-1032337062829449789"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620438"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620438"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"6739244360423696002"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620438"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620438"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"-5613713180460514355"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620454"
xil_pn:in_ck=
"-88236163103343582"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"-5659100974288834190"
xil_pn:start_ts=
"1366620438"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_xmsgs/xst.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.lso"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ngc"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ngr"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.prj"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.stx"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.syr"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.xst"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_xst.xrpt"
/>
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
<outfile
xil_pn:name=
"xst"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620454"
xil_pn:in_ck=
"9180755367508499589"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"1934330619683713069"
xil_pn:start_ts=
"1366620454"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620465"
xil_pn:in_ck=
"-3184428132143472969"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"7619738475395271108"
xil_pn:start_ts=
"1366620454"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_ngo"
/>
<outfile
xil_pn:name=
"_xmsgs/ngdbuild.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bld"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ngd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_ngdbuild.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620500"
xil_pn:in_ck=
"-3184428132143472968"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1366620465"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.pcf"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_map.map"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_map.mrp"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_map.ncd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_map.ngm"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_map.xrpt"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_summary.xml"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_usage.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620536"
xil_pn:in_ck=
"-7407895592276768303"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1366620500"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ncd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.pad"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.par"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ptwx"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.unroutes"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.xpi"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_pad.csv"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_pad.txt"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_par.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620557"
xil_pn:in_ck=
"-7071212854459536945"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1366620536"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/bitgen.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bgn"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bit"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.drc"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ut"
/>
<outfile
xil_pn:name=
"webtalk.log"
/>
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"1366620536"
xil_pn:in_ck=
"-3184428132143473100"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1366620525"
>
<status
xil_pn:value=
"FailedRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/trce.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.twr"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.twx"
/>
</transform>
</transforms>
</generated_project>
hdl/release/syn/run.tcl
deleted
100644 → 0
View file @
706c104c
project open conv_ttl_blo_v2.xise
process run
{
Generate Programming File
}
-force rerun_all
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment