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Started reimplementation of I2C bridge, i2c_slave unit works in simulation and synthesizes.

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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{appendix}
\usepackage{tabularx}
%%\usepackage{draftwatermark}
%%\SetWatermarkLightness{0.9}
%%\SetWatermarkScale{5}
\begin{document}
\title{\textbf{{\LARGE I2C Slave to Wishbone Master module}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\hypersetup{
colorlinks = true,
urlcolor = blue
pdftitle = {SPI master multifield HDL core},
pdfauthor = {Carlos Gil Soriano},
pdfsubject = {Reference guide for SPI master multifield HDL core},
pdfkeywords = {I2C, VHDL, core, register, mappingi, configurable length}
}
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.5,
keepaspectratio]{../../../doc/OHWR/Pictures/Figures/OHRlogo.png}
\includegraphics[scale=0.25,
keepaspectratio]{../../../doc/OHWR/Pictures/Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
An I2C Slave to Wishbone Master module is depicted in this document.
Architecture-independent core kindly written in VHDL.\\
The following subjects are addressed:
\begin{itemize}
\item Control registers of the module
\item Step-by-step instructions for proper setup and use.
\end{itemize}
\end{abstract}
\vspace{2cm}
\begin{center}
\begin{tabular}{|p{2.5cm}|p{3.5cm}|p{3.5cm}|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
\hline
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & I2C slave & February 23, 2012\\
\hline
0.9 & I2C slave & \today\\
\hline
\end{tabular}
\end{center}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
Copyright CERN 2012.\\
This documentation describes Open Hardware and is licensed under the
CERN OHL v.1.1.\\
You may redistribute and modify this documentation under the terms of the CERN
OHL v.1.1. (\url{http://ohwr.org/cernohl}). This documentation is distributed
WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY,
SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.\\
Please see the CERN OHL variable.1.1 for applicable conditions.\\
\pagebreak
\setcounter{tocdepth}{3}
\tableofcontents
\pagebreak
\listoftables
\listoffigures
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\pagebreak
\section{Structure}
The i2c module contains several blocks related the following way:\\
-- i2c\_slave\_top.vhd
----- i2c\_regs.vhd
----- i2c\_slave\_core.vhd
--------- gc\_counter.vhd
--------- gc\_ff.vhd
--------- i2c\_bit.vhd
------------- i2c\_debouncer.vhd
The I2C slave functionalities are:
\begin{itemize}
\item Addresseable at both general or individual address.
\item Three independent fields (indirect wishbone address, write bytes into i2c
slave and read bytes from slave) can be configured to help integration.
\item A watchdog timer can be enable to increase reliability.
\end{itemize}
\begin{center}
\begin{tabularx}{\textwidth}{|X|}
\hline
It is recommended to take a look to the I2C standard before continue reading.\\
\hline
\end{tabularx}
\end{center}
\pagebreak
\subsection{Intended use}
\textit{I2C Slave to Wishbone Master module} is intended to be used in both
\href{http://www.ohwr.org/projects/conv-ttl-blo/wiki}{CONV-TTL-BLO}
\footnote{\href{https://edms.cern.ch/nav/P:EDA-02446:V0/P:EDA-02446:V0/TAB3}{EDA-02446}} and \href{http://www.ohwr.org/projects/conv-ttl-rs485/wiki}{CONV-TTL-RS485}
\footnote{\href{https://edms.cern.ch/nav/P:EDA-02541:V0/P:EDA-02541:V0/TAB3}{EDA-02541}} projects to allow FPGA be remotely reprogrammed. Read and write operations have been specified as follows:
\subsubsection{I2C Master write into slave}
\begin{description}
\item[Start] The master will issue a start condition.
\item[Byte 1] The master will issue a write operation to a given I2C slave
address. Less significant bit is driven first into SDA line.
\item[Ack 1] An ack is expected from slave.
\item[Byte 2] The master will drive the SDA line with the upper-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 2] An ack is expected from slave.
\item[Byte 3] The master will drive the SDA line with the lower-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 3] An ack is expected from slave.
\item[Byte 4] The master will drive the SDA line with the highest byte to
be written at the given wishbone address. Most significant bit is driven
first into the SDA line.
\item[Ack 4] An ack is expected from slave.
\item[Byte 5] The master will drive the SDA line with the second highest
byte to be written at the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 5] An ack is expected from slave.
\item[Byte 6] The master will drive the SDA line with the second lowest
byte to be written at the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 6] An ack is expected from slave.
\item[Byte 7] The master will drive the SDA line with the second lowest
byte to be written at the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 7] An ack is expected from slave.
\end{description}
Refer to \hyperref[sec:appendixA]{appendix ~\ref{sec:appendixA}} for a
detailed waveform diagram.
\subsubsection{I2C Master read from slave}
\begin{description}
\item[Start] The master will issue a start condition.
\item[Byte 1] The master will issue a write operation to a given I2C slave
address. Less significant bit is driven first into SDA line.
\item[Ack 1] An ack is expected from slave.
\item[Byte 2] The master will drive the SDA line with the upper-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 2] An ack is expected from slave.
\item[Byte 3] The master will drive the SDA line with the lower-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 3] An ack is expected from slave.
\item[Restart] The master will issue a (re)start condition.
\item[Byte 4] The master will issue a read operation to a given I2C slave
address. Less significant bit is driven first into SDA line.
\item[Byte 5] The slave will drive the SDA line with the highest byte to
be read from the given wishbone address. Most significant bit is driven
first into the SDA line.
\item[Ack 5] An nack is expected from master.
\item[Byte 6] The slave will drive the SDA line with the second highest
byte to be read from the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 6] An nack is expected from master.
\item[Byte 7] The slave will drive the SDA line with the second lowest
byte to be read from the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 7] An nack is expected from master.
\item[Byte 8] The slave will drive the SDA line with the lowest byte to
be read from the given wishbone address. Most significant bit is driven
first into the SDA line.
\item[Ack 8] An nack is expected from master.
\item[Pause] The master will issue a pause condition.
\end{description}
Refer to \hyperref[sec:appendixB]{appendix ~\ref{sec:appendixB}} for a
detailed waveform diagram.
\subsection{Interrupting lines offered from top or core modules}
To increase functionality of the core, some interrupt lines are offered so the
IP core can be used together with a soft-core.
\subsubsection{pf\_wb\_addr\_o}
One-clock signal to request prefetch of the data specified by upon the
reception of the wishbone address in the i2c.
\subsubsection{rd\_done\_o}
The slave has finished to read the SDA line. Hence, this signal informs that a
\textbf{i2c master write operation into the slave} has completed.
\subsubsection{wr\_done\_o}
The slave has finished to write into the SDA line. Hence, this signal informs that a
\textbf{i2c master read operation from slave} has completed.
\pagebreak
\section{Registers}
\subsection{CTR0}
\textit{CTR0} register is a \textbf{write-read} register.\\
It controls the indirect addres and holds the I2C address (which in
the case of \textit{CONV-TTL-BLO} will be
connected to VME64x geographical address pins).\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
0 & I2C\_OP & I2C OPeration & \textbf{'0'}\\
\hline
7-1 & I2C\_ADDR & I2C address & \textbf{See below}\\
\hline
11-8 & BIA & Bytes of Indirect Addressing & \textbf{X"2"}\\
\hline
19-12 & BRD & Bytes to be ReaD from FPGA & \textbf{X"4"}\\
\hline
27-20 & BWR & Bytes to be WRitten to FPGA & \textbf{X"4"}\\
\hline
31-28 & x & Reserved & \textbf{X"0"}\\
\hline
\end{tabular}
\caption{\textit{CTR0} register}
\end{center}
\end{table}
The default value of I2C\_ADDR is \textbf{c\_I2C\_GENERAL\_ADDR}. It can be
found in \textit{i2c\_slave\_pkg.vhd}.
\subsection{LT}
\textit{LT} stands for Line Timing register. It is a \textbf{read-only} register.\\
By accessing to this register, the speed of the line can be inferred. The value
of \textit{WBCP} is fixed prior synthesis, whereas \textit{SCLP} it is updated
on every transaction carried out in the I2C bus. SCLP returns the number of
wishbone cycles within an I2C clock period:
\begin{equation}
I2C_{speed} = \frac{SCLP}{WBCP}
\end{equation}
It should be noted that SCLP is an averaged value of the wishbone counter
among the first eight bits received (the ones that correspond to I2C address
plus write/read bit).\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
7-0 & WBCP & WishBone Clock Period & \textbf{User dependant}\\
\hline
31-8 & SCLP & SCL Period & \textbf{X"000000"}\\
\hline
\end{tabular}
\caption{\textit{LT} register}
\end{center}
\end{table}
\pagebreak
\subsection{DTX}
The \textit{DTX} register is a \textbf{write-read} register.\\
It holds the data to be sent when a read request from the master is issued.
\footnote{Contents are left uninitialized to reduce IP size.}\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
31-0 & data & data to send & \textbf{Not valid}\\
\hline
\end{tabular}
\caption{\textit{DTX} register }
\end{center}
\end{table}
\subsection{DRXA}
The \textit{DRXA} register is a \textbf{read-only} register.\\
It holds the last four received bytes through the I2C. LSB ordered.\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
31-0 & data & Data RX register & \textbf{Not valid}\\
\hline
\end{tabular}
\caption{\textit{DRXA} register}
\end{center}
\end{table}
\subsection{DRXB}
The\textit{DRXB} register is a \textbf{read-only} register.\\
It holds the second group of last four received bytes through I2C. LSB ordered.\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
31-0 & data & Data RX register & \textbf{Not valid}\\
\hline
\end{tabular}
\caption{\textit{DRXB} register}
\end{center}
\end{table}
\pagebreak
\section{Internal Memory Mapping}
The wishbone interface is addressed with 4-bit depth. Memory maps into:\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{CTR0} & Write-read\\
\hline
\textbf{0x1} & \textit{LT} & Read-only\\
\hline
\textbf{0x2} & \textit{DTX} & Write-read\\
\hline
\textbf{0x3} & \textit{DRXA} & Read-only\\
\hline
\textbf{0x4} & \textit{DRXB} & Read-only\\
\hline
\end{tabular}
\caption{I2C internal memory map}
\end{center}
\end{table}
\pagebreak
\section{(Re)Initilization}
It takes place when:
\begin{itemize}
\item An external reset is issued.
\item The watchdog timer runs out.
\item An I2C transaction is finished.
\end{itemize}
Subsequently, \textit{CTR0}, which controls the behaviour of the IP core, (re)initializes to:
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Default}\\
\hline
\hline
0 & I2C\_OP & \textbf{'0'}\\
\hline
7-1 & I2C\_ADDR & \textbf{See below}\\
\hline
11-8 & BIA & \textbf{X"2"}\\
\hline
19-12 & BRD & \textbf{X"4"}\\
\hline
27-20 & BWR & \textbf{X"4"}\\
\hline
31-28 & x & \textbf{X"0"}\\
\hline
\end{tabular}
\caption{\textit{CTR0} register}
\end{center}
\end{table}
\textbf{I2C\_ADDR} is initialized to the value of the \textbf{i2c\_addr\_i} port in
\textit{i2c\_slave\_top}.\\
For a better understanding of the i2c finite state machine, please take a look to
the appendix.
\subsection{Watchdog timer}
A fixed-length watchdog timer has been included in the module.\\
The watchdog timer is able to reinitialize the module whenever a fixed deadline
is met. The value of this fixed deadline can be controlled \textit{before
synthesis} in i2c\_slave\_pkg.vhd.
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | l |}
\hline
\textbf{Constant} & \textbf{Meaning}\\
\hline
\hline
c\_WB\_CLK\_PERIOD & Wishbone clock period (ns)\\
\hline
c\_WATCHDOG\_DEADLINE & Deadline period (ns)\\
\hline
c\_WATCHDOG\_ENABLE & Watchdog enable\\
\hline
c\_WATCHDOG\_WIDTH & Bit length of watchdog counter\\
\hline
\end{tabular}
\caption{Watchdog constants}
\end{center}
\end{table}
\section{Modifiying length of the I2C fields}
This module was conceived to let the user easily modify the length of three
main fields.\\
Due to the integration into the project it was requiered for, the
selectable-length fields are:\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| c | c |}
\hline
\textbf{I2C field} & \textbf{Select length}\\
\hline
\hline
Wishbone address & \textit{CTR0.\textbf{BIA}}\\
\hline
Data to read from slave & \textit{CTR0.\textbf{BRD}}\\
\hline
Data to write into slave & \textit{CTR0.\textbf{BWR}}\\
\hline
\end{tabular}
\caption{I2C multifield capability}
\end{center}
\end{table}
\pagebreak
\appendix
\section{I2C master write into slave} \label{sec:appendixA}
A I2C master write into a slave is shown. \textit{CTR0} is configured as:
\begin{itemize}
\item \textbf{CTR0.I2C\_ADDR}: X"3"
\item \textbf{CTR0.BIA}: X"2"
\item \textbf{CTR0.BWR}: X"4"
\end{itemize}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=1.1,
keepaspectratio]{./Figures/i2c_write.png}
\caption{I2C master write into slave}
\end{center}
\end{figure}
\pagebreak
\section{I2C master read from slave} \label{sec:appendixB}
A I2C master write into a slave is shown. \textit{CTR0} is configured as:
\begin{itemize}
\item \textbf{CTR0.I2C\_ADDR}: X"3"
\item \textbf{CTR0.BIA}: X"2"
\item \textbf{CTR0.BRD}: X"4"
\end{itemize}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=1.1,
keepaspectratio]{./Figures/i2c_read_slave.png}
\caption{I2C master read from slave}
\end{center}
\end{figure}
\section{i2c\_slave\_core Finite State Machine}
The finite state machine found in \textit{i2c\_slave\_core} is shown below.
Please note consistency with the colour schema in previous appendixes.
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.8,
keepaspectratio]{./Figures/i2c_SLA_fsm.png}
\caption{\textit{i2c\_slave\_core} fsm}
\end{center}
\end{figure}
\end{document}
hdl/i2c_to_wb_bridge/rtl/Manifest.py deleted 100644 → 0
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files = [
"i2c_slave_pkg.vhd",
"i2c_debounce.vhd",
"i2c_bit.vhd",
"bridge_regs.vhd",
"bridge.vhd",
"i2c_to_wb_bridge.vhd"
]
hdl/i2c_to_wb_bridge/rtl/bridge.vhd deleted 100644 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineers: Carlos Gil Soriano
-- Theodor-Adrian Stana
--
-- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge
-- Module Name: bridge - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a bridge from I2C to Wishbone.
-- The module consist on the following interfaces:
-- - I2C interface
-- - Wishbone master
-- - Wishbone slave
-- - Interruption lines
-- Each time a valid instruction is set in the I2C interface, this
-- is reported either:
-- A.- Via Wishbone: acting the module as a Wishbone master.
-- B.- Interrupts: the module offers some interrupt pins that
-- allows an external processor interact with
-- the module via the Wishbone slave
-- interface.
-- The FSM of this I2C core is able to detect indirect I2C
-- addressing. Thus reads, writes and prefetching of data
-- through Wishbone master interface will be issued.
-- ~ SUBCOMPONENTS ~
-- This component evaluates the data at the byte level, upon
-- the previous analysis of the SCL and SDA pins at a bit level.
-- The bit level analysis is carried out in:
-- --> ./i2c_bit.vhd
-- Two internal FIFOs (one for RX and another TX) are combined
-- with this module to store the received and ready-to-be sent
-- frames. The files are:
-- --> ./FIFO_stack.vhd
-- --> ./FIFO_dispatcher.vhd
-- Both the Wishbone master and slave interface access control
-- and all configuration registers can be found in:
-- --> ./i2c_regs.vhd
--
-- Dependencies: i2c_bit.vhd, FIFO_stack.vhd, FIFO_dispatcher.vhd, gc_ff.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- 0.1 - Initial submission. I2C instructions for Read and Write work.
-- 1.0 - Code completely revamped. Code tested with a code coverage of
-- 81.5% with the testbench provided in:
-- ../test/i2c_slave_test_top_tb.vhd
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
entity bridge is
generic
(
g_WB_CLK_PERIOD : time := 50 ns
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
-- I2C pins
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- Registers
ctr0_i : in std_logic_vector(31 downto 0);
lt_o : out std_logic_vector(31 downto 0);
drxa_o : out std_logic_vector(31 downto 0);
drxb_o : out std_logic_vector(31 downto 0);
-- Alarms for controlling the i2c states
pf_wb_addr_o : out std_logic;
pf_wb_data_i : in std_logic_vector(31 downto 0);
rd_done_o : out std_logic;
wr_done_o : out std_logic
);
end entity bridge;
architecture behav of bridge is
type t_state is (
R0_RESET,
S0_IDLE,
S1_START_DETECT,
S2_I2C_ADDR,
S2A_I2C_ADDR_ACK,
S2NA_I2C_ADDR_NACK,
S3_WISHBONE_ADDR,
S3A_WISHBONE_ADDR_ACK,
S4_DETECT_OPERATION,
S5R_READ_SDA,
S5RA_READ_SDA_ACK,
S5W0_RESTART,
S5W1_I2C_ADDR,
S5W1A_I2C_ADDR_ACK,
S5W1NA_I2C_ADDR_NACK,
S5W2_WRITE_SDA,
S5W2A_WRITE_SDA_ACK,
S5W3_NACK,
S6_WAIT_START_PAUSE,
S7_PAUSE_DETECT
);
component i2c_bit is
port
(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC
);
end component i2c_bit;
component gc_counter is
generic
(
g_DATA_WIDTH: NATURAL
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
);
end component gc_counter;
-------------------------------------------------------------------------------
-- FSM signals for the I2C module
-------------------------------------------------------------------------------
-- Four signals are employed to govern the FSM behaviour and its outputs.
--
-- These signals are updated in done_comb_proc process, dependant of the done
-- signal coming from i2c_bit.vhd
-- Every time a deglitched falling edge of the SCL line is detected in the
-- aforementioned i2c_bit.vhd, the signals done, start_o, pause_o, rcved_o are
-- considered valid to be studied in bridge.vhd processes.
--
-------------------------------------------------------------------------------
constant c_WATCHDOG_END_VALUE : NATURAL := 10**9; -- 8sec reset period
signal state : t_state := R0_RESET;
signal state_d0 : t_state := R0_RESET;
signal s_DRXA_slv : std_logic_vector(31 downto 0) := (others => '0');
signal s_DRXB_slv : std_logic_vector(31 downto 0) := (others => '0');
signal s_DRX_slv : std_logic_vector(63 downto 0) := (others => '0');
signal s_DTX_slv : std_logic_vector(31 downto 0);
signal s_CTR0 : r_CTR0;
signal s_LT : r_LT := c_LT_default;
signal s_i2c_addr_ctr0 : std_logic_vector(7 downto 0);
signal s_i2c_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- i2c signals
-------------------------------------------------------------------------------
signal s_sda_o : std_logic;
signal s_sda_en_o : std_logic;
signal s_bit_done : std_logic;
-- Bit counter signals
signal s_bit_cnt_slv : std_logic_vector(c_COUNTER_WIDTH - 1 downto 0);
signal s_bit_cnt : unsigned(7 downto 0);
signal s_bit_cnt_rst : std_logic;
-- Byte counter signals
signal s_byte_cnt_slv : std_logic_vector(c_COUNTER_WIDTH - 1 downto 0);
signal s_byte_cnt : unsigned(7 downto 0);
signal s_byte_cnt_rst : std_logic;
signal s_byte_cnt_en : std_logic := '0';
-- Interrupting signals (i2c_bit.vhd)
signal s_start_o : std_logic;
signal s_pause_o : std_logic;
signal s_rcved_o : std_logic;
signal s_pf_wb_data : std_logic_vector(31 downto 0) := (others => '1');
signal s_pf_wb_data_arr : std_logic_vector(31 downto 0) := (others => '1');
signal s_watchdog_cnt_rst : std_logic;
signal s_watchdog_cnt_slv : std_logic_vector(c_WATCHDOG_WIDTH - 1 downto 0);
signal s_watchdog_cnt : NATURAL;
signal txsr : std_logic_vector(31 downto 0);
begin
s_CTR0 <= f_CTR0(ctr0_i);
lt_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i;
cmp_i2c_bit: i2c_bit
port map
(
rst_i => rst_i,
clk_i => clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => s_start_o,
pause_o => s_pause_o,
rcved_o => s_rcved_o,
done_o => s_bit_done
);
cmp_bit_counter: gc_counter
generic map
(
g_data_width => c_DATA_WIDTH
)
port map
(
clk_i => clk_i,
rst_i => s_bit_cnt_rst,
en_i => s_bit_done,
cnt_o => s_bit_cnt_slv
);
s_bit_cnt <= unsigned(s_bit_cnt_slv);
cmp_byte_counter: gc_counter
generic map
(
g_data_width => c_DATA_WIDTH
)
port map
(
clk_i => clk_i,
rst_i => s_byte_cnt_rst,
en_i => s_byte_cnt_en,
cnt_o => s_byte_cnt_slv
);
s_byte_cnt <= unsigned(s_byte_cnt_slv);
cmp_watchdog_counter: gc_counter
generic map
(
g_data_width => c_WATCHDOG_WIDTH
)
port map
(
clk_i => clk_i,
rst_i => s_watchdog_cnt_rst,
en_i => c_WATCHDOG_ENABLE,
cnt_o => s_watchdog_cnt_slv
);
s_watchdog_cnt <= to_integer(UNSIGNED(s_watchdog_cnt_slv));
scl_o <= '1';
scl_en_o <= '0';
sda_o <= s_sda_o;
p_sda_o: process(state, txsr)
begin
case state is
when S2A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S3A_WISHBONE_ADDR_ACK =>
s_sda_o <= '0';
when S5RA_READ_SDA_ACK =>
s_sda_o <= '0';
when S5W1A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S5W2_WRITE_SDA =>
s_sda_o <= txsr(31);
when others =>
s_sda_o <= '1';
end case;
end process;
sda_en_o <= s_sda_en_o;
p_sda_en_o: process(state)
begin
s_sda_en_o <= '0';
case state is
when S2A_I2C_ADDR_ACK =>
s_sda_en_o <= '1';
when S3A_WISHBONE_ADDR_ACK =>
s_sda_en_o <= '1';
when S5RA_READ_SDA_ACK =>
s_sda_en_o <= '1';
when S5W1A_I2C_ADDR_ACK =>
s_sda_en_o <= '1';
when S5W2_WRITE_SDA =>
s_sda_en_o <= '1';
when others =>
null;
end case;
end process;
s_DRXA_slv <= s_DRX_slv(r_DRX'a_length - 1 downto 0);
s_DRXB_slv <= s_DRX_slv(r_DRX'a_length*2 - 1 downto r_DRX'a_length);
--Process to store the incoming data
p_store_FIFO: process(clk_i)
procedure shift_DRX is
begin
for i in 1 to s_DRX_slv'length - 1 loop
s_DRX_slv(i) <= s_DRX_slv(i-1);
end loop;
s_DRX_slv(0) <= s_rcved_o;
end procedure;
begin
if rising_edge(clk_i) then
if s_bit_done = '1' then
case state is
when S2_I2C_ADDR =>
shift_DRX;
when S3_WISHBONE_ADDR =>
shift_DRX;
when S4_DETECT_OPERATION =>
if s_start_o = '0'
and s_pause_o = '0' then
shift_DRX;
end if;
when S5R_READ_SDA =>
shift_DRX;
when S5W1_I2C_ADDR =>
shift_DRX;
when others =>
null;
end case;
end if;
end if;
end process;
s_i2c_addr_ctr0(7 downto 1) <= std_logic_vector(s_CTR0.I2C_ADDR);
s_i2c_addr(0) <= '0';
gen_i2c: for i in 1 to 7 generate
s_i2c_addr(8-i) <= s_i2c_addr_ctr0(i);
end generate gen_i2c;
p_delays : process(clk_i)
begin
if rising_edge(clk_i) then
state_d0 <= state;
end if;
end process;
-- Process to generate the pf_wb_addr_o signal.
p_pf_wb_addr: process(clk_i)
begin
if rising_edge(clk_i) then
pf_wb_addr_o <= '0';
if state = S5W1A_I2C_ADDR_ACK
and state_d0 = S5W1_I2C_ADDR then
pf_wb_addr_o <= '1';
end if;
end if;
end process;
-- Process to generate the rd_done_o signal.
p_rd_done: process(clk_i)
begin
if rising_edge(clk_i) then
rd_done_o <= '0';
if state = S6_WAIT_START_PAUSE
and state_d0 = S5RA_READ_SDA_ACK then
rd_done_o <= '1';
end if;
end if;
end process;
-- Process to generate the wr_done_o signal.
p_wr_done: process(clk_i)
begin
if rising_edge(clk_i) then
wr_done_o <= '0';
if state = S6_WAIT_START_PAUSE
and state_d0 = S5W3_NACK then
wr_done_o <= '1';
end if;
end if;
end process;
drxa_o <= s_DRXA_slv;
drxb_o <= s_DRXB_slv;
-- Process to update the signals that drive bit_counter_8
p_bit_counter_comb : process(state, state_d0, s_byte_cnt)
begin
s_bit_cnt_rst <= '0';
s_byte_cnt_rst <= '0';
case state is
when R0_RESET =>
if state_d0 /= R0_RESET then
s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1';
end if;
when S0_IDLE =>
null;
when S1_START_DETECT =>
s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1';
when S2_I2C_ADDR =>
null;
when S2A_I2C_ADDR_ACK =>
if (state_d0 = S2_I2C_ADDR) then
s_byte_cnt_rst <= '1';
end if;
when S3_WISHBONE_ADDR =>
if (state_d0 = S2A_I2C_ADDR_ACK) or
(state_d0 = S3A_WISHBONE_ADDR_ACK) or
(state_d0 = S5W1A_I2C_ADDR_ACK) then
s_bit_cnt_rst <= '1';
end if;
if (s_byte_cnt = s_ctr0.bia) and (state_d0 = S2A_I2C_ADDR_ACK) then
s_byte_cnt_rst <= '1';
end if;
when S3A_WISHBONE_ADDR_ACK =>
if (state_d0 = S3_WISHBONE_ADDR) then
s_bit_cnt_rst <= '1';
end if;
when S4_DETECT_OPERATION =>
if (state_d0 = S3A_WISHBONE_ADDR_ACK) then
s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1';
end if;
when S5W1_I2C_ADDR =>
null;
when S5W1A_I2C_ADDR_ACK =>
if (state_d0 <= S5W1_I2C_ADDR) then
s_bit_cnt_rst <= '1';
end if;
when S5W2_WRITE_SDA =>
null;
when S5W2A_WRITE_SDA_ACK =>
if (state_d0 = S5W2_WRITE_SDA) then
s_bit_cnt_rst <= '1';
end if;
when S5W0_RESTART =>
if (state_d0 = S4_DETECT_OPERATION) then
s_bit_cnt_rst <= '1';
end if;
when S5R_READ_SDA =>
if (s_byte_cnt = s_ctr0.bia) and (state_d0 = S3A_WISHBONE_ADDR_ACK) then
s_byte_cnt_rst <= '1';
end if;
if (state_d0 = S5RA_READ_SDA_ACK) then
s_bit_cnt_rst <= '1';
end if;
when S5RA_READ_SDA_ACK =>
if (state_d0 = S5R_READ_SDA) then
s_bit_cnt_rst <= '1';
end if;
when S6_WAIT_START_PAUSE =>
if (state_d0 /= S6_WAIT_START_PAUSE) then
s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1';
end if;
when S7_PAUSE_DETECT =>
null;
when others =>
null;
end case;
end process;
p_byte_counter_en: process (state, state_d0)
begin
s_byte_cnt_en <= '0';
case state is
when R0_RESET =>
null;
-- if state_d0 /= R0_RESET then
-- end if;
when S3A_WISHBONE_ADDR_ACK =>
if (state_d0 = S3_WISHBONE_ADDR) then
s_byte_cnt_en <= '1';
end if;
when S5RA_READ_SDA_ACK =>
if (state_d0 = S5R_READ_SDA) then
s_byte_cnt_en <= '1';
end if;
when S5W2A_WRITE_SDA_ACK =>
if (state_d0 = S5W2_WRITE_SDA) then
s_byte_cnt_en <= '1';
end if;
when others =>
null;
end case;
end process p_byte_counter_en;
-- Watchdog reset process
p_watchdog_rst: process(clk_i)
begin
if rising_edge(clk_i) then
s_watchdog_cnt_rst <= '0';
if rst_i = '1' then
s_watchdog_cnt_rst <= '1';
end if;
if s_watchdog_cnt >= c_WATCHDOG_END_VALUE then
s_watchdog_cnt_rst <= '1';
end if;
if state /= state_d0 then
s_watchdog_cnt_rst <= '1';
end if;
end if;
end process;
-- Small process that records the length of a
-- bit over the I2C interface.
p_lt_sclp: process(clk_i)
variable v_count : std_logic_vector(23 downto 0);
begin
if rising_edge(clk_i) then
if state = R0_RESET then
s_LT.SCLP <= c_LT_default.SCLP;
else
if (state = S2A_I2C_ADDR_ACK) and (state_d0 = S2_I2C_ADDR) then
-- Here we do a division bit 8, because the watchdog timer counts for
-- 8 scl clocks
v_count := s_watchdog_cnt_slv(24 - 1 + 3 downto 3);
s_LT.SCLP <= UNSIGNED(v_count);
end if;
end if;
end if;
end process p_lt_sclp;
-- Process to set the next fsm
p_fsm: process(clk_i)
procedure check_start_stop is
begin
if (s_start_o = '1') then
state <= S1_START_DETECT;
elsif (s_pause_o = '1') then
state <= R0_RESET;
end if;
end procedure;
begin
if rising_edge(clk_i) then
if (rst_i = '1') or (s_watchdog_cnt >= c_WATCHDOG_END_VALUE) then
state <= R0_RESET;
txsr <= (others => '0');
else
case state is
when R0_RESET =>
state <= S0_IDLE;
when S0_IDLE =>
if (s_bit_done = '1') then
if (s_start_o = '1') then
state <= S1_START_DETECT;
else
state <= R0_RESET;
end if;
end if;
when S1_START_DETECT =>
state <= S2_I2C_ADDR;
when S2_I2C_ADDR =>
if (s_bit_done = '1') then
if (s_bit_cnt = 7) then
if (s_DRX_slv(6 downto 0) = "0000000") or
(s_DRX_slv(6 downto 0) = std_logic_vector(s_CTR0.I2C_ADDR)) then
state <= S2A_I2C_ADDR_ACK;
else
state <= S2NA_I2C_ADDR_NACK;
end if;
end if;
check_start_stop;
end if;
when S2A_I2C_ADDR_ACK =>
if (s_bit_done = '1') then
state <= S3_WISHBONE_ADDR;
end if;
when S2NA_I2C_ADDR_NACK =>
if (s_bit_done = '1') then
state <= S6_WAIT_START_PAUSE;
end if;
when S3_WISHBONE_ADDR =>
if (s_bit_done = '1') then
if (s_bit_cnt = 7) then
state <= S3A_WISHBONE_ADDR_ACK;
end if;
check_start_stop;
end if;
when S3A_WISHBONE_ADDR_ACK =>
if (s_bit_done = '1') then
if (s_byte_cnt = s_ctr0.bia) then
state <= S4_DETECT_OPERATION;
else
state <= S3_WISHBONE_ADDR;
end if;
end if;
when S4_DETECT_OPERATION =>
if (s_bit_done = '1') then
if (s_start_o = '1') then
state <= S5W0_RESTART;
elsif (s_pause_o = '1') then
state <= R0_RESET;
else
state <= S5R_READ_SDA;
check_start_stop;
end if;
end if;
when S5R_READ_SDA =>
if (s_bit_done = '1') then
if (s_bit_cnt = 7) then
state <= S5RA_READ_SDA_ACK;
end if;
check_start_stop;
end if;
when S5RA_READ_SDA_ACK =>
if (s_bit_done = '1') then
if (s_byte_cnt < s_ctr0.brd) then
state <= S5R_READ_SDA;
else
state <= S6_WAIT_START_PAUSE;
end if;
end if;
when S5W0_RESTART =>
state <= S5W1_I2C_ADDR;
when S5W1_I2C_ADDR =>
if (s_bit_done = '1') then
if (s_bit_cnt = 7) then
if (s_DRX_slv(6 downto 0) = "0000000") -- ????????????????
or (s_DRX_slv(6 downto 0) = std_logic_vector(s_CTR0.I2C_ADDR)) then
state <= S5W1A_I2C_ADDR_ACK;
else
state <= S5W1NA_I2C_ADDR_NACK;
end if;
end if;
check_start_stop;
end if;
when S5W1A_I2C_ADDR_ACK =>
txsr <= f_ch_endian(pf_wb_data_i);
if s_bit_done = '1' then
state <= S5W2_WRITE_SDA;
end if;
when S5W1NA_I2C_ADDR_NACK =>
if s_bit_done = '1' then
state <= S6_WAIT_START_PAUSE;
end if;
when S5W2_WRITE_SDA =>
if (s_bit_done = '1') then
txsr <= txsr(30 downto 0) & '0';
if (s_bit_cnt = 8) then
state <= S5W2A_WRITE_SDA_ACK;
end if;
--! It can be removed, never reached
check_start_stop;
end if;
when S5W2A_WRITE_SDA_ACK =>
if (s_bit_done = '1') then
if (s_rcved_o = '0') then
if (s_byte_cnt < s_ctr0.bwr) then
state <= S5W2_WRITE_SDA;
else
state <= R0_RESET;
end if;
else
state <= S5W3_NACK;
check_start_stop;
end if;
end if;
when S5W3_NACK =>
state <= S6_WAIT_START_PAUSE;
when S6_WAIT_START_PAUSE =>
if (s_bit_done = '1') then
if (s_pause_o = '1') then
state <= S7_PAUSE_DETECT;
elsif (s_start_o = '1') then
state <= S1_START_DETECT;
else
state <= R0_RESET;
check_start_stop;
end if;
end if;
when S7_PAUSE_DETECT =>
state <= R0_RESET;
check_start_stop;
when others =>
state <= R0_RESET;
end case;
end if;
end if;
end process p_fsm;
end behav;
hdl/i2c_to_wb_bridge/rtl/bridge_regs.vhd deleted 100644 → 0
View file @ 9a04b242
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:56:55 10/25/2011
-- Design Name: I2C slave register HDL
-- Module Name: bridge_regs - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the HDL that holds all the register of the I2C slave
-- core
--
-- The registers should be programmed in the following order:
-- 1.- CTR0 Sets up the control register: enable, start, i2c address
-- 2.- CTR1 Sets up the threshold for detection signals in RX and TX buffers
--
-- Revision:
-- Revision 0.01 - File Created
-- 1.0 - Stable version
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
entity bridge_regs is
port
(
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_master_we_o : out std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
-- These are the registers offers to others modules of the FPGA
wb_slave_we_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
-- These are the registers that are offered to the i2c slave core
ctr0_o : out std_logic_vector(31 downto 0);
lt_i : in std_logic_vector(31 downto 0);
drxa_i : in std_logic_vector(31 downto 0);
drxb_i : in std_logic_vector(31 downto 0);
pf_wb_addr_i : in std_logic;
pf_wb_data_o : out std_logic_vector(31 downto 0);
rd_done_i : in std_logic;
wr_done_i : in std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end entity bridge_regs;
architecture behav of bridge_regs is
type t_wb_state is (
R0_RESET,
S0_IDLE,
S1P_WB_RD_RQT, -- Prefetch
S1_WB_RD_RQT,
S1N_WB_NOOP,
S1_PF_WB_DATA_OUT,
S2P_WB_WR_RQT, -- Prefetch
S2_WB_WR_RQT,
S2N_WB_NOOP,
S3_WB_ACK
);
signal wb_state : t_wb_state := R0_RESET;
signal s_wb_slave_addr : unsigned(3 downto 0);
signal s_wb_slave_ack : std_logic := '0';
signal s_wb_slave_rty : std_logic := '0';
signal s_wb_slave_err : std_logic := '0';
signal s_CTR0_slv : std_logic_vector (r_CTR0'a_length - 1 downto 0);
signal s_CTR0 : r_CTR0 := c_CTR0_default;
signal s_LT : r_LT;
signal s_DTX : std_logic_vector (r_DTX'a_length - 1 downto 0);
signal mst_we : std_logic;
signal s_wb_master_ack_retries : std_logic_vector(c_RETRY_LENGTH - 1 downto 0) := (others => '0');
signal s_wb_addr_rd : std_logic_vector(15 downto 0) := (others => '0');
begin
wb_master_we_o <= mst_we;
s_wb_slave_addr <= UNSIGNED(wb_slave_adr_i);
s_CTR0_slv <= f_std_logic_vector(s_CTR0);
s_LT <= f_LT(lt_i);
wb_slave_ack_o <= s_wb_slave_ack;
wb_slave_rty_o <= s_wb_slave_rty;
wb_slave_err_o <= s_wb_slave_err;
ctr0_o <= s_CTR0_slv;
pf_wb_data_o <= s_DTX;
--! @brief Process that controls the retries of the wishbone interface
--! @param wb_clk_i Main clock
p_wb_master_retries: process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_state = S3_WB_ACK then
s_wb_master_ack_retries(0) <= '1';
for i in 1 to c_RETRY_LENGTH - 1 loop
s_wb_master_ack_retries(i) <= s_wb_master_ack_retries(i-1);
end loop;
else
s_wb_master_ack_retries <= (others => '0');
end if;
end if;
end process;
-- Process to rule slave wishbone outputs
p_wb_slave: process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_state = R0_RESET then
s_CTR0 <= c_CTR0_default;
s_CTR0.I2C_ADDR <= UNSIGNED(i2c_addr_i);
s_wb_slave_ack <= '0';
s_wb_slave_rty <= '0';
s_wb_slave_err <= '0';
else
s_wb_slave_ack <= '0';
s_wb_slave_rty <= '0';
s_wb_slave_err <= '0';
if (wb_slave_stb_i = '1') and (wb_slave_cyc_i = '1') and
(s_wb_slave_ack = '0') and (s_wb_slave_rty = '0') and
(s_wb_slave_err = '0') then
case wb_slave_we_i is
when '1' =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
-- when c_CTR0_addr =>
-- s_CTR0 <= f_CTR0(wb_slave_dat_i);
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
when others =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
wb_slave_dat_o <= f_std_logic_vector(s_CTR0);
when c_LT_addr =>
wb_slave_dat_o <= f_std_logic_vector(s_LT);
when c_DTX_addr =>
wb_slave_dat_o <= s_DTX;
when c_DRXA_addr =>
wb_slave_dat_o <= drxa_i;
when c_DRXB_addr =>
wb_slave_dat_o <= drxb_i;
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
end case;
end if;
end if;
end if;
end process;
-- Process that outputs the wishbone
-- master interface. It should be noted
-- that we double-buffer the received data
-- to assure consistency of the data to be
-- read/written when repetitions of the
-- wishbone master interface happen.
p_wb_master: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
mst_we <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_dat_o <= (others => '0');
wb_master_adr_o <= (others => '0');
s_dtx <= (others => '0');
else
case wb_state is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1P_WB_RD_RQT =>
s_wb_addr_rd <= drxa_i(23 downto 8);
when S1_WB_RD_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_adr_o <= s_wb_addr_rd;
when S1N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_adr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT =>
s_DTX <= wb_master_dat_i;
when S2P_WB_WR_RQT =>
null;
when S2_WB_WR_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
mst_we <= '1';
wb_master_sel_o <= X"F";
wb_master_dat_o <= f_ch_endian(drxa_i);
wb_master_adr_o <= drxb_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
mst_we <= '1';
wb_master_sel_o <= X"F";
wb_master_dat_o <= f_ch_endian(drxa_i);
wb_master_adr_o <= drxb_i(15 downto 0);
when S3_WB_ACK =>
-- null;
wb_master_cyc_o <= '0';
wb_master_stb_o <= '0';
mst_we <= '0';
when others =>
null;
end case;
end if;
end if;
end process p_wb_master;
-- This is the process that controls the wishbone master interface
-- which bridges the i2c interface with the wishbone interface.
p_master_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
wb_state <= R0_RESET;
else
case wb_state is
when R0_RESET =>
wb_state <= S0_IDLE;
when S0_IDLE =>
if pf_wb_addr_i = '1' then
wb_state <= S1P_WB_RD_RQT;
elsif rd_done_i = '1' then
wb_state <= S2P_WB_WR_RQT;
end if;
when S1P_WB_RD_RQT =>
wb_state <= S1_WB_RD_RQT;
when S1_WB_RD_RQT =>
wb_state <= S1N_WB_NOOP;
when S1N_WB_NOOP =>
wb_state <= S1_PF_WB_DATA_OUT;
when S1_PF_WB_DATA_OUT =>
wb_state <= S3_WB_ACK;
when S2P_WB_WR_RQT =>
wb_state <= S2_WB_WR_RQT;
when S2_WB_WR_RQT =>
wb_state <= S2N_WB_NOOP;
when S2N_WB_NOOP =>
wb_state <= S3_WB_ACK;
when S3_WB_ACK =>
wb_state <= R0_RESET;
if wb_master_ack_i = '1' then
wb_state <= R0_RESET;
else
if wb_master_rty_i = '1' then
if s_wb_master_ack_retries(c_RETRY_LENGTH - 1) = '1' then
-- We stop retrying to not block the core
wb_state <= R0_RESET;
else
if mst_we = '1' then
wb_state <= S1_WB_RD_RQT;
else
wb_state <= S2_WB_WR_RQT;
end if;
end if;
end if;
end if;
when others =>
wb_state <= R0_RESET;
end case;
end if;
else
end if;
end process p_master_fsm;
end behav;
hdl/i2c_to_wb_bridge/rtl/i2c_bit.vhd deleted 100644 → 0
View file @ 9a04b242
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the fsm for the recognition of a bit. It offers some
-- interrupting lines to the upper level (i2c_slave_core.vhd)
-- which is responsible for managing byte level transactions
--
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- 0.1 - Module works with no reported issues.
-- 1.0 - Code revamped. Now is clearer and easier to read.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_bit is
port
(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC
);
end i2c_bit;
architecture behav of i2c_bit is
component i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end component i2c_debouncer;
type t_state is (
R0_RESET,
S0_IDLE,
S1A_HIGH_TMP,
S1A_HIGH,
S1B_LOW_TMP,
S1B_LOW,
S2A_START_TMP,
S2A_START,
S2B_STOP_DETECT,
Q1_ERROR
);
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
-- Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
signal sda_deglitched : STD_LOGIC;
signal sda_deglitched_d1 : STD_LOGIC;
signal scl_deglitched : STD_LOGIC;
signal scl_deglitched_d1 : STD_LOGIC;
signal state : t_state;
signal scl_rising : STD_LOGIC;
signal scl_falling : STD_LOGIC;
begin
cmp_scl_debouncer: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => scl_i,
output => scl_deglitched,
glitch_mask => c_GLITCH_MASK
);
cmp_sda_debounce: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => sda_i,
output => sda_deglitched,
glitch_mask => c_GLITCH_MASK
);
process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
sda_deglitched_d1 <= '0';
scl_deglitched_d1 <= '0';
else
sda_deglitched_d1 <= sda_deglitched;
scl_deglitched_d1 <= scl_deglitched;
end if;
end if;
end process;
-- This is the process that samples the scl for detecting
-- rise and falling edges
reg_proc: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
scl_falling <= '0';
scl_rising <= '0';
elsif (scl_deglitched = '0') and (scl_deglitched_d1 = '1') then
scl_falling <= '1';
elsif (scl_deglitched = '1') and (scl_deglitched_d1 = '0') then
scl_rising <= '1';
else
scl_falling <= '0';
scl_rising <= '0';
end if;
end if;
end process;
-- Combinatorial process to update the outputs.
p_comb_output: process(state)
begin
start_o <= '0';
pause_o <= '0';
rcved_o <= '0';
done_o <= '0';
case state is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1A_HIGH =>
rcved_o <= '1';
done_o <= '1';
when S1B_LOW =>
rcved_o <= '0';
done_o <= '1';
when S2A_START =>
start_o <= '1';
done_o <= '1';
when S2B_STOP_DETECT =>
pause_o <= '1';
done_o <= '1';
when Q1_ERROR =>
null;
when others =>
null;
end case;
end process p_comb_output;
-- The fsm of this module, later on the sda sampled line is
-- validated in the falling edge of scl.
p_fsm: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
state <= R0_RESET;
elsif scl_falling = '1' then
-- After a detection of a falling edge we update the
-- detection of a '0', a '1' and a start condition.
case state is
when S1A_HIGH_TMP =>
state <= S1A_HIGH;
when S1B_LOW_TMP =>
state <= S1B_LOW;
when S2A_START_TMP =>
state <= S2A_START;
when others =>
state <= S0_IDLE;
end case;
elsif (scl_rising = '1') then
-- When a rising edge is detected we annotate the first value
-- in SDA: either a temporary '0' or '1'
if (sda_deglitched_d1 = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
end if;
else
-- When we are in high level of a scl cycle, we keep on updating
-- the FSM
if (scl_deglitched = '1') then
case state is
-- Just for random bit swapped coverage.
when S0_IDLE =>
if (sda_deglitched = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
end if;
when S1A_HIGH_TMP =>
if sda_deglitched = '0' then
-- The detection of the start condition will be reported
-- in the next SCL rising edge.
state <= S2A_START_TMP;
end if;
when S1B_LOW_TMP =>
if sda_deglitched = '1' then
-- The detection of the pause condition MUST be
-- reported immediately.
state <= S2B_STOP_DETECT;
end if;
when S2A_START_TMP =>
if (sda_deglitched = '1') then
--! This happens if the deglitching is not enough
state <= Q1_ERROR;
end if;
when others =>
state <= S0_IDLE;
end case;
else
if (scl_deglitched_d1 = '0') then
state <= S0_IDLE;
end if;
end if;
end if;
end if;
end process p_fsm;
end behav;
hdl/i2c_to_wb_bridge/rtl/i2c_debounce.vhd deleted 100644 → 0
View file @ 9a04b242
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:11:43 10/25/2011
-- Design Name:
-- Module Name: i2c_debounce - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a I2C debouncer. The main difference is that it is
-- intended to filter out low glitches. That means the oppositive
-- from the previous version --debouncer.vhd.
-- This behaviour makes more sense compared on how I2C definition
-- resolves arbitration --conceptually the same as this module.
--
-- A '1' in the glitch_mask means that the bit should be studied.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal input_d0 : STD_LOGIC;
-- The first of this signal is already stable (ff'ed two times at [0])
signal delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
input_d0 <= '0';
delay <= (others => '0');
else
input_d0 <= input;
delay(0) <= input_d0;
delay(g_length-1 downto 1) <= delay(g_length-2 downto 0);
end if;
end if;
end process;
p_output: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
output <= '1';
else
-- We can deglitch either zeros or ones
if ( (delay and glitch_mask) = glitch_mask
or (not(delay) and glitch_mask) = glitch_mask) then
output <= delay(0);
else
-- Internall pull-up of the pin
output <= '1';
end if;
end if;
end if;
end process p_output;
end Behavioral;
hdl/i2c_to_wb_bridge/rtl/i2c_slave_pkg.vhd deleted 100644 → 0
View file @ 9a04b242
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
-- Theodor-Adrian Stana
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
-- Module Name: i2c_slave_pkg - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Package for the i2c_slave
--
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package i2c_slave_pkg is
--! Default clock divider
constant c_RST_EXTENSOR : NATURAL := 4;
constant c_DEBOUNCE_LENGTH : NATURAL := 6;
--! Broadcast address as specified in I2C standard
constant c_I2C_GENERAL_ADDR : UNSIGNED(6 downto 0) := to_unsigned(0,7);
constant c_RETRY_LENGTH : NATURAL := 10; --! 10 clks max. retries
constant c_SDA_reverse_bytes : BOOLEAN := false;
constant c_SDA_MSb : BOOLEAN := false;
-------------------------------------------------------------------------------
-- This is the declaration area of the constants used in other components:
-- c_COUNTER_WIDTH bit length of the gc_counter
-- c_DATA_WIDTH width of the data to be stored in FIFO_stack
-- and FIFO_dispatchers.
-- c_RX_STACK_DEPTH depth of FIFO_stack
-- c_TX_STACK_DEPTH depth of FIFO_dispatch
-------------------------------------------------------------------------------
constant c_COUNTER_WIDTH : NATURAL := 8;
constant c_DATA_WIDTH : NATURAL := 8;
constant c_RX_STACK_DEPTH : NATURAL := 6;
constant c_TX_STACK_DEPTH : NATURAL := 4;
constant c_WB_CLK_PERIOD : TIME := 50 ns;
constant c_WATCHDOG_WIDTH : NATURAL := 32;
constant c_WATCHDOG_DEADLINE : TIME := 10**9*60 ns;
constant c_WATCHDOG_ENABLE : STD_LOGIC := '1';
attribute a_length : NATURAL;
-------------------------------------
-- CTR0 register
-------------------------------------
-- 32 bits
-- Wishbone access: Write-read
------------------------------------
-- BIT NAME Description
-- 0 I2C_OP I2C OPeration
-- 7-1 I2C_ADDR I2C address
-- 11-8 BIA Bytes of Indirect Addressing
-- 19-12 BRD Bytes to be ReaD from FPGA
-- 27-20 BWR Bytes to be WRitten to FPGA
-- 31-28 x Reserved
-------------------------------------
-- I2C_OP Operations
-- 0 Read from I2C
-- 1 Write into I2C
-------------------------------------
type r_CTR0 is
record
I2C_OP : STD_LOGIC;
I2C_ADDR : UNSIGNED( 7 downto 1);
BIA : UNSIGNED(11 downto 8);
BRD : UNSIGNED(19 downto 12);
BWR : UNSIGNED(27 downto 20);
x : STD_LOGIC_VECTOR(31 downto 28);
end record;
attribute a_length of r_CTR0 : type is 32;
-------------------------------------
-- LT register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 7-0 WBCP WishBone Clock Period
-- 31-8 SCLP SCL Period
-------------------------------------
-- Both period are given with nanosecond
-- precision.
-------------------------------------
type r_LT is
record
WBCP : UNSIGNED(7 downto 0);
SCLP : UNSIGNED(31 downto 8);
end record;
attribute a_length of r_LT : type is 32;
-------------------------------------
-- DRX register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 31-0 DRX Data RX register
-------------------------------------
type r_DRX is
record
data : STD_LOGIC_VECTOR(31 downto 0);
end record;
attribute a_length of r_DRX : type is 32;
-------------------------------------
-- DTX register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 31-0 DTX Data TX register
-------------------------------------
type r_DTX is
record
data : STD_LOGIC_VECTOR(31 downto 0);
end record;
attribute a_length of r_DTX : type is 32;
constant c_CTR0_addr : UNSIGNED(3 downto 0) := X"0";
constant c_LT_addr : UNSIGNED(3 downto 0) := X"1";
constant c_DTX_addr : UNSIGNED(3 downto 0) := X"2";
constant c_DRXA_addr : UNSIGNED(3 downto 0) := X"3";
constant c_DRXB_addr : UNSIGNED(3 downto 0) := X"4";
constant c_CTR0_default : r_CTR0 := (I2C_OP => '0',
I2C_ADDR => c_I2C_GENERAL_ADDR,
BIA => to_unsigned(2, 4),
BRD => to_unsigned(4, 8),
BWR => to_unsigned(4, 8),
x => (others => '0'));
constant c_LT_default : r_LT := (WBCP =>
to_unsigned(c_WB_CLK_PERIOD/(1 ns), 8),
SCLP => to_unsigned(0, 24));
component i2c_slave_core
generic(g_WB_CLK_PERIOD : TIME := 50 ns);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
CTR0_i : in STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
LT_o : out STD_LOGIC_VECTOR (r_LT'a_length - 1 downto 0);
DRXA_o : out STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DRXB_o : out STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
pf_wb_addr_o : out STD_LOGIC;
pf_wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC);
end component;
component i2c_regs
port (wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_we_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
CTR0_o : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
LT_i : in STD_LOGIC_VECTOR (r_LT'a_length - 1 downto 0);
DRXA_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DRXB_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
rd_done_i : in STD_LOGIC;
wr_done_i : in STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0));
end component;
component i2c_debouncer is
generic (g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH);
port (rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0));
end component;
component i2c_bit
port (rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC);
end component;
function f_CTR0 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_CTR0;
function f_LT (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_LT;
function f_ch_endian(val : std_logic_vector) return std_logic_vector;
function f_STD_LOGIC_VECTOR(r_register : in r_CTR0) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : in r_LT) return STD_LOGIC_VECTOR;
end i2c_slave_pkg;
package body i2c_slave_pkg is
function f_CTR0 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_CTR0 is
variable v_return : r_CTR0;
begin
v_return.I2C_OP := r_register(0);
v_return.I2C_ADDR := UNSIGNED(r_register( 7 downto 1));
v_return.BIA := UNSIGNED(r_register(11 downto 8));
v_return.BRD := UNSIGNED(r_register(19 downto 12));
v_return.BWR := UNSIGNED(r_register(27 downto 20));
v_return.x := (others => '0');
return v_return;
end function;
function f_LT (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_LT is
variable v_return : r_LT;
begin
v_return.WBCP := UNSIGNED(r_register(7 downto 0));
v_return.SCLP := UNSIGNED(r_register(31 downto 8));
return v_return;
end function;
function f_STD_LOGIC_VECTOR(r_register : in r_LT)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(31 downto 0);
begin
v_return(7 downto 0) := STD_LOGIC_VECTOR(r_register.WBCP);
v_return(31 downto 8) := STD_LOGIC_VECTOR(r_register.SCLP);
return v_return;
end function;
function f_STD_LOGIC_VECTOR(r_register : in r_CTR0)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(31 downto 0);
begin
v_return(0) := r_register.I2C_OP;
v_return( 7 downto 1) := STD_LOGIC_VECTOR(r_register.I2C_ADDR);
v_return(11 downto 8) := STD_LOGIC_VECTOR(r_register.BIA);
v_return(19 downto 12) := STD_LOGIC_VECTOR(r_register.BRD);
v_return(27 downto 20) := STD_LOGIC_VECTOR(r_register.BWR);
v_return(31 downto 28) := (others => '0');
return v_return;
end function;
function f_ch_endian(val : std_logic_vector)
return std_logic_vector is
variable retval : std_logic_vector(31 downto 0);
begin
retval( 7 downto 0) := val(31 downto 24);
retval(15 downto 8) := val(23 downto 16);
retval(23 downto 16) := val(15 downto 8);
retval(31 downto 24) := val( 7 downto 0);
return retval;
end function;
end i2c_slave_pkg;
hdl/i2c_to_wb_bridge/rtl/i2c_to_wb_bridge.vhd deleted 100644 → 0
View file @ 9a04b242
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT CHANGED
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_to_wb_bridge - behav
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.all;
entity i2c_to_wb_bridge is
port
(
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
pf_wb_addr_o : out std_logic;
rd_done_o : out std_logic;
wr_done_o : out std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end i2c_to_wb_bridge;
architecture behav of i2c_to_wb_bridge is
component bridge is
generic
(
g_WB_CLK_PERIOD : time := 50 ns
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
-- I2C pins
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- Registers
CTR0_i : in std_logic_vector (r_CTR0'a_length - 1 downto 0);
LT_o : out std_logic_vector (r_LT'a_length - 1 downto 0);
DRXA_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
DRXB_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
-- Alarms for controlling the i2c states
pf_wb_addr_o : out std_logic;
pf_wb_data_i : in std_logic_vector(31 downto 0);
rd_done_o : out std_logic;
wr_done_o : out std_logic
);
end component bridge;
component bridge_regs is
port
(
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
-- These are the registers offers to others modules of the FPGA
wb_slave_we_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
-- These are the registers that are offered to the i2c slave core
ctr0_o : out STD_LOGIC_VECTOR (31 downto 0);
lt_i : in STD_LOGIC_VECTOR (31 downto 0);
drxa_i : in STD_LOGIC_VECTOR (31 downto 0);
drxb_i : in STD_LOGIC_VECTOR (31 downto 0);
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
rd_done_i : in STD_LOGIC;
wr_done_i : in STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component bridge_regs;
signal ctr0 : std_logic_vector(r_CTR0'a_length - 1 downto 0);
signal lt : std_logic_vector(r_LT'a_length - 1 downto 0);
signal drxa : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal drxb : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal pf_wb_addr : std_logic;
signal pf_wb_data : std_logic_vector(31 downto 0);
signal rd_done : std_logic;
signal wr_done : std_logic;
begin
pf_wb_addr_o <= pf_wb_addr;
rd_done_o <= rd_done;
wr_done_o <= wr_done;
cmp_bridge: bridge
generic map
(
g_wb_clk_period => 8 ns
)
port map
(
clk_i => clk_i,
rst_i => rst_i,
sda_en_o => sda_en_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_en_o,
scl_i => scl_i,
scl_o => scl_o,
CTR0_i => ctr0,
LT_o => lt,
DRXA_o => drxa,
DRXB_o => drxb,
pf_wb_addr_o => pf_wb_addr,
pf_wb_data_i => pf_wb_data,
rd_done_o => rd_done,
wr_done_o => wr_done
);
cmp_bridge_regs: bridge_regs
port map
(
pf_wb_addr_i => pf_wb_addr,
pf_wb_data_o => pf_wb_data,
rd_done_i => rd_done,
wr_done_i => wr_done,
wb_rst_i => rst_i,
wb_clk_i => clk_i,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_dat_i => wb_master_dat_i,
wb_master_dat_o => wb_master_dat_o,
wb_master_adr_o => wb_master_adr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
wb_slave_we_i => wb_slave_we_i,
wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_sel_i => wb_slave_sel_i,
wb_slave_dat_i => wb_slave_dat_i,
wb_slave_dat_o => wb_slave_dat_o,
wb_slave_adr_i => wb_slave_adr_i,
wb_slave_ack_o => wb_slave_ack_o,
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
ctr0_o => ctr0,
lt_i => lt,
drxa_i => drxa,
drxb_i => drxb,
i2c_addr_i => i2c_addr_i
);
end behav;
hdl/i2c_to_wb_bridge/syn/Makefile deleted 100644 → 0
View file @ 9a04b242
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo_v2.xise
ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo_v2
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../top/conv_ttl_blo_v2.ucf \
../top/conv_ttl_blo_v2.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../rtl/i2c_slave_pkg.vhd \
../rtl/i2c_debounce.vhd \
../rtl/i2c_bit.vhd \
../rtl/bridge_regs.vhd \
../rtl/bridge.vhd \
../rtl/i2c_to_wb_bridge.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd \
../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
conv_ttl_blo_v2.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/i2c_to_wb_bridge/syn/Manifest.py deleted 100644 → 0
View file @ 9a04b242
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../top"
]
}
hdl/i2c_to_wb_bridge/syn/conv_ttl_blo_v2.gise deleted 100644 → 0
View file @ 9a04b242
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo_v2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo_v2.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo_v2.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo_v2.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo_v2.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="conv_ttl_blo_v2.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="conv_ttl_blo_v2.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_v2.ncd" xil_pn:subbranch="Par"/>
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hdl/i2c_to_wb_bridge/syn/conv_ttl_blo_v2.xise deleted 100644 → 0
View file @ 9a04b242
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<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="impact.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_blo_v2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-11T14:36:38" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A9429981388E98626D5BFE9AED5E1A83" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<files>
<file xil_pn:name="../top/conv_ttl_blo_v2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../rtl/bridge_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../rtl/bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../rtl/i2c_to_wb_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
hdl/i2c_to_wb_bridge/syn/run.tcl deleted 100644 → 0
View file @ 9a04b242
project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/i2c_to_wb_bridge/test/i2c_bit_tb.vhd deleted 100644 → 0
View file @ 9a04b242
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:07:51 10/26/2011
-- Design Name: i2c slave to wb_master testbench
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
library work;
USE ieee.std_logic_1164.ALL;
USE work.i2c_slave_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component i2c_bit
port(
rst_i : IN std_logic;
wb_clk_i : IN std_logic;
sda_i : IN std_logic;
scl_i : IN std_logic;
done_o : OUT std_logic;
start_o : OUT std_logic;
pause_o : OUT std_logic;
rcved_o : OUT std_logic
);
end component;
--Inputs
signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0';
signal sda_i : std_logic := '0';
signal scl_i : std_logic := '0';
--Outputs
signal start_o : std_logic;
signal pause_o : std_logic;
signal rcved_o : std_logic;
signal done_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_bit
PORT MAP (rst_i => rst_i,
wb_clk_i => wb_clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => start_o,
pause_o => pause_o,
rcved_o => rcved_o,
done_o => done_o);
-- Clock process definitions
wb_clk_i_process :process
begin
wb_clk_i <= '1';
wait for wb_clk_i_period/2;
wb_clk_i <= '0';
wait for wb_clk_i_period/2;
end process;
scl_i_process :process
begin
scl_i <= '1';
wait for scl_i_period/2;
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
begin
sda_i <= '1';
scl_i <= 'Z';
end init_cond;
procedure rst is
begin
wait for wb_clk_i_period*2;
rst_i <= '1';
wait for wb_clk_i_period*2;
rst_i <= '0';
wait for wb_clk_i_period*2;
end rst;
procedure start is
begin
sda_i <= '1';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '0';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end start;
procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
begin
for i in 0 to 6 loop
sda_i <= addr(i);
wait for scl_i_period;
end loop;
end addr_send;
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '1';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end pause;
begin
init_cond;
rst;
start;
addr_send("0101100");
pause;
wait;
end process;
END;
hdl/i2c_to_wb_bridge/test/i2c_master_driver.vhd deleted 100644 → 0
View file @ 9a04b242
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use work.i2c_slave_pkg.ALL;
use work.i2c_tb_pkg.ALL;
use std.textio.ALL;
--! Code intended for simulation only.
entity i2c_master_driver is
generic(g_WR_DATA_LENGTH : NATURAL := 32;
g_RD_DATA_LENGTH : NATURAL := 32;
g_WB_ADDR_LENGTH : NATURAL := 16;
g_SCL_PERIOD : TIME := 250 us;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
scl_master_o : out STD_LOGIC;
i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0);
wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(g_RD_DATA_LENGTH - 1 downto 0);
start_i : in STD_LOGIC;
start_done_o : out STD_LOGIC;
pause_i : in STD_LOGIC;
pause_done_o : out STD_LOGIC;
write_i : in STD_LOGIC;
write_done_o : out STD_LOGIC;
read_i : in STD_LOGIC;
read_done_o : out STD_LOGIC);
end i2c_master_driver;
architecture Behavioral of i2c_master_driver is
type i2c_byte_field is (ADDRESS_0,
ADDRESS_1,
WISHBONE_HIGH,
WISHBONE_LOW,
DATA0,
DATA1,
DATA2,
DATA3);
file s_file_handler : TEXT;
--! constant c_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt";
constant sep : CHARACTER := ht;
signal s_scl_clk : STD_LOGIC := '1';
signal s_sda_master_o : STD_LOGIC := '1';
signal s_test_id : NATURAL := 0;
signal s_start_done : STD_LOGIC := '0';
signal s_pause_done : STD_LOGIC := '0';
signal s_write_done : STD_LOGIC := '0';
signal s_read_done : STD_LOGIC := '0';
signal s_active_link : STD_LOGIC := '0';
signal s_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0);
signal s_DTX : STD_LOGIC_VECTOR(0 to 31) := (others => '0');
begin
file_open(s_file_handler, g_LOG_PATH, WRITE_MODE);
sda_master_o <= s_sda_master_o;
scl_master_o <= s_scl_clk when s_active_link = '1'
else '1';
start_done_o <= s_start_done;
pause_done_o <= s_pause_done;
write_done_o <= s_write_done;
read_done_o <= s_read_done;
rd_data_o <= s_DTX;
scl_clk_process: process
begin
s_scl_clk <= not(s_scl_clk);
wait for g_SCL_PERIOD/2;
end process;
p_sda: process
variable v_bit_number : NATURAL := 0;
variable v_write_data : STD_LOGIC_VECTOR(g_RD_DATA_LENGTH - 1 downto 0);
variable v_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0);
--! @brief Function that returns strings for the acked field to be
--! logged.
--! @param byte_type i2c_byte_field type to be translated into a string
function get_field(byte_type : i2c_byte_field) return STRING is
variable v_return : STRING (16 downto 1) := (others => ' ');
begin
case byte_type is
when ADDRESS_0 =>
v_return := " [ADDRESS|0]";
when ADDRESS_1 =>
v_return := " [ADDRESS|1]";
when WISHBONE_HIGH =>
v_return := " WISHBONE HIGH";
when WISHBONE_LOW =>
v_return := " WISHBONE LOW";
when DATA0 =>
v_return := " READ DATA 0";
when DATA1 =>
v_return := " READ DATA 1";
when DATA2 =>
v_return := " READ DATA 2";
when DATA3 =>
v_return := " READ DATA 3";
when others =>
null;
end case;
return v_return;
end function;
function order_i2c_addr_op(
i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0))
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(7 downto 0);
begin
for i in 0 to 7 loop
v_return(7-i) := i2c_addr_op(i);
end loop;
return v_return;
end function;
--! @brief Function to reorder data before being sent by driver
--! through SDA
--! @param data Data to be reordered before being sent
function order_write_data(
data : STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0))
return STD_LOGIC_VECTOR is
variable v_ordered_tmp : STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
variable v_ordered : STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
begin
if c_SDA_reverse_bytes = true then
for i in 0 to g_RD_DATA_LENGTH/8 - 1 loop
for j in 0 to 7 loop
v_ordered_tmp(i*8+j) := data(((g_WR_DATA_LENGTH/8 - 1)-i)*8+j);
end loop;
end loop;
else
v_ordered := data;
end if;
if c_SDA_MSb = true then
for i in 0 to g_RD_DATA_LENGTH/8 - 1 loop
for j in 0 to 7 loop
v_ordered(i*8+j) := v_ordered_tmp(i*8+(8-j));
end loop;
end loop;
else
v_ordered := v_ordered_tmp;
end if;
return v_ordered;
end function;
--! @brief Procedure to send bytes through SDA
--! @param byte Byte to be sent
procedure send_byte(byte : STD_LOGIC_VECTOR(7 downto 0)) is
begin
--! This comes from a falling edge
for i in 7 downto 0 loop
wait for g_SCL_PERIOD/4;
s_sda_master_o <= byte(i);
wait until falling_edge(s_scl_clk);
end loop;
end procedure;
--! @brief Procedure to check acks
--! @param test_id Test ID
--! @param operation Operation to be performed, either READ or WRITE
procedure check_ack(test_id : NATURAL;
operation : STRING (5 downto 1);
byte_type : i2c_byte_field) is
variable v_line_buffer : LINE;
variable v_check : STRING ( 4 downto 1) := (others => ' ');
variable v_operation : STRING ( 5 downto 1) := (others => ' ');
variable v_ack : STRING (16 downto 1) := (others => ' ');
begin
wait until rising_edge(s_scl_clk);
v_operation := operation;
v_ack := get_field(byte_type);
if sda_master_i = '1' then
v_check (4 downto 1) := "Fail";
write(v_line_buffer,string'(integer'image(test_id)&sep& v_check&sep&v_operation&sep&v_ack));
else
v_check (2 downto 1) := "OK";
write(v_line_buffer,string'(integer'image(test_id)&sep
& v_check &sep
& v_operation &sep
& v_ack));
end if;
writeline(s_file_handler, v_line_buffer);
wait until falling_edge(s_scl_clk);
end procedure;
--! @brieg Procedure to start/restart I2C communication
procedure start_I2c is
begin
s_sda_master_o <= '1';
wait until rising_edge(s_scl_clk);
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
s_active_link <= '1';
wait until falling_edge(s_scl_clk);
wait until rising_edge(tb_clk);
s_start_done <= '1';
wait until rising_edge(tb_clk);
s_start_done <= '0';
end procedure;
--! @brief Procedure to pause I2c communication
procedure pause_I2C is
begin
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
wait until rising_edge(s_scl_clk);
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '1';
s_active_link <= '1';
--! We allow one clock to let i2c_slave_core.vhd to react
wait until rising_edge(tb_clk);
s_pause_done <= '1';
wait until rising_edge(tb_clk);
s_pause_done <= '0';
s_active_link <= '0';
end procedure;
procedure read_bit is
variable v_bit_rcv : STD_LOGIC;
begin
wait until rising_edge(s_scl_clk);
v_bit_rcv := sda_master_i;
for i in 0 to (g_SCL_PERIOD/2)/(1 ns) - 1 loop
if v_bit_rcv /= sda_master_i then
--! Here we report an error
end if;
wait for 1 ns;
end loop;
wait until falling_edge(s_scl_clk);
s_DTX(s_DTX'length - 1) <= v_bit_rcv;
end procedure;
procedure shift_bit is
begin
for i in 1 to s_DTX'length - 1 loop
s_DTX(i-1) <= s_DTX(i);
end loop;
end procedure;
procedure read_byte is
begin
for i in 0 to 7 loop
read_bit;
shift_bit;
end loop;
--! At the end we are just in the falling edge of scl
end procedure;
procedure place_ack is
begin
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
wait until falling_edge(s_scl_clk);
s_sda_master_o <= '1';
end procedure;
procedure place_nack is
begin
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '1';
wait until falling_edge(s_scl_clk);
s_sda_master_o <= '0';
end procedure;
variable first : boolean := true;
begin
if (first = true) then
wait until rst_n = '1';
first := false;
end if;
if start_i = '1' then
assert false report "mst start" severity note;
start_I2c;
elsif pause_i = '1' then
assert false report "mst pause" severity note;
pause_I2C;
elsif write_i = '1' then
assert false report "mst write" severity note;
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
v_i2c_addr_op := i2c_addr_op_i;
v_i2c_addr_op(0) := '0';
send_byte(v_i2c_addr_op);
check_ack(s_test_id, "WRITE", ADDRESS_0);
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, "WRITE", WISHBONE_HIGH);
--! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, "WRITE", WISHBONE_LOW);
--! 4.- Send DATA0
send_byte(wr_data_i(31 downto 24));
check_ack(s_test_id, "WRITE", DATA0);
--! 5.- Send DATA1
send_byte(wr_data_i(23 downto 16));
check_ack(s_test_id, "WRITE", DATA1);
--! 6.- Send DATA2
send_byte(wr_data_i(15 downto 8));
check_ack(s_test_id, "WRITE", DATA2);
--! 7.- Send DATA3
send_byte(wr_data_i(7 downto 0));
check_ack(s_test_id, "WRITE", DATA3);
pause_I2C;
s_write_done <= '1';
wait until rising_edge(tb_clk);
s_write_done <= '0';
elsif read_i = '1' then
assert false report "mst read" severity note;
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
v_i2c_addr_op := i2c_addr_op_i;
v_i2c_addr_op(0) := '0';
send_byte(v_i2c_addr_op);
check_ack(s_test_id, " READ", ADDRESS_0);
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, " READ", WISHBONE_HIGH);
--! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, " READ", WISHBONE_LOW);
--! 4.- We have to place a start condition
start_I2c;
--! 5.- Send [ADDRESS|1]
v_i2c_addr_op(7 downto 1) := i2c_addr_op_i(7 downto 1);
v_i2c_addr_op(0) := '1';
send_byte(v_i2c_addr_op);
check_ack(s_test_id, " READ", ADDRESS_0);
--! 6.- Read DATA0
read_byte;
place_ack;
--! 7.- Read DATA1
read_byte;
place_ack;
--! 8.- Read DATA2
read_byte;
place_ack;
--! 9.- Read DATA3
read_byte;
place_ack;
pause_I2C;
s_read_done <= '1';
wait until rising_edge(tb_clk);
s_read_done <= '0';
end if;
wait until rising_edge(tb_clk);
end process;
end;
hdl/i2c_to_wb_bridge/test/i2c_slave_top_tb.vhd deleted 100644 → 0
View file @ 9a04b242
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 10:59:15 10/31/2011
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
-- Project Name: i2c_slave_wb_master
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_slave_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.1 - File Modified. Now the sda_i line is more acurately accessed.
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALl;
use std.textio.ALL;
use work.i2c_tb_pkg.ALL;
use work.wishbone_driver_pkg.ALL;
entity i2c_slave_top_tb is
end i2c_slave_top_tb;
architecture behavior of i2c_slave_top_tb is
--! Connections for i2c_slave_top
signal sda_slave_oen : STD_LOGIC;
signal sda_slave_i : STD_LOGIC := '1';
signal sda_slave_o : STD_LOGIC;
signal scl_slave_oen : STD_LOGIC;
signal scl_slave_i : STD_LOGIC := '1';
signal scl_slave_clk : STD_LOGIC := '1';
signal scl_slave_o : STD_LOGIC;
signal wb_clk : STD_LOGIC := '0';
signal wb_rst_i : STD_LOGIC := '0';
signal wb_master_stb_o : STD_LOGIC;
signal wb_master_cyc_o : STD_LOGIC;
signal wb_master_sel_o : STD_LOGIC_VECTOR (3 downto 0);
signal wb_master_we_o : STD_LOGIC;
signal wb_master_data_i : STD_LOGIC_VECTOR (31 downto 0) := X"00000000";
signal wb_master_data_o : STD_LOGIC_VECTOR (31 downto 0);
signal wb_master_addr_o : STD_LOGIC_VECTOR (15 downto 0);
signal wb_master_ack_i : STD_LOGIC := '0';
signal wb_master_rty_i : STD_LOGIC := '0';
signal wb_master_err_i : STD_LOGIC := '0';
signal wb_slave_cyc_i : STD_LOGIC := '0';
signal wb_slave_stb_i : STD_LOGIC;
signal wb_slave_sel_i : STD_LOGIC_VECTOR (3 downto 0) := X"0";
signal wb_slave_we_i : STD_LOGIC := '0';
signal wb_slave_data_i : STD_LOGIC_VECTOR (31 downto 0) := X"00000000";
signal wb_slave_data_o : STD_LOGIC_VECTOR (31 downto 0);
signal wb_slave_addr_i : STD_LOGIC_VECTOR (3 downto 0) := X"0";
signal wb_slave_ack_o : STD_LOGIC;
signal wb_slave_rty_o : STD_LOGIC;
signal wb_slave_err_o : STD_LOGIC;
signal wb_driver_cyc_o : STD_LOGIC := '0';
signal wb_driver_stb_o : STD_LOGIC;
signal wb_driver_sel_o : STD_LOGIC_VECTOR (3 downto 0) := X"0";
signal wb_driver_we_o : STD_LOGIC := '0';
signal wb_driver_data_o : STD_LOGIC_VECTOR (31 downto 0) := X"00000000";
signal wb_driver_data_i : STD_LOGIC_VECTOR (31 downto 0);
signal wb_driver_addr_o : STD_LOGIC_VECTOR (3 downto 0) := X"0";
signal wb_driver_ack_i : STD_LOGIC;
signal wb_driver_rty_i : STD_LOGIC;
signal wb_driver_err_i : STD_LOGIC;
signal pf_wb_addr_o : STD_LOGIC;
signal rd_done_o : STD_LOGIC;
signal wr_done_o : STD_LOGIC;
signal i2c_addr_i : STD_LOGIC_VECTOR (6 downto 0);
--! Connections for the wishbone driver
signal s_wb_driver_data_i : STD_LOGIC_VECTOR(31 downto 0)
:= (others => '0');
signal s_wb_driver_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal s_wb_driver_addr_i : STD_LOGIC_VECTOR(3 downto 0)
:= (others => '0');
signal s_wb_driver_write_i : STD_LOGIC := '0';
signal s_wb_driver_write_done_o : STD_LOGIC;
signal s_wb_driver_read_i : STD_LOGIC := '0';
signal s_wb_driver_read_done_o : STD_LOGIC;
signal s_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0)
:= (others => '0');
signal s_wishbone_addr : STD_LOGIC_VECTOR(c_WB_ADDR_LENGTH - 1 downto 0)
:= (others => '0');
signal s_wr_data : STD_LOGIC_VECTOR(c_WR_DATA_LENGTH - 1 downto 0)
:= (others => '0');
signal s_rd_data : STD_LOGIC_VECTOR(c_RD_DATA_LENGTH - 1 downto 0);
signal s_i2c_driver_start : STD_LOGIC := '0';
signal s_i2c_driver_start_done : STD_LOGIC;
signal s_i2c_driver_pause : STD_LOGIC := '0';
signal s_i2c_driver_pause_done : STD_LOGIC;
signal s_i2c_driver_write : STD_LOGIC := '0';
signal s_i2c_driver_write_done : STD_LOGIC;
signal s_i2c_driver_read : STD_LOGIC := '0';
signal s_i2c_driver_read_done : STD_LOGIC;
--! Feedback mode by default
signal s_feedback_wb_bus : STD_LOGIC;
type i2c_start_op is (S0_READ,
S1_WRITE);
begin
i2c_addr_i(6 downto 5) <= "00";
i2c_addr_i(4 downto 0) <= std_logic_vector(c_VME_SLOT);
-- Instantiate the Unit Under Test (UUT)
uut: i2c_slave_top
port map (sda_oen => sda_slave_oen,
sda_i => sda_slave_i,
sda_o => sda_slave_o,
scl_oen => scl_slave_oen,
scl_i => scl_slave_i,
scl_o => scl_slave_o,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_we_o => wb_master_we_o,
wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_sel_i => wb_slave_sel_i,
wb_slave_we_i => wb_slave_we_i,
wb_slave_data_i => wb_slave_data_i,
wb_slave_data_o => wb_slave_data_o,
wb_slave_addr_i => wb_slave_addr_i,
wb_slave_ack_o => wb_slave_ack_o,
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
pf_wb_addr_o => pf_wb_addr_o,
rd_done_o => rd_done_o,
wr_done_o => wr_done_o,
i2c_addr_i => i2c_addr_i);
i2c_driver: i2c_master_driver
port map(tb_clk => wb_clk,
sda_master_i => sda_slave_o,
sda_master_o => sda_slave_i,
scl_master_o => scl_slave_i,
i2c_addr_op_i => s_i2c_addr_op,
wishbone_addr_i => s_wishbone_addr,
wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
start_i => s_i2c_driver_start,
start_done_o => s_i2c_driver_start_done,
pause_i => s_i2c_driver_pause,
pause_done_o => s_i2c_driver_pause_done,
write_i => s_i2c_driver_write,
write_done_o => s_i2c_driver_write_done,
read_i => s_i2c_driver_read,
read_done_o => s_i2c_driver_read_done);
wb_driver: wishbone_driver
generic map(g_WB_ADDR_LENGTH => wb_slave_addr_i'length,
g_WB_CLK_PERIOD => c_WB_CLK_PERIOD)
port map(wb_clk_i => wb_clk,
wb_rst_i => wb_rst_i,
wb_stb_o => wb_driver_stb_o,
wb_cyc_o => wb_driver_cyc_o,
wb_sel_o => wb_driver_sel_o,
wb_we_o => wb_driver_we_o,
wb_data_i => wb_driver_data_i,
wb_data_o => wb_driver_data_o,
wb_addr_o => wb_driver_addr_o,
wb_ack_i => wb_driver_ack_i,
wb_rty_i => wb_driver_rty_i,
wb_err_i => wb_driver_err_i,
data_i => s_wb_driver_data_i,
data_o => s_wb_driver_data_o,
addr_i => s_wb_driver_addr_i,
write_i => s_wb_driver_write_i,
write_done_o => s_wb_driver_write_done_o,
read_i => s_wb_driver_read_i,
read_done_o => s_wb_driver_read_done_o);
wb_slave_cyc_i <= wb_master_cyc_o when s_feedback_wb_bus = '1'
else wb_driver_cyc_o;
wb_slave_stb_i <= wb_master_stb_o when s_feedback_wb_bus = '1'
else wb_driver_stb_o;
wb_slave_sel_i <= wb_master_sel_o when s_feedback_wb_bus = '1'
else wb_driver_sel_o;
wb_slave_we_i <= wb_master_we_o when s_feedback_wb_bus = '1'
else wb_driver_we_o;
wb_slave_data_i <= wb_master_data_o when s_feedback_wb_bus = '1'
else wb_driver_data_o;
wb_slave_addr_i <= wb_master_addr_o(3 downto 0) when s_feedback_wb_bus = '1'
else wb_driver_sel_o;
wb_master_data_i <= wb_slave_data_o;
wb_master_ack_i <= wb_slave_ack_o;
wb_master_rty_i <= wb_slave_rty_o;
wb_master_err_i <= wb_slave_err_o;
wb_driver_data_i <= wb_slave_data_o;
wb_driver_ack_i <= wb_slave_ack_o;
wb_driver_rty_i <= wb_slave_rty_o;
wb_driver_err_i <= wb_slave_err_o;
--! Clock process definitions
wb_clk_process :process
begin
wb_clk <= '1';
wait for c_WB_CLK_PERIOD/2;
wb_clk <= '0';
wait for c_WB_CLK_PERIOD/2;
end process;
--! Stimulus process
p_i2c_tb: process
procedure set_i2c_wb_feedback is
begin
s_feedback_wb_bus <= '1';
wait until rising_edge(wb_clk);
end procedure;
procedure unset_i2c_wb_feedback is
begin
s_feedback_wb_bus <= '0';
wait until rising_edge(wb_clk);
end procedure;
procedure start_I2C is
begin
s_i2c_driver_start <= '1';
wait until rising_edge(s_i2c_driver_start_done);
wait until rising_edge(wb_clk);
s_i2c_driver_start <= '0';
end procedure;
procedure write_I2C(i2c_addr : STD_LOGIC_VECTOR(7 downto 0);
wb_addr : STD_LOGIC_VECTOR(s_wishbone_addr'length - 1 downto 0);
wr_data : STD_LOGIC_VECTOR(s_wr_data'length - 1 downto 0)) is
begin
wait until rising_edge(wb_clk);
s_i2c_addr_op <= i2c_addr;
s_wishbone_addr <= wb_addr;
s_wr_data <= wr_data;
s_i2c_driver_write <= '1';
wait until rising_edge(wb_clk);
s_i2c_driver_write <= '0';
wait until rising_edge(s_i2c_driver_write_done);
wait until rising_edge(wb_clk);
end procedure;
--! This procedure is a wrapper in case we want to address with VME
--! directions. Front padding is done with zeroes.
procedure write_I2C(vme_slot : UNSIGNED(4 downto 0);
wb_addr : STD_LOGIC_VECTOR(s_wishbone_addr'length - 1 downto 0);
wr_data : STD_LOGIC_VECTOR(s_wr_data'length - 1 downto 0)) is
variable v_i2c_addr : STD_LOGIC_VECTOR(7 downto 0);
begin
v_i2c_addr(7 downto 6) := "00";
v_i2c_addr(5 downto 1) := STD_LOGIC_VECTOR(vme_slot);
v_i2c_addr(0) := '0';
write_I2C(v_i2c_addr, wb_addr, wr_data);
end procedure;
procedure read_I2C(vme_slot : UNSIGNED(4 downto 0);
wb_addr : STD_LOGIC_VECTOR(s_wishbone_addr'length - 1 downto 0);
wr_data : STD_LOGIC_VECTOR(s_wr_data'length - 1 downto 0)) is
variable v_i2c_addr : STD_LOGIC_VECTOR(7 downto 0);
begin
v_i2c_addr(7 downto 6) := "00";
v_i2c_addr(5 downto 1) := STD_LOGIC_VECTOR(vme_slot);
v_i2c_addr(0) := '0';
wait until rising_edge(wb_clk);
-- i2c_master_driver
s_i2c_addr_op <= v_i2c_addr;
s_wishbone_addr <= wb_addr;
s_wr_data <= wr_data;
s_i2c_driver_read <= '1';
wait until rising_edge(wb_clk);
s_i2c_driver_read <= '0';
wait until rising_edge(s_i2c_driver_read_done);
wait until rising_edge(wb_clk);
end procedure;
begin
wb_rst_i <= '1';
wait for c_WB_CLK_PERIOD*10;
wb_rst_i <= '0';
--! First we place a write
set_i2c_wb_feedback;
start_I2C;
--! Try to write into DTX addr position
write_I2C(c_VME_SLOT, X"0002", X"B16B00B5");
wait for c_WB_CLK_PERIOD*25;
--! Then we read from the FPGA
--unset_i2c_wb_feedback;
start_I2C;
--! We read addr 1 (LT) via I2C
--! Then, the core internally prefetchs via wishbone and then
--! write the register into I2C to the master
read_I2C(c_VME_SLOT, X"BAB1", X"B16B00B5");
wait for c_WB_CLK_PERIOD*25;
end process;
end;
hdl/i2c_to_wb_bridge/test/i2c_tb_pkg.vhd deleted 100644 → 0
View file @ 9a04b242
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
package i2c_tb_pkg is
--! Clock period definitions
constant c_WB_CLK_PERIOD : time := 50 ns; -- @ 20 MHz
constant c_SCL_I_PERIOD : time := 10000 ns; -- @ 400 KHz
--! Will be used as the LSB of the I2C
constant c_VME_SLOT : UNSIGNED(4 downto 0) := "11110";
--! Length of some buses
constant c_WR_DATA_LENGTH : NATURAL := 32;
constant c_RD_DATA_LENGTH : NATURAL := 32;
constant c_WB_ADDR_LENGTH : NATURAL := 16;
component i2c_slave_top is
port (sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0));
end component;
component i2c_master_driver is
generic(g_WR_DATA_LENGTH : NATURAL := c_WR_DATA_LENGTH;
g_RD_DATA_LENGTH : NATURAL := c_RD_DATA_LENGTH;
g_WB_ADDR_LENGTH : NATURAL := c_WB_ADDR_LENGTH;
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
scl_master_o : out STD_LOGIC;
i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0);
wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(g_RD_DATA_LENGTH - 1 downto 0);
start_i : in STD_LOGIC;
start_done_o : out STD_LOGIC;
pause_i : in STD_LOGIC;
pause_done_o : out STD_LOGIC;
write_i : in STD_LOGIC;
write_done_o : out STD_LOGIC;
read_i : in STD_LOGIC;
read_done_o : out STD_LOGIC);
end component;
type I2C_master_driver_ctrl is
record
START : STD_LOGIC;
PAUSE : STD_LOGIC;
WRITE : STD_LOGIC;
READ : STD_LOGIC;
end record;
constant c_I2C_master_driver_ctrl_default : I2C_master_driver_ctrl
:=(START => '0',
PAUSE => '0',
WRITE => '0',
READ => '0');
end i2c_tb_pkg;
package body i2c_tb_pkg is
end i2c_tb_pkg;
hdl/i2c_to_wb_bridge/test/log/i2c_master_driver.txt deleted 100644 → 0
View file @ 9a04b242
1 OK WRITE [ADDRESS|0]
1 OK WRITE WISHBONE HIGH
1 OK WRITE WISHBONE LOW
1 OK WRITE READ DATA 0
1 OK WRITE READ DATA 1
1 OK WRITE READ DATA 2
1 OK WRITE READ DATA 3
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
hdl/i2c_to_wb_bridge/top/Manifest.py deleted 100644 → 0
View file @ 9a04b242
files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../rtl",
]
}
hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.ucf deleted 100644 → 0
View file @ 9a04b242
##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##----------------------------------------
#NET "RST" LOC = N20;
#NET "RST" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
#NET "CLK20_VCXO" LOC = E16;
#TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
##======================================
##-- FRONT PANEL TTLs
##======================================
##-------------------
##-- LEDs
##-------------------
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = LVTTL;
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = LVTTL;
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = LVTTL;
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = LVTTL;
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = LVTTL;
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = LVTTL;
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = LVTTL;
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = LVTTL;
##-------------------
##-- Front channel LEDs
##-------------------
#NET "PULSE_FRONT_LED_N[1]" LOC = H5;
#NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[1]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[1]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[2]" LOC = J6;
#NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[2]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[2]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[3]" LOC = K6;
#NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[3]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[3]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[4]" LOC = K5;
#NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[4]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[4]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[5]" LOC = M7;
#NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[5]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[5]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[6]" LOC = M6;
#NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[6]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[6]" SLEW = QUIETIO;
##-------------------
##-- Rear LEDs
##-------------------
#NET "PULSE_REAR_LED_N[1]" LOC = AB17;
#NET "PULSE_REAR_LED_N[1]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[1]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[1]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[2]" LOC = AB19;
#NET "PULSE_REAR_LED_N[2]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[2]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[2]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[3]" LOC = AA16;
#NET "PULSE_REAR_LED_N[3]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[3]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[3]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[4]" LOC = AA18;
#NET "PULSE_REAR_LED_N[4]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[4]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[4]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[5]" LOC = AB16;
#NET "PULSE_REAR_LED_N[5]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[5]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[5]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[6]" LOC = AB18;
#NET "PULSE_REAR_LED_N[6]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[6]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[6]" SLEW = QUIETIO;
###-------------------
###-- TTL trigger I/O
###-------------------
#NET "FPGA_INPUT_TTL_N[1]" LOC = T2;
#NET "FPGA_INPUT_TTL_N[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[2]" LOC = U3;
#NET "FPGA_INPUT_TTL_N[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[3]" LOC = V5;
#NET "FPGA_INPUT_TTL_N[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[4]" LOC = W4;
#NET "FPGA_INPUT_TTL_N[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[5]" LOC = T6;
#NET "FPGA_INPUT_TTL_N[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[6]" LOC = T3;
#NET "FPGA_INPUT_TTL_N[6]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[1]" LOC = C1;
#NET "FPGA_OUT_TTL[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[2]" LOC = F2;
#NET "FPGA_OUT_TTL[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[3]" LOC = F5;
#NET "FPGA_OUT_TTL[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[4]" LOC = H4;
#NET "FPGA_OUT_TTL[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[5]" LOC = J4;
#NET "FPGA_OUT_TTL[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[6]" LOC = H2;
#NET "FPGA_OUT_TTL[6]" IOSTANDARD = LVCMOS33;
##-------------------
##-- Inverted TTL I/O
##--
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
#NET "INV_IN_N[1]" LOC = V2;
#NET "INV_IN_N[1]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[2]" LOC = W3;
#NET "INV_IN_N[2]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[3]" LOC = Y2;
#NET "INV_IN_N[3]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[4]" LOC = AA2;
#NET "INV_IN_N[4]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[1]" LOC = J3;
#NET "INV_OUT[1]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[2]" LOC = L3;
#NET "INV_OUT[2]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[3]" LOC = M3;
#NET "INV_OUT[3]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[4]" LOC = P2;
#NET "INV_OUT[4]" IOSTANDARD = LVCMOS33;
##======================================
##-- RTM signals
##======================================
##-- Blocking I/O
##
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
#NET "FPGA_BLO_IN[1]" LOC = Y9;
#NET "FPGA_BLO_IN[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[2]" LOC = AA10;
#NET "FPGA_BLO_IN[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[3]" LOC = W12;
#NET "FPGA_BLO_IN[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[4]" LOC = AA6;
#NET "FPGA_BLO_IN[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[5]" LOC = Y7;
#NET "FPGA_BLO_IN[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[6]" LOC = AA8;
#NET "FPGA_BLO_IN[6]" IOSTANDARD = LVCMOS33;
#
#NET "FPGA_TRIG_BLO[1]" LOC = W9;
#NET "FPGA_TRIG_BLO[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[2]" LOC = T10;
#NET "FPGA_TRIG_BLO[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[3]" LOC = V7;
#NET "FPGA_TRIG_BLO[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[4]" LOC = U9;
#NET "FPGA_TRIG_BLO[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[5]" LOC = T8;
#NET "FPGA_TRIG_BLO[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[6]" LOC = R9;
#NET "FPGA_TRIG_BLO[6]" IOSTANDARD = LVCMOS33;
###======================================
###-- VME CONNECTOR SIGNALS
###======================================
###-------------------
###-- I2C lines
###-------------------
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = LVTTL;
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = LVTTL;
NET "SCL_O" DRIVE = 4;
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = LVTTL;
NET "SCL_OE" DRIVE = 4;
# NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = LVTTL;
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = LVTTL;
NET "SDA_O" SLEW = FAST;
NET "SDA_O" DRIVE = 4;
# NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = LVTTL;
NET "SDA_OE" SLEW = FAST;
NET "SDA_OE" DRIVE = 4;
# NET "SDA_OE" PULLDOWN;
###-------------------
###-- Geographical Address
###-------------------
NET "FPGA_GA[0]" LOC = H20;
NET "FPGA_GA[0]" IOSTANDARD = LVTTL;
NET "FPGA_GA[1]" LOC = J20;
NET "FPGA_GA[1]" IOSTANDARD = LVTTL;
NET "FPGA_GA[2]" LOC = K19;
NET "FPGA_GA[2]" IOSTANDARD = LVTTL;
NET "FPGA_GA[3]" LOC = K20;
NET "FPGA_GA[3]" IOSTANDARD = LVTTL;
NET "FPGA_GA[4]" LOC = L19;
NET "FPGA_GA[4]" IOSTANDARD = LVTTL;
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = LVTTL;
###-------------------
###-- ROM memory
###-------------------
#NET "FPGA_PROM_CCLK" LOC = Y20;
#NET "FPGA_PROM_CCLK" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_CSO_B_N" LOC = AA3;
#NET "FPGA_PROM_CSO_B_N" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_DIN" LOC = AA20;
#NET "FPGA_PROM_DIN" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_MOSI" LOC = AB20;
#NET "FPGA_PROM_MOSI" IOSTANDARD = LVTTL;
#
#
####======================================
####-- WHITE RABBIT
####======================================
####-------------------
####-- Thermo for UID
####-------------------
##NET "THERMOMETER" LOC = B1;
## NET "THERMOMETER" IOSTANDARD = "LVCMOS25";
####-------------------
####-- DACs control
####--
####-- + CMOS 3.3V input
####-------------------
##NET "FPGA_PLLDAC1_DIN" LOC = AB14;
## NET "FPGA_PLLDAC1_DIN" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SCLK" LOC = AA14;
## NET "FPGA_PLLDAC1_SCLK" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
## NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_DIN" LOC = W14;
## NET "FPGA_PLLDAC2_DIN" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SCLK" LOC = Y14;
## NET "FPGA_PLLDAC2_SCLK" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SYNC_N" LOC = W13;
## NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
####-------------------
####-- SFP connection
####-------------------
##NET "FPGA_SFP_LOS" LOC = G3;
## NET "FPGA_SFP_LOS" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF0" LOC = K8;
## NET "FPGA_SFP_MOD_DEF0" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_RATE_SELECT" LOC = C4;
## NET "FPGA_SFP_RATE_SELECT" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF1" LOC = G4;
## NET "FPGA_SFP_MOD_DEF1" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF2" LOC = F3;
## NET "FPGA_SFP_MOD_DEF2" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_TX_DISABLE" LOC = E4;
## NET "FPGA_SFP_TX_DISABLE" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_TX_FAULT" LOC = D2;
## NET "FPGA_SFP_TX_FAULT" IOSTANDARD = "LVCMOS33";
####-------------------
####-- FPGA MGT lines
####-------------------
##NET "FPGAMGTCLK0_P" LOC = A10;
## NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
##NET "FPGAMGTCLK0_N" LOC = B10;
## NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_P" LOC = D7;
## NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_N" LOC = C7;
## NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_P" LOC = B6;
## NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_N" LOC = A6;
## NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
#
#
###======================================
###-- ADDITIONAL PINS
###======================================
NET "FPGA_OE" LOC = R3;
NET "FPGA_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_OE" DRIVE = 4;
NET "FPGA_OE" SLEW = QUIETIO;
NET "FPGA_BLO_OE" LOC = P5;
NET "FPGA_BLO_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_OE" DRIVE = 4;
NET "FPGA_BLO_OE" SLEW = QUIETIO;
NET "FPGA_TRIG_TTL_OE" LOC = N3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_TTL_OE" DRIVE = 4;
NET "FPGA_TRIG_TTL_OE" SLEW = QUIETIO;
NET "FPGA_INV_OE" LOC = P6;
NET "FPGA_INV_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_INV_OE" DRIVE = 4;
NET "FPGA_INV_OE" SLEW = QUIETIO;
###-------------------
###-- Configuration Switches
###
###-- Schematics name EXTRA_SWITCH_*
###---- renamed to EXTRA_SWITCH[*]
###-------------------
#NET "EXTRA_SWITCH[1]" LOC = F22;
#NET "EXTRA_SWITCH[1]" IOSTANDARD = LVCMOS33;
## NET "EXTRA_SWITCH[2]" LOC = G22;
## NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[3]" LOC = H21;
## NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[4]" LOC = H22;
## NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[5]" LOC = J22;
## NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[6]" LOC = K21;
## NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[7]" LOC = K22;
## NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVCMOS33";
NET "LEVEL" LOC = L22;
NET "LEVEL" IOSTANDARD = LVCMOS33;
##-------------------
##-- Motherboard and piggyback IDs
##-------------------
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
####-------------------
####-- General purpose
####-------------------
## NET "FPGA_HEADER_OUT_N[1]" LOC = F15;
## NET "FPGA_HEADER_OUT_N[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[2]" LOC = F16;
## NET "FPGA_HEADER_OUT_N[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[3]" LOC = F17;
## NET "FPGA_HEADER_OUT_N[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[4]" LOC = F14;
## NET "FPGA_HEADER_OUT_N[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[5]" LOC = H14;
## NET "FPGA_HEADER_OUT_N[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[6]" LOC = H13;
## NET "FPGA_HEADER_OUT_N[6]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[1]" LOC = A17;
## NET "FPGA_HEADER_IN_N[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[2]" LOC = A18;
## NET "FPGA_HEADER_IN_N[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[3]" LOC = B18;
## NET "FPGA_HEADER_IN_N[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[4]" LOC = A19;
## NET "FPGA_HEADER_IN_N[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[5]" LOC = A20;
## NET "FPGA_HEADER_IN_N[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[6]" LOC = B20;
## NET "FPGA_HEADER_IN_N[6]" IOSTANDARD = "LVCMOS33";
hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.vhd deleted 100644 → 0
View file @ 9a04b242
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-trig-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo_v2.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
-- Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library unisim;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
entity conv_ttl_blo_v2 is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- RST : in std_logic;
-- CLK20_VCXO : in std_logic;
FPGA_CLK_P : in std_logic; --Using the 125MHz clock
FPGA_CLK_N : in std_logic;
-- LEDs
LED_CTRL0 : out std_logic;
LED_CTRL0_OEN : out std_logic;
LED_CTRL1 : out std_logic;
LED_CTRL1_OEN : out std_logic;
LED_MULTICAST_2_0 : out std_logic;
LED_MULTICAST_3_1 : out std_logic;
LED_WR_GMT_TTL_TTLN : out std_logic;
LED_WR_LINK_SYSERROR : out std_logic;
LED_WR_OK_SYSPW : out std_logic;
LED_WR_OWNADDR_I2C : out std_logic;
-- I/Os for pulses
-- PULSE_FRONT_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
-- PULSE_REAR_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_INPUT_TTL_N : in std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_OUT_TTL : out std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_BLO_IN : in std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_TRIG_BLO : out std_logic_vector(g_nr_ttl_chan downto 1);
-- INV_IN_N : in std_logic_vector(g_nr_inv_chan downto 1);
-- INV_OUT : out std_logic_vector(g_nr_inv_chan downto 1);
-- Lines for the i2c_slave
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_OE : out std_logic;
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_OE : out std_logic;
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
--
-- -- Pins of the SPI interface to write into the Flash memory
-- FPGA_PROM_CCLK : out std_logic;
-- FPGA_PROM_CSO_B_N : out std_logic;
-- FPGA_PROM_DIN : in std_logic;
-- FPGA_PROM_MOSI : out std_logic;
--
FPGA_OE : out std_logic;
FPGA_BLO_OE : out std_logic;
FPGA_TRIG_TTL_OE : out std_logic;
FPGA_INV_OE : out std_logic;
-- TTL/INV_TTL_N
LEVEL : in std_logic;
-- EXTRA_SWITCH : in std_logic_vector(7 downto 1);
-- It allows power sequencing of the
-- 24V rail after a security given delay
MR_N : out std_logic;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
FPGA_RTMM_N : in std_logic_vector(2 downto 0);
FPGA_RTMP_N : in std_logic_vector(2 downto 0)
);
end conv_ttl_blo_v2;
architecture behav of conv_ttl_blo_v2 is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : NATURAL := 1;
constant c_nr_slaves : NATURAL := 1;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word aligned
-----------------------------------------
-- M25P32 [0200-03FF]
-- MULTIBOOT [0080-00CF]
-- I2C_SLAVE [0040-007F]
-- SR [0000-003F]
-----------------------------------------
-- base address definitions
constant c_addr_i2c_bridge : t_wishbone_address := X"00000040";
constant c_addr_multiboot : t_wishbone_address := X"00000080";
constant c_addr_m25p32 : t_wishbone_address := X"00000200";
-- address mask definitions
-- 64 words per page: 6 + 1 bits
constant c_mask_i2c_bridge : t_wishbone_address := X"FFFFFFC0";
constant c_mask_multiboot : t_wishbone_address := X"FFFFFFC0";
constant c_mask_m25p32 : t_wishbone_address := X"FFFFFE00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_addr_m25p32,
--c_addr_multiboot,
(others => c_addr_i2c_bridge)
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_mask_m25p32,
-- c_mask_multiboot,
(others => c_mask_i2c_bridge)
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component i2c_to_wb_bridge is
port
(
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
pf_wb_addr_o : out std_logic;
rd_done_o : out std_logic;
wr_done_o : out std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end component i2c_to_wb_bridge;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk_125 : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Signals for pulse generation triggers
signal trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
-- Pulse status LED signals
signal front_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
-- Output enable signals
signal oe, ttl_oe, blo_oe, inv_oe : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_nr_slaves - 1 downto 0);
-- I2C bridge signals
signal i2c_rd_done, i2c_wr_done : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf: IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => FPGA_CLK_P,
IB => FPGA_CLK_N,
O => clk_125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen: reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk_125,
rst_n_o => rst_n
);
rst <= not rst_n;
MR_N <= rst_n;
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe: process(clk_125)
begin
if rising_edge(clk_125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '0';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
FPGA_OE <= oe;
FPGA_BLO_OE <= blo_oe;
FPGA_TRIG_TTL_OE <= ttl_oe;
FPGA_INV_OE <= inv_oe;
--============================================================================
-- I2C bridge logic
--============================================================================
i2c_addr <= "10" & FPGA_GA;
cmp_bridge: i2c_to_wb_bridge
port map
(
sda_en_o => SDA_OE,
sda_i => SDA_I,
sda_o => SDA_O,
scl_en_o => SCL_OE,
scl_i => SCL_I,
scl_o => SCL_O,
clk_i => clk_125,
rst_i => rst,
wb_master_stb_o => xbar_slave_in(0).stb,
wb_master_cyc_o => xbar_slave_in(0).cyc,
wb_master_sel_o => xbar_slave_in(0).sel,
wb_master_we_o => xbar_slave_in(0).we,
wb_master_dat_i => xbar_slave_out(0).dat,
wb_master_dat_o => xbar_slave_in(0).dat,
wb_master_adr_o => xbar_slave_in(0).adr(15 downto 0),
wb_master_ack_i => xbar_slave_out(0).ack,
wb_master_rty_i => xbar_slave_out(0).rty,
wb_master_err_i => xbar_slave_out(0).err,
wb_slave_stb_i => xbar_master_out(0).stb,
wb_slave_cyc_i => xbar_master_out(0).cyc,
wb_slave_sel_i => xbar_master_out(0).sel,
wb_slave_we_i => xbar_master_out(0).we,
wb_slave_dat_i => xbar_master_out(0).dat,
wb_slave_dat_o => xbar_master_in(0).dat,
wb_slave_adr_i => xbar_master_out(0).adr(5 downto 2),
wb_slave_ack_o => xbar_master_in(0).ack,
wb_slave_rty_o => xbar_master_in(0).rty,
wb_slave_err_o => xbar_master_in(0).err,
pf_wb_addr_o => open,
rd_done_o => i2c_rd_done,
wr_done_o => i2c_wr_done,
i2c_addr_i => i2c_addr
);
xbar_slave_in(0).adr(31 downto 16) <= (others => '0');
-- Process to set the I2C_UP signal for display on the front panel
-- of the front module. The I2C_UP signal is permanently set once an
-- I2C transfer has successfully completed, as signaled by the RD_DONE
-- and WR_DONE outputs of the I2C slave.
p_i2c_up: process (clk_125) is
begin
if rising_edge(clk_125) then
if (rst_n = '0') then
i2c_up <= '0';
elsif (i2c_rd_done = '1') or (i2c_wr_done = '1') then
i2c_up <= '1';
end if;
end if;
end process p_i2c_up;
--============================================================================
-- Instantiation and connection of a Wishbone crossbar module
--============================================================================
xbar_master_in(0).stall <= '0';
xbar_master_in(0).int <= '0';
cmp_wb_crossbar: xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
-- Address of the slaves connected
-- It should be noted that the default address length is 32
-- In our project only 16 bits are addressable
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk_125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C valid
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (i2c_up = '1') else
c_LED_RED;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (LEVEL = '1') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl: bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
led_intensity_i => "0011111",
led_state_i => bicolor_led_state,
column_o(0) => LED_WR_OWNADDR_I2C,
column_o(1) => LED_WR_GMT_TTL_TTLN,
column_o(2) => LED_WR_LINK_SYSERROR,
column_o(3) => LED_WR_OK_SYSPW,
column_o(4) => LED_MULTICAST_2_0,
column_o(5) => LED_MULTICAST_3_1,
line_o(0) => LED_CTRL0,
line_o(1) => LED_CTRL1,
line_oen_o(0) => LED_CTRL0_OEN,
line_oen_o(1) => LED_CTRL1_OEN
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm <= not FPGA_RTMM_N;
rtmp <= not FPGA_RTMP_N;
cmp_rtm_detector: rtm_detector
port map
(
rtmm_i => rtmm,
rtmp_i => rtmp,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
end behav;
hdl/pulse_generator/rtl/Manifest.py
View file @ 53c9ec7c
files = [
"pulse_generator.vhd"
]
files = "pulse_generator.vhd"
modules = {
"local" : [
"../../glitch_filt",
"../../../../ip_cores/general-cores"
]
}
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ 53c9ec7c
......@@ -61,28 +61,44 @@ entity pulse_generator is
(
-- Pulse width, in number of clk_i cycles
g_pulse_width : natural := 15;
-- Length of glitch filter; the longer the glitch filter, the
-- longer the input trigger needs to be.
g_glitch_filt_len : natural := 6
-- Glitch filter length:
-- g_glitch_filt_len=1 => trigger width should be > 1 clk_i cycle
-- g_glitch_filt_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse type input
-- '1' - TYPE 1 (glitch-sensitive, without output jitter)
-- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
trig_i : in std_logic;
-- Pulse output, active-high
pulse_o : out std_logic
-- latency:
-- TYPE 1 pulse: none
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end entity pulse_generator;
architecture behav of pulse_generator is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (ST_IDLE, ST_PULSE_TYPE1, ST_PULSE_TYPE2);
--============================================================================
-- Function and procedure declarations
--============================================================================
......@@ -96,20 +112,54 @@ architecture behav of pulse_generator is
return(63);
end function f_log2_size;
--============================================================================
-- Component declarations
--============================================================================
component glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end component glitch_filt;
--============================================================================
-- Signal declarations
--============================================================================
-- Deglitched trigger
signal trig_degl : std_logic;
signal trig_degl_d0 : std_logic;
-- Pulse length counter
signal width_cnt : unsigned(f_log2_size(g_pulse_width)-1 downto 0);
-- Pulse-specific signals
signal pulse : std_logic;
signal pulse_reject : std_logic;
signal pulse_type1 : std_logic;
signal pulse_type1_d0 : std_logic;
signal pulse_type1_d1 : std_logic;
signal pulse_type1_d2 : std_logic;
signal pulse_rst : std_logic;
-- Glitch filter
signal glitch_filt : std_logic_vector(g_glitch_filt_len downto 0);
signal glitch_filt_d0 : std_logic;
signal pulse_type2 : std_logic;
-- FSM signal
signal state : t_state;
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -118,91 +168,146 @@ begin
--============================================================================
-- Output logic
--============================================================================
pulse_o <= trig_i when (pulse_reject = '0') else
pulse;
--============================================================================
-- Glitch filtration logic
--============================================================================
glitch_filt(0) <= trig_i;
gen_glitch_filt: if (g_glitch_filt_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_glitch_filt_len downto 1) <= (others => '0');
else
glitch_filt(g_glitch_filt_len downto 1) <= glitch_filt(g_glitch_filt_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
pulse_o <= pulse_type1 when (pulse_type_i = '1') else
pulse_type2;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
-- Generate the pulse on rising edge of trig_i
p_pulse_type1: process(pulse_rst, trig_i)
begin
if (pulse_rst = '1') then
pulse_type1 <= '0';
elsif rising_edge(trig_i) then
pulse_type1 <= '1';
end if;
end process p_pulse_type1;
-- and synchronize it in clk_i domain
p_sync_pulse_type1: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
width_cnt <= (others => '0');
pulse <= '0';
glitch_filt_d0 <= '0';
pulse_type1_d0 <= '0';
pulse_type1_d1 <= '0';
pulse_type1_d2 <= '0';
else
-- FF to detect rising edge on glitch filter output
glitch_filt_d0 <= glitch_filt(g_glitch_filt_len);
-- Start outputting pulse with controlled length once the glitch filter
-- has stabilized
if (glitch_filt = (glitch_filt'range => '1')) and (glitch_filt_d0 = '0') then
pulse <= '1';
end if;
if (pulse = '1') then
width_cnt <= width_cnt + 1;
-- Reset pulse length counter and clear output pulse when reached max
-- length. The max length is given by the module input, minus the
-- glitch filter length (due to the flip-flops the pulse goes through).
--
-- The "-2" is first because the counter starts from zero, thus the max
-- length should be pulse_len-1, and second because the pulse is set
-- on the clock edge following the glitch filter output settling to all
-- ones.
if (width_cnt = g_pulse_width-g_glitch_filt_len-2) then
width_cnt <= (others => '0');
pulse <= '0';
end if;
end if;
pulse_type1_d0 <= pulse_type1;
pulse_type1_d1 <= pulse_type1_d0;
pulse_type1_d2 <= pulse_type1_d1;
end if;
end if;
end process p_gen_pulse;
-- This process is used to reject pulses longer than the pulse width defined
-- via the generic. This safeguards the blocking output transformers from
-- reaching saturation current when an INV-TTL signal is applied at the TTL
-- input without setting the LEVEL switch appropriately. It also guards the
-- transformers when no signal is present at the TTL input and the LEVEL switch
-- is set to INV-TTL.
--
-- When the pulse signal is set, the pulse_reject signal is also set. The
-- pulse_reject signal is cleared when the pulse input has settled back to '0'.
--
-- By using the pulse_reject signal as an enable for the output, the pulse output
-- width is cut to the desired size.
p_pulse_reject: process(clk_i)
end process p_sync_pulse_type1;
-- Type 2 pulse is generated when the FSM is counting to the pulse width
p_pulse_type2: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_reject <= '1';
elsif (pulse = '1') then
pulse_reject <= '1';
elsif (trig_i = '0') then
pulse_reject <= '0';
pulse_type2 <= '0';
elsif (state = ST_PULSE_TYPE2) then
pulse_type2 <= '1';
else
pulse_type2 <= '0';
end if;
end if;
end process p_pulse_reject;
end process p_pulse_type2;
--============================================================================
-- Glitch filtration logic
--============================================================================
cmp_glitch_filt: glitch_filt
generic map
(
g_len => g_glitch_filt_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => trig_i,
dat_o => trig_degl
);
--============================================================================
-- Pulse width adjustment logic
--============================================================================
p_pulse_width: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= ST_IDLE;
pulse_rst <= '1';
width_cnt <= (others => '0');
trig_degl_d0 <= '0';
else
-- Deglitched trigger delay
trig_degl_d0 <= trig_degl;
-- State machine
case state is
---------------------------------------------------------------------
-- ST_IDLE
---------------------------------------------------------------------
-- Clear all values and go to type 1 or type 2 pulse generation
-- when the appropriate input arrives
---------------------------------------------------------------------
when ST_IDLE =>
width_cnt <= (others => '0');
pulse_rst <= '0';
if (pulse_type_i = '1') then
if (pulse_type1_d1 = '1') and (pulse_type1_d2 = '0') then
state <= ST_PULSE_TYPE1;
end if;
else
if (trig_degl = '1') and (trig_degl_d0 = '0') then
state <= ST_PULSE_TYPE2;
end if;
end if;
---------------------------------------------------------------------
-- ST_PULSE_TYPE1
---------------------------------------------------------------------
-- Increment width counter to maximum value, then generate reset
-- signal for type 1 pulse.
--
-- Max value: g_pulse_width-5 due to:
-- 1. width_cnt starts from 0 => g_pulse_width-1
-- 2. three cycle delay from FFs in gc_sync_ffs
-- 3. one clock cycle delay for switching from ST_IDLE to ST_PULSE_TYPE1
---------------------------------------------------------------------
when ST_PULSE_TYPE1 =>
width_cnt <= width_cnt + 1;
if (width_cnt = g_pulse_width - 5) then
pulse_rst <= '1';
state <= ST_IDLE;
end if;
---------------------------------------------------------------------
-- ST_PULSE_TYPE2
---------------------------------------------------------------------
-- Increment counter to max value and generate type 2 pulse while
-- incrementing.
--
-- Max value: g_pulse_width, because we start outputting the
-- pulse while already in this state, on the cycle when
-- width_cnt = 1
---------------------------------------------------------------------
when ST_PULSE_TYPE2 =>
width_cnt <= width_cnt + 1;
if (width_cnt = g_pulse_width - 1) then
pulse_rst <= '1';
state <= ST_IDLE;
end if;
when others =>
state <= ST_IDLE;
end case;
end if;
end if;
end process p_pulse_width;
end architecture behav;
--==============================================================================
......
hdl/pulse_generator/sim/run.do
View file @ 53c9ec7c
vlib work
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../old_rep_test/rtl/pulse_gen.vhd"
vcom -explicit -93 "../../glitch_filt/rtl/glitch_filt.vhd"
vcom -explicit -93 "../rtl/pulse_generator.vhd"
vcom -explicit -93 "testbench.vhd"
......
hdl/pulse_generator/sim/testbench.vhd
View file @ 53c9ec7c
......@@ -63,12 +63,13 @@ architecture behav of testbench is
generic
(
g_pulse_width : natural := 15;
g_glitch_filt_len : natural := 6
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_type_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
);
......@@ -93,6 +94,7 @@ architecture behav of testbench is
signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
signal actual_trig : std_logic := '0';
signal actual_pulse : std_logic := '0';
signal ptype : std_logic;
--==============================================================================
-- architecture begin
......@@ -104,14 +106,15 @@ begin
generic map
(
g_pulse_width => 125,
g_glitch_filt_len => 6
g_glitch_filt_len => 4
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
trig_i => actual_trig,
pulse_o => pulse
clk_i => clk,
rst_n_i => rst_n,
pulse_type_i => ptype,
trig_i => actual_trig,
pulse_o => pulse
);
-- CLOCK GENERATION
......@@ -150,16 +153,22 @@ begin
rst_n_i => rst_n,
pulse_o => trig
);
actual_trig <= '1'; --trig;
actual_trig <= trig;
actual_pulse <= pulse;
lvl_n <= not lvl;
cmp_pulse_gen2: pulse_gen
generic map
(
g_pwidth => 1033,
g_freq => 2066
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_o => ptype
);
lvl <= '1';
--trig <= '1';
end architecture behav;
--==============================================================================
-- architecture end
......
hdl/pulse_generator/sim/transcript
View file @ 53c9ec7c
......@@ -15,8 +15,8 @@ do run.do
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -46,71 +46,8 @@ do run.do
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
add wave \
sim:/testbench/DUT/pulse_reject
restart; run 100 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# -- Compiling entity glitch_filt
# -- Compiling architecture behav of glitch_filt
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
......@@ -127,323 +64,20 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "pulse_generator(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.glitch_filt(behav)#1
# Loading work.pulse_gen(behav)#1
# Loading work.pulse_gen(behav)#2
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
add wave \
sim:/testbench/DUT/pulse_reject
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/hdl/pulse_generator/sim/wave.do
restart; run 100 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -451,8 +85,8 @@ do run.do
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -482,60 +116,8 @@ do run.do
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# -- Compiling entity glitch_filt
# -- Compiling architecture behav of glitch_filt
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
......@@ -552,13 +134,16 @@ do run.do
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "pulse_generator(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.glitch_filt(behav)#1
# Loading work.pulse_gen(behav)#1
# Loading work.pulse_gen(behav)#2
# hexadecimal
# 0 ps
# 105 us
hdl/pulse_generator/sim/wave.do
View file @ 53c9ec7c
......@@ -4,15 +4,21 @@ add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/ptype
add wave -noupdate /testbench/pulse
add wave -noupdate -divider internal
add wave -noupdate /testbench/DUT/glitch_filt
add wave -noupdate /testbench/DUT/pulse
add wave -noupdate /testbench/DUT/pulse_reject
add wave -noupdate /testbench/DUT/width_cnt
add wave -noupdate /testbench/DUT/state
add wave -noupdate /testbench/DUT/pulse_o
add wave -noupdate /testbench/DUT/pulse_type1
add wave -noupdate /testbench/DUT/pulse_type1_d0
add wave -noupdate /testbench/DUT/pulse_type1_d1
add wave -noupdate /testbench/DUT/pulse_type1_d2
add wave -noupdate /testbench/DUT/pulse_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {12112676 ps} 0}
WaveRestoreCursors {{Cursor 2} {16080000 ps} 0}
configure wave -namecolwidth 233
configure wave -valuecolwidth 91
configure wave -valuecolwidth 132
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
......@@ -25,4 +31,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {105 us}
WaveRestoreZoom {0 ps} {102112676 ps}
hdl/release/syn/Makefile
View file @ 53c9ec7c
......@@ -42,7 +42,100 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd \
../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
conv_ttl_blo_v2.xise
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 53c9ec7c
......@@ -55,6 +55,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo_v2.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo_v2.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo_v2.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_v2_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_v2_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.mrp" xil_pn:subbranch="Map"/>
......@@ -77,35 +78,37 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1363103684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1363103684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1363103684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1363103684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1363103684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1363103684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1363103684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009896" xil_pn:in_ck="-1985142147321250132" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363009882">
<transform xil_pn:end_ts="1363164504" xil_pn:in_ck="-88236163103343582" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363164492">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
......@@ -121,11 +124,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1363009896" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1363009896">
<transform xil_pn:end_ts="1363104090" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1363104090">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363009903" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363009896">
<transform xil_pn:end_ts="1363164509" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363164504">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,7 +137,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363009934" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363009903">
<transform xil_pn:end_ts="1363164539" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363164509">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
......@@ -149,8 +152,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1363009963" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363009934">
<transform xil_pn:end_ts="1363164570" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363164539">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ncd"/>
......@@ -163,8 +167,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363009981" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363009963">
<transform xil_pn:end_ts="1363164588" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363164570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
......@@ -174,7 +179,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1363009981" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363009981">
<transform xil_pn:end_ts="1363164589" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363164588">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
......@@ -184,7 +189,7 @@
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363009963" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363009955">
<transform xil_pn:end_ts="1363164570" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363164561">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 53c9ec7c
......@@ -78,6 +78,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -343,22 +344,49 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../pulse_generator/rtl/pulse_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
</files>
......
hdl/release/top/conv_ttl_blo_v2.ucf
View file @ 53c9ec7c
......@@ -338,20 +338,20 @@ NET "FPGA_INV_OE" SLEW = QUIETIO;
###-- Schematics name EXTRA_SWITCH_*
###---- renamed to EXTRA_SWITCH[*]
###-------------------
#NET "EXTRA_SWITCH[1]" LOC = F22;
#NET "EXTRA_SWITCH[1]" IOSTANDARD = LVCMOS33;
## NET "EXTRA_SWITCH[2]" LOC = G22;
## NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[3]" LOC = H21;
## NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[4]" LOC = H22;
## NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[5]" LOC = J22;
## NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[6]" LOC = K21;
## NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[7]" LOC = K22;
## NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[1]" LOC = F22;
NET "EXTRA_SWITCH[1]" IOSTANDARD = LVCMOS33;
NET "EXTRA_SWITCH[2]" LOC = G22;
NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[3]" LOC = H21;
NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[4]" LOC = H22;
NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[5]" LOC = J22;
NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[6]" LOC = K21;
NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[7]" LOC = K22;
NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVCMOS33";
NET "LEVEL" LOC = L22;
NET "LEVEL" IOSTANDARD = LVCMOS33;
##-------------------
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 53c9ec7c
......@@ -96,7 +96,7 @@ entity conv_ttl_blo_v2 is
--TTL/INV_TTL_N
LEVEL : in std_logic;
-- EXTRA_SWITCH : in std_logic_vector(7 downto 1);
EXTRA_SWITCH : in std_logic_vector(7 downto 1);
-- It allows power sequencing of the
-- 24V rail after a security given delay
......@@ -136,15 +136,35 @@ architecture behav of conv_ttl_blo_v2 is
component pulse_generator is
generic
(
-- Pulse width, in number of clk_i cycles
g_pulse_width : natural := 15;
g_glitch_filt_len : natural := 6
-- Glitch filter length:
-- g_glitch_filt_len=1 => trigger width should be > 1 clk_i cycle
-- g_glitch_filt_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse type input
-- '1' - TYPE 1 (glitch-sensitive, without output jitter)
-- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- TYPE 1 pulse: none
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end component pulse_generator;
......@@ -270,7 +290,7 @@ begin
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
blo_oe <= '0';
ttl_oe <= '1';
inv_oe <= '1';
end if;
......@@ -301,10 +321,11 @@ begin
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
trig_i => trig(i),
pulse_o => pulse_outputs(i)
clk_i => clk_125,
rst_n_i => rst_n,
pulse_type_i => EXTRA_SWITCH(1),
trig_i => trig(i),
pulse_o => pulse_outputs(i)
);
-- Status LED pulse generators
......@@ -316,10 +337,11 @@ begin
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
trig_i => trig(i),
pulse_o => pulse_leds(i)
clk_i => clk_125,
rst_n_i => rst_n,
pulse_type_i => EXTRA_SWITCH(1),
trig_i => trig(i),
pulse_o => pulse_leds(i)
);
end generate gen_ttl_pulse_generators;
......@@ -327,7 +349,7 @@ begin
FPGA_OUT_TTL <= pulse_outputs;
FPGA_TRIG_BLO <= pulse_outputs;
-- Pulse status LEDs assignments
-- Pulse status LED output assignments
PULSE_FRONT_LED_N <= (not pulse_leds) when (ttl_oe = '1') else
(others => '0');
PULSE_REAR_LED_N <= (not pulse_leds) when (blo_oe = '1') else
......@@ -350,10 +372,11 @@ begin
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
trig_i => trig_inv(i),
pulse_o => inv_outputs(i)
clk_i => clk_125,
rst_n_i => rst_n,
pulse_type_i => EXTRA_SWITCH(1),
trig_i => trig_inv(i),
pulse_o => inv_outputs(i)
);
end generate gen_inv_pulse_generators;
......
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