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Commit 62b1c43a authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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i2c documentation up-to-date. Added .gitignore in the i2c_slave_wb_master… 

i2c documentation up-to-date. Added .gitignore in the i2c_slave_wb_master folder. Everything is correctly synched in this folder.
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hdl/ctdah_lib/test/wishbone_driver.vhd
View file @ 62b1c43a
......@@ -24,7 +24,7 @@ entity wishbone_driver is
wb_rty_i : in STD_LOGIC;
wb_err_i : in STD_LOGIC;
data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR(g_WB_DATA_I_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
......@@ -34,7 +34,7 @@ entity wishbone_driver is
read_done_o : out STD_LOGIC);
end wishbone_driver;
architecture Behavioral of wishbone_driver is
architecture Behavioral of wishbone_driver is
begin
......@@ -74,15 +74,15 @@ begin
wb_sel_o <= (others => '0');
write_done_o <= '1';
else
wb_stb_o <= '0';
wb_cyc_o <= '0';
wb_sel_o <= (others => '0');
wb_stb_o <= '0';
wb_cyc_o <= '0';
wb_sel_o <= (others => '0');
wb_we_o <= '0';
wb_data_o <= (others => '0');
wb_addr_o <= (others => '0');
data_o <= (others => '0');
write_done_o <= '0';
read_done_o <= '0';
read_done_o <= '0';
end if;
wait until rising_edge(wb_clk_i);
end process;
......
hdl/ctdah_lib/test/wishbone_driver_pkg.vhd
View file @ 62b1c43a
......@@ -11,7 +11,7 @@ package wishbone_driver_pkg is
g_WB_CLK_PERIOD : TIME := 50 ns);
port(wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_stb_o : out STD_LOGIC;
wb_cyc_o : out STD_LOGIC;
wb_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
......@@ -22,11 +22,11 @@ package wishbone_driver_pkg is
wb_ack_i : in STD_LOGIC;
wb_rty_i : in STD_LOGIC;
wb_err_i : in STD_LOGIC;
data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR(g_WB_DATA_I_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
write_i : in STD_LOGIC;
write_done_o : out STD_LOGIC;
read_i : in STD_LOGIC;
......
hdl/i2c_slave_wb_master/.gitignore 0 → 100644
View file @ 62b1c43a
#Ignore LaTeX trash
./doc/.*
./doc/.*.swo
./doc/.*.swp
./doc/Figures/*.eps
#Ignore autotrash from ISE
./project/
!/project/project.gise
!/project/project.xise
!/project/waveform/
#Ignore swap files at rtl/ and test/ folders
./rtl/.*.swo
./rtl/.*.swp
./test/.*.swo
./test/.*.swp
hdl/i2c_slave_wb_master/doc/Figures/I2C_drawings.svg
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hdl/i2c_slave_wb_master/doc/Figures/clk_fsm.svg 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/i2c_slave_wb_master/doc/i2cSpecs.pdf 100755 → 100644
View file @ 62b1c43a
No preview for this file type
hdl/i2c_slave_wb_master/doc/i2cSpecs.tex 100755 → 100644
View file @ 62b1c43a
......@@ -4,7 +4,7 @@
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{appendix}
\usepackage{tabularx}
%%\usepackage{draftwatermark}
%%\SetWatermarkLightness{0.9}
%%\SetWatermarkScale{5}
......@@ -81,6 +81,7 @@ Please see the CERN OHL variable.1.1 for applicable conditions.\\
\setcounter{tocdepth}{3}
\tableofcontents
\pagebreak
\listoftables
\listoffigures
\pagebreak
......@@ -106,14 +107,124 @@ The i2c module contains several blocks related the following way:\\
------------- i2c\_debouncer.vhd
The I2C slave functionalities are:
\section{Interrupting lines offered}
\subsection{pf\_wb\_addr\_o}
\begin{itemize}
\item Addresseable at both general or individual address.
\item Three independent fields (indirect wishbone address, write bytes into i2c
slave and read bytes from slave) can be configured to help integration.
\item A watchdog timer can be enable to increase reliability.
\end{itemize}
\begin{center}
\begin{tabularx}{\textwidth}{|X|}
\hline
It is recommended to take a look to the I2C standard before continue reading.\\
\hline
\end{tabularx}
\end{center}
\subsection{rd\_done\_o}
\pagebreak
\subsection{Intended use}
\textit{I2C Slave to Wishbone Master module} is intended to be used in both
\href{http://www.ohwr.org/projects/conv-ttl-blo/wiki}{CONV-TTL-BLO}
\footnote{\href{https://edms.cern.ch/nav/P:EDA-02446:V0/P:EDA-02446:V0/TAB3}{EDA-02446}} and \href{http://www.ohwr.org/projects/conv-ttl-rs485/wiki}{CONV-TTL-RS485}
\footnote{\href{https://edms.cern.ch/nav/P:EDA-02541:V0/P:EDA-02541:V0/TAB3}{EDA-02541}} projects to allow FPGA be remotely reprogrammed. Read and write operations have been specified as follows:
\subsubsection{I2C Master write into slave}
\begin{description}
\item[Start] The master will issue a start condition.
\item[Byte 1] The master will issue a write operation to a given I2C slave
address. Less significant bit is driven first into SDA line.
\item[Ack 1] An ack is expected from slave.
\item[Byte 2] The master will drive the SDA line with the upper-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 2] An ack is expected from slave.
\item[Byte 3] The master will drive the SDA line with the lower-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 3] An ack is expected from slave.
\item[Byte 4] The master will drive the SDA line with the highest byte to
be written at the given wishbone address. Most significant bit is driven
first into the SDA line.
\item[Ack 4] An ack is expected from slave.
\item[Byte 5] The master will drive the SDA line with the second highest
byte to be written at the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 5] An ack is expected from slave.
\item[Byte 6] The master will drive the SDA line with the second lowest
byte to be written at the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 6] An ack is expected from slave.
\item[Byte 7] The master will drive the SDA line with the second lowest
byte to be written at the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 7] An ack is expected from slave.
\end{description}
Refer to \hyperref[sec:appendixA]{appendix ~\ref{sec:appendixA}} for a
detailed waveform diagram.
\subsubsection{I2C Master read from slave}
\begin{description}
\item[Start] The master will issue a start condition.
\item[Byte 1] The master will issue a write operation to a given I2C slave
address. Less significant bit is driven first into SDA line.
\item[Ack 1] An ack is expected from slave.
\item[Byte 2] The master will drive the SDA line with the upper-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 2] An ack is expected from slave.
\item[Byte 3] The master will drive the SDA line with the lower-half part
of the wishbone addres to be read. Most significant bit is driven first
into the SDA line.
\item[Ack 3] An ack is expected from slave.
\item[Restart] The master will issue a (re)start condition.
\item[Byte 4] The master will issue a read operation to a given I2C slave
address. Less significant bit is driven first into SDA line.
\item[Byte 5] The slave will drive the SDA line with the highest byte to
be read from the given wishbone address. Most significant bit is driven
first into the SDA line.
\item[Ack 5] An nack is expected from master.
\item[Byte 6] The slave will drive the SDA line with the second highest
byte to be read from the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 6] An nack is expected from master.
\item[Byte 7] The slave will drive the SDA line with the second lowest
byte to be read from the given wishbone address. Most significant bit is
driven first into the SDA line.
\item[Ack 7] An nack is expected from master.
\item[Byte 8] The slave will drive the SDA line with the lowest byte to
be read from the given wishbone address. Most significant bit is driven
first into the SDA line.
\item[Ack 8] An nack is expected from master.
\item[Pause] The master will issue a pause condition.
\end{description}
Refer to \hyperref[sec:appendixB]{appendix ~\ref{sec:appendixB}} for a
detailed waveform diagram.
\subsection{Interrupting lines offered from top or core modules}
To increase functionality of the core, some interrupt lines are offered so the
IP core can be used together with a soft-core.
\subsubsection{pf\_wb\_addr\_o}
One-clock signal to request prefetch of the data specified by upon the
reception of the wishbone address in the i2c.
\subsubsection{rd\_done\_o}
The slave has finished to read the SDA line. Hence, this signal informs that a
\textbf{i2c master write operation into the slave} has completed.
\subsubsection{wr\_done\_o}
The slave has finished to write into the SDA line. Hence, this signal informs that a
\textbf{i2c master read operation from slave} has completed.
\subsection{wr\_done\_o}
\pagebreak
\section{Registers}
......@@ -127,28 +238,31 @@ connected to VME64x geographical address pins).\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c |}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
0 & I2C\_OP & I2C OPeration\\
0 & I2C\_OP & I2C OPeration & \textbf{'0'}\\
\hline
7-1 & I2C\_ADDR & I2C address\\
7-1 & I2C\_ADDR & I2C address & \textbf{See below}\\
\hline
11-8 & BIA & Bytes of Indirect Addressing\\
11-8 & BIA & Bytes of Indirect Addressing & \textbf{X"2"}\\
\hline
19-12 & BRD & Bytes to be ReaD from FPGA\\
19-12 & BRD & Bytes to be ReaD from FPGA & \textbf{X"4"}\\
\hline
27-20 & BWR & Bytes to be WRitten to FPGA\\
27-20 & BWR & Bytes to be WRitten to FPGA & \textbf{X"4"}\\
\hline
31-28 & x & Reserved\\
31-28 & x & Reserved & \textbf{X"0"}\\
\hline
\end{tabular}
\caption{\textit{CTR0} register}
\end{center}
\end{table}
The default value of I2C\_ADDR is \textbf{c\_I2C\_GENERAL\_ADDR}. It can be
found in \textit{i2c\_slave\_pkg.vhd}.
\subsection{LT}
\textit{LT} stands for Line Timing register. It is a \textbf{read-only} register.\\
......@@ -167,36 +281,38 @@ plus write/read bit).\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c |}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
7-0 & WBCP & WishBone Clock Period\\
7-0 & WBCP & WishBone Clock Period & \textbf{User dependant}\\
\hline
31-8 & SCLP & SCL Period\\
31-8 & SCLP & SCL Period & \textbf{X"000000"}\\
\hline
\end{tabular}
\caption{\textit{LT} register}
\end{center}
\end{table}
\pagebreak
\subsection{DTX}
The \textit{DTX} register is a \textbf{write-read} register.\\
It holds the data to be sent when a read request from the master is issued.
\footnote{Contents are left uninitialized to reduce IP size.}\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c |}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
31-0 & data & data to send\\
31-0 & data & data to send & \textbf{Not valid}\\
\hline
\end{tabular}
\caption{\textit{DTX} register}
\caption{\textit{DTX} register }
\end{center}
\end{table}
......@@ -208,12 +324,12 @@ It holds the last four received bytes through the I2C. LSB ordered.\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c |}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
31-0 & data & Data RX register\\
31-0 & data & Data RX register & \textbf{Not valid}\\
\hline
\end{tabular}
\caption{\textit{DRXA} register}
......@@ -227,12 +343,12 @@ It holds the second group of last four received bytes through I2C. LSB ordered.\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c |}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
31-0 & data & Data RX register\\
31-0 & data & Data RX register & \textbf{Not valid}\\
\hline
\end{tabular}
\caption{\textit{DRXB} register}
......@@ -268,28 +384,153 @@ The wishbone interface is addressed with 4-bit depth. Memory maps into:\\
\end{table}
\pagebreak
\section{Initilization}
\section{(Re)Initilization}
It takes place when:
\begin{itemize}
\item An external reset is issued.
\item The watchdog timer runs out.
\item An I2C transaction is finished.
\end{itemize}
Subsequently, \textit{CTR0}, which controls the behaviour of the IP core, (re)initializes to:
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Default}\\
\hline
\hline
0 & I2C\_OP & \textbf{'0'}\\
\hline
7-1 & I2C\_ADDR & \textbf{See below}\\
\hline
11-8 & BIA & \textbf{X"2"}\\
\hline
19-12 & BRD & \textbf{X"4"}\\
\hline
27-20 & BWR & \textbf{X"4"}\\
\hline
31-28 & x & \textbf{X"0"}\\
\hline
\end{tabular}
\caption{\textit{CTR0} register}
\end{center}
\end{table}
\textbf{I2C\_ADDR} is initialized to the value of the \textbf{i2c\_addr\_i} port in
\textit{i2c\_slave\_top}.\\
For a better understanding of the i2c finite state machine, please take a look to
the appendix.
\subsection{Watchdog timer}
A fixed-length watchdog timer has been included in the module.\\
The watchdog timer is able to reinitialize the module whenever a fixed deadline
is met. The value of this fixed deadline can be controlled \textit{before
synthesis} in i2c\_slave\_pkg.vhd.
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| l | l |}
\hline
\textbf{Constant} & \textbf{Meaning}\\
\hline
\hline
c\_WB\_CLK\_PERIOD & Wishbone clock period (ns)\\
\hline
c\_WATCHDOG\_DEADLINE & Deadline period (ns)\\
\hline
c\_WATCHDOG\_ENABLE & Watchdog enable\\
\hline
c\_WATCHDOG\_WIDTH & Bit length of watchdog counter\\
\hline
\end{tabular}
\caption{Watchdog constants}
\end{center}
\end{table}
\section{Modifiying length of the I2C fields}
This module was conceived to let the user easily modify the length of three
main fields.\\
Due to the integration into the project it was requiered for, the
selectable-length fields are:\\
\begin{table}[!htb]
\begin{center}
\begin{tabular}{| c | c |}
\hline
\textbf{I2C field} & \textbf{Select length}\\
\hline
\hline
Wishbone address & \textit{CTR0.\textbf{BIA}}\\
\hline
Data to read from slave & \textit{CTR0.\textbf{BRD}}\\
\hline
Data to write into slave & \textit{CTR0.\textbf{BWR}}\\
\hline
\end{tabular}
\caption{I2C multifield capability}
\end{center}
\end{table}
\pagebreak
\appendix
\section{I2C master write into slave}
\section{I2C master write into slave} \label{sec:appendixA}
In the following figure a I2C master write into a slave is shown. The
parameters of the transaction are:
A I2C master write into a slave is shown. \textit{CTR0} is configured as:
\begin{itemize}
\item \textbf{CTRO.I2C\_ADDR}: X"3"
\item \textbf{CTR0.I2C\_ADDR}: X"3"
\item \textbf{CTR0.BIA}: X"2"
\item \textbf{CTR0.BWR}: X"4"
\end{itemize}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=1.25,
\includegraphics[scale=1.1,
keepaspectratio]{./Figures/i2c_write.png}
\caption{I2C master write into slave}
\end{center}
\end{figure}
\pagebreak
\section{I2C master read from slave} \label{sec:appendixB}
A I2C master write into a slave is shown. \textit{CTR0} is configured as:
\begin{itemize}
\item \textbf{CTR0.I2C\_ADDR}: X"3"
\item \textbf{CTR0.BIA}: X"2"
\item \textbf{CTR0.BRD}: X"4"
\end{itemize}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=1.1,
keepaspectratio]{./Figures/i2c_read_slave.png}
\caption{I2C master read from slave}
\end{center}
\end{figure}
\section{i2c\_slave\_core Finite State Machine}
The finite state machine found in \textit{i2c\_slave\_core} is shown below.
Please note consistency with the colour schema in previous appendixes.
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.8,
keepaspectratio]{./Figures/i2c_SLA_fsm.png}
\caption{\textit{i2c\_slave\_core} fsm}
\end{center}
\end{figure}
\end{document}
hdl/i2c_slave_wb_master/project/modelsim/wave.do deleted 100755 → 0
View file @ a8566fda
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /i2c_slave_top_tb/wb_clk
add wave -noupdate /i2c_slave_top_tb/wb_rst_i
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_oen
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_o
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_i
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/scl_i
add wave -noupdate -group i2c_bit -height 16 /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/i2c_bit_fsm
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_sda_dGLITCH_d1
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_dGLITCH_d1
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_rising
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_falling
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/done
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_done_d1
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_done_d2
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/start_o
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/pause_o
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/rcved_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/pf_wb_addr_o
add wave -noupdate -group wishbone_MASTER -height 16 /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate -group wishbone_MASTER /i2c_slave_top_tb/uut/wb_master_cyc_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_stb_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_sel_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_we_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_data_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_data_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_addr_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_ack_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_rty_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_err_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_cyc_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_cyc_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_stb_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_sel_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_we_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_data_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_data_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_addr_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_ack_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_rty_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_err_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/PRE_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/CTR0_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/CTR1_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/STA_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX0_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX1_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX2_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX3_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX4_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX5_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX0_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX1_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX2_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX3_i
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_next
add wave -noupdate -height 16 /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_previous
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_previous_start
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_byte_cnt
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/Q
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/C
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/CLR
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/D
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rx_fifo_flush
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_i2c_addr
add wave -noupdate -radix binary /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rx_fifo_din
add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/clk_i
add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/rst_i
add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/en_i
add wave -noupdate -group {bit count} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/cnt_o
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/clk_i
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/rst_i
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/en_i
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/cnt_o
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_i
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/clk
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/push
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/flush
add wave -noupdate -group {rx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_o
add wave -noupdate -group {rx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_int
add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_i
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/clk
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/load
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/flush
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/oen_i
add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_o
add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_int
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/rd_done_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/wr_done_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rcved_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_tx_fifo_reg_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {471826715 ps} 0}
configure wave -namecolwidth 193
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {455785207 ps} {503379726 ps}
hdl/i2c_slave_wb_master/project/project.gise 0 → 100644
View file @ 62b1c43a
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="project.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="i2c_bit.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="i2c_bit.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="i2c_bit.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="i2c_bit.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="i2c_bit.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="i2c_bit.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="i2c_bit.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="i2c_bit.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="i2c_bit_summary.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="i2c_bit_tb.fdo"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="i2c_bit_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="i2c_slave_core.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="i2c_slave_core.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="i2c_slave_core.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="i2c_slave_core.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="i2c_slave_core.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="i2c_slave_core.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="i2c_slave_core.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="i2c_slave_core.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="i2c_slave_core_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="i2c_slave_core_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="i2c_slave_core_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="i2c_slave_top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="i2c_slave_top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="i2c_slave_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="i2c_slave_top.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="i2c_slave_top.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="i2c_slave_top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="i2c_slave_top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="i2c_slave_top.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="i2c_slave_top_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="i2c_slave_top_summary.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="i2c_slave_top_tb.fdo"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="i2c_slave_top_tb_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="i2c_slave_top_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="i2c_slave_top_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1351176457" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1351176457">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352677754" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1352677754">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_stack.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../test/i2c_bit_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../test/i2c_slave_top_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1352215597" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-9002096945947998699" xil_pn:start_ts="1352215597">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215597" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-4325641994361838445" xil_pn:start_ts="1352215597">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215574" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="5962221678014933934" xil_pn:start_ts="1352215574">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352677754" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1352677754">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_stack.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../test/i2c_bit_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../test/i2c_slave_top_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1352677756" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1352677754">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="i2c_slave_top_tb.fdo"/>
<outfile xil_pn:name="vsim.wlf"/>
<outfile xil_pn:name="work"/>
</transform>
<transform xil_pn:end_ts="1351176604" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1351176604">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215545" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-144096903103142421" xil_pn:start_ts="1352215545">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215545" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5962221678014933934" xil_pn:start_ts="1352215545">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215545" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1352215545">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215545" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3112228716704801965" xil_pn:start_ts="1352215545">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215545" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1352215545">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352215545" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="1380845560383869368" xil_pn:start_ts="1352215545">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352382626" xil_pn:in_ck="6441921431846390163" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8022121412301228921" xil_pn:start_ts="1352382619">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="i2c_bit.ngr"/>
<outfile xil_pn:name="i2c_slave_core.ngr"/>
<outfile xil_pn:name="i2c_slave_top.lso"/>
<outfile xil_pn:name="i2c_slave_top.ngc"/>
<outfile xil_pn:name="i2c_slave_top.ngr"/>
<outfile xil_pn:name="i2c_slave_top.prj"/>
<outfile xil_pn:name="i2c_slave_top.syr"/>
<outfile xil_pn:name="i2c_slave_top.xst"/>
<outfile xil_pn:name="i2c_slave_top_tb_beh.prj"/>
<outfile xil_pn:name="i2c_slave_top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
</transforms>
</generated_project>
hdl/i2c_slave_wb_master/project/waveform/i2c_slave_top_wv.wcfg 100755 → 100644
View file @ 62b1c43a
File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd 100755 → 100644
View file @ 62b1c43a
File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd 100755 → 100644
View file @ 62b1c43a
File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd 100755 → 100644
View file @ 62b1c43a
File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd 100755 → 100644
View file @ 62b1c43a
......@@ -557,7 +557,8 @@ begin
begin
if rising_edge(clk) then
if s_watchdog_cnt >= c_WATCHDOG_END_VALUE then
if rst_i = '1'
or s_watchdog_cnt >= c_WATCHDOG_END_VALUE then
i2c_SLA_fsm <= R0_RESET;
else
case i2c_SLA_fsm is
......@@ -673,6 +674,7 @@ begin
if s_bit_cnt = 7 then
i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK;
end if;
--! It can be removed, never reached
check_start_stop;
end if;
when S5W2A_WRITE_SDA_ACK =>
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd 100755 → 100644
View file @ 62b1c43a
File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/test/i2c_bit_tb.vhd 100755 → 100644
View file @ 62b1c43a
File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd 100755 → 100644
View file @ 62b1c43a
File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/test/log/i2c_master_driver.txt 0 → 100644
View file @ 62b1c43a
1 OK WRITE [ADDRESS|0]
1 OK WRITE WISHBONE HIGH
1 OK WRITE WISHBONE LOW
1 OK WRITE READ DATA 0
1 OK WRITE READ DATA 1
1 OK WRITE READ DATA 2
1 OK WRITE READ DATA 3
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
hdl/multiboot/project/multiboot.xise
View file @ 62b1c43a
......@@ -16,33 +16,41 @@
<files>
<file xil_pn:name="../rtl/multiboot_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../rtl/multiboot_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../test/multiboot_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../test/multiboot_core_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../test/multiboot_pkg_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
</files>
<properties>
......@@ -80,7 +88,7 @@
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -301,8 +309,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/multiboot_core_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.multiboot_core_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/multiboot_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.multiboot_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -325,7 +333,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.multiboot_core_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.multiboot_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......@@ -387,7 +395,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|multiboot_core_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|multiboot_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="multiboot" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
......
hdl/multiboot/project/wave.do deleted 100644 → 0
View file @ a8566fda
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /multiboot_core_tb/rst
add wave -noupdate -radix hexadecimal /multiboot_core_tb/clk
add wave -noupdate -radix hexadecimal /multiboot_core_tb/CTRL0_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/CTRL1_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/STAT_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL1_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL2_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL3_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL4_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL1_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL2_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL3_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL4_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/multiboot_fsm
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/readback_fsm
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_busy_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_o_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_ce_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_i_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_write_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/op_cycles
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1750000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {1057409 ps} {1887747 ps}
hdl/multiboot/project/waveform/wave.do 0 → 100644
View file @ 62b1c43a
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/addr_i
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/data_i
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/data_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/read_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/read_done_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/write_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/write_done_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_sel_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_stb_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_cyc_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_we_o
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/wb_addr_o
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/wb_data_i
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/wb_data_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_ack_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_err_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_rty_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_rst_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_clk
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_we_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_stb_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_cyc_i
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_sel_i
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_data_i
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_data_o
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_addr_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_ack_o
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_rty_o
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_err_o
add wave -noupdate -divider Registers
add wave -noupdate /multiboot_tb/wb_driver/wb_clk_i
add wave -noupdate /multiboot_tb/wb_driver/wb_rst_i
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_CTR0
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_CTR1
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_STAT
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_MBA
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_GBA
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_MBA_addr
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_GBA_addr
add wave -noupdate -radix hexadecimal -subitemconfig {/multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(15) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(14) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(13) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(12) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(11) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(10) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(9) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(8) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(7) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(6) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(5) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(4) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(3) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(2) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(1) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(0) {-radix hexadecimal}} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regB
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen1
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen2
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen3
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen4
add wave -noupdate -divider multiboot_core
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_ICAP_fsm
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_multiboot_fsm
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_readback_fsm
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_CTR0_core
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/MBA_ICAP_o
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/GBA_ICAP_o
add wave -noupdate -divider SignalSpy
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/CE
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/CLK
add wave -noupdate -expand -group ICAP -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/I
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/WRITE
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/BUSY
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/O
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1751210191 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {1750252160 ps} {1751578414 ps}
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