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Conv TTL Blocking
Commit 67acc6e6 authored by gilsoriano's avatar gilsoriano
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Modifications done to the test to allow compatibility with m25p32 test.

parent 3a931f62
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hdl/spi_master_multifield/project/waveform/wave.do
View file @ 67acc6e6
......@@ -2,17 +2,17 @@ onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /spi_master_core_tb/rst_i
add wave -noupdate /spi_master_core_tb/clk_i
add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_miso_i
add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_mosi_o
add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_clk_o
add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_cs_n_o
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_miso_i
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_mosi_o
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_cs_n_o
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_clk_o
add wave -noupdate -radix hexadecimal /spi_master_core_tb/inst_i
add wave -noupdate -radix hexadecimal /spi_master_core_tb/addr_i
add wave -noupdate -radix hexadecimal /spi_master_core_tb/data_i
add wave -noupdate -expand /spi_master_core_tb/uut/s_STATUS
add wave -noupdate -radix hexadecimal -expand -subitemconfig {/spi_master_core_tb/s_SPI0.CPOL {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI0.CPHA {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI0.BREAD {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI0.BDATA {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI0.BADDR {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI0.BINST {-height 17 -radix hexadecimal}} /spi_master_core_tb/s_SPI0
add wave -noupdate -expand -subitemconfig {/spi_master_core_tb/uut/s_SPI0_core.BREAD {-radix unsigned} /spi_master_core_tb/uut/s_SPI0_core.BDATA {-radix unsigned} /spi_master_core_tb/uut/s_SPI0_core.BADDR {-radix unsigned} /spi_master_core_tb/uut/s_SPI0_core.BINST {-radix unsigned}} /spi_master_core_tb/uut/s_SPI0_core
add wave -noupdate -radix hexadecimal -subitemconfig {/spi_master_core_tb/s_SPI1.PUSH_DATA {-radix hexadecimal} /spi_master_core_tb/s_SPI1.PUSH_ADDR {-radix hexadecimal} /spi_master_core_tb/s_SPI1.PUSH_INST {-radix hexadecimal} /spi_master_core_tb/s_SPI1.x {-radix hexadecimal} /spi_master_core_tb/s_SPI1.READ_MISO {-radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_DATA {-radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_ADDR {-radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_INST {-radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_OP {-radix hexadecimal} /spi_master_core_tb/s_SPI1.y {-radix hexadecimal} /spi_master_core_tb/s_SPI1.CLK_DIV {-radix hexadecimal} /spi_master_core_tb/s_SPI1.z {-radix hexadecimal}} /spi_master_core_tb/s_SPI1
add wave -noupdate /spi_master_core_tb/uut/s_STATUS
add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI0
add wave -noupdate /spi_master_core_tb/uut/s_SPI0_core
add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI1
add wave -noupdate /spi_master_core_tb/uut/s_SPI1_core
add wave -noupdate /spi_master_core_tb/uut/s_SPI1_core_d0
add wave -noupdate /spi_master_core_tb/uut/s_SPI2
......@@ -45,26 +45,26 @@ add wave -noupdate -group data_fifo -label s_SPI1.PUSH_DATA -radix hexadecimal /
add wave -noupdate -group data_fifo -label s_STATUS.PULL_DATA /spi_master_core_tb/uut/s_STATUS.PULL_DATA
add wave -noupdate -group data_fifo /spi_master_core_tb/uut/data_i
add wave -noupdate -group data_fifo /spi_master_core_tb/uut/s_data_reg_o
add wave -noupdate -group Testbench /spi_master_core_tb/s_rst_spi_analyser
add wave -noupdate -group Testbench /spi_master_core_tb/s_spi_count
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_inst_flag
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_addr_flag
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_data_flag
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/inst_check
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/addr_check
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/data_check
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_d0
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_n
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_n_d0
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_tmp
add wave -noupdate /spi_master_core_tb/uut/data_o
add wave -noupdate -expand -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/clk_i
add wave -noupdate -expand -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/rst_i
add wave -noupdate -expand -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/en_i
add wave -noupdate -expand -group {READ EDGE counter} -radix unsigned /spi_master_core_tb/uut/spi_read_edge_counter/cnt_o
add wave -noupdate -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/clk_i
add wave -noupdate -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/rst_i
add wave -noupdate -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/en_i
add wave -noupdate -group {READ EDGE counter} -radix unsigned /spi_master_core_tb/uut/spi_read_edge_counter/cnt_o
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_rst_spi_analyser
add wave -noupdate -expand -group Testbench /spi_master_core_tb/tester/s_spi_count
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/s_inst_check
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_inst_flag
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/s_addr_check
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_addr_flag
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/s_data_check
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_data_flag
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {365000 ps} 0}
WaveRestoreCursors {{Cursor 1} {1877079 ps} 0}
configure wave -namecolwidth 260
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -79,4 +79,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {5785936 ps} {8116530 ps}
WaveRestoreZoom {0 ps} {19409250 ps}
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @ 67acc6e6
......@@ -716,6 +716,9 @@ begin
spi_mosi_o <= s_data_reg_o(to_integer(unsigned(
not(s_read_edge_counter_cnt(2 downto 0)))));
when others =>
--! TODO: high impedance is just to see the proper switching in
--! blue in ModelSim. Change to 0
--spi_mosi_o <= '0';
spi_mosi_o <= 'Z';
end case;
end procedure;
......@@ -724,6 +727,9 @@ begin
if rising_edge(clk_i) then
if s_STATUS.clk_fsm = R0_RESET then
--! TODO: high impedance is just to see the proper switching in
--! blue in ModelSim. Change to 0
--spi_mosi_o <= '0';
spi_mosi_o <= 'Z';
else
......
hdl/spi_master_multifield/test/spi_analyser.vhd 0 → 100755
View file @ 67acc6e6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;
entity spi_analyser is
port( rst_i : in STD_LOGIC;
SPI0_i : in r_SPI0;
SPI1_i : in r_SPI1;
spi_mosi_o : in STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : in STD_LOGIC;
spi_cs_n_o : in STD_LOGIC;
inst_check_o : out STD_LOGIC_VECTOR (7 downto 0);
addr_check_o : out STD_LOGIC_VECTOR (23 downto 0);
data_check_o : out STD_LOGIC_VECTOR (2047 downto 0);
end_inst_flag_o : out STD_LOGIC;
end_addr_flag_o : out STD_LOGIC;
end_data_flag_o : out STD_LOGIC
);
end spi_analyser;
architecture behavior of spi_analyser is
signal s_spi_count : NATURAL := 0;
signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1;
signal s_spi_mosi : STD_LOGIC;
signal s_spi_clk : STD_LOGIC;
signal s_inst_check : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal s_addr_check : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal s_data_check : STD_LOGIC_VECTOR (2047 downto 0) := (others => '0');
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
signal s_end_data_flag : STD_LOGIC;
begin
s_SPI0 <= SPI0_i;
s_SPI1 <= SPI1_i;
s_spi_mosi <= spi_mosi_o;
s_spi_clk <= spi_clk_o;
inst_check_o <= s_inst_check;
addr_check_o <= s_addr_check;
data_check_o <= s_data_check;
end_inst_flag_o <= s_end_inst_flag;
end_addr_flag_o <= s_end_addr_flag;
end_data_flag_o <= s_end_data_flag;
p_spi_analyser: process(spi_clk_o, rst_i)
variable v_inst_length : NATURAL;
variable v_addr_length : NATURAL;
variable v_data_length : NATURAL;
procedure analyze_SPI_bit is
begin
--! This is the equivalent to the HW crop in spi_master_core
v_inst_length := f_min(to_integer(s_SPI0.BINST), c_INST_LENGTH)*8;
v_addr_length := f_min(to_integer(s_SPI0.BADDR), c_ADDR_LENGTH)*8;
v_data_length := f_min(to_integer(s_SPI0.BDATA), c_DATA_LENGTH)*8;
s_spi_count <= s_spi_count + 1;
s_end_inst_flag <= '0';
s_end_addr_flag <= '0';
s_end_data_flag <= '0';
if s_SPI1.SEND_INST = '1' then
if s_spi_count < v_inst_length then
s_inst_check(v_inst_length - 1 - s_spi_count) <= s_spi_mosi;
if s_spi_count = (v_inst_length - 1) then
if s_end_inst_flag = '0' then
s_end_inst_flag <= '1';
end if;
end if;
else
end if;
else
end if;
if s_SPI1.SEND_ADDR = '1' then
if s_SPI1.SEND_INST = '1' then
if s_spi_count >= (v_inst_length + v_addr_length) then
elsif s_spi_count >= v_inst_length
and s_spi_count < (v_inst_length + v_addr_length) then
s_addr_check(v_addr_length - 1 - (s_spi_count -
v_inst_length)) <= s_spi_mosi;
if s_spi_count = (v_inst_length + v_addr_length - 1) then
if s_end_addr_flag = '0' then
s_end_addr_flag <= '1';
end if;
end if;
else
end if;
else
if s_spi_count < v_addr_length then
s_addr_check(v_addr_length - 1 - s_spi_count) <= s_spi_mosi;
if s_spi_count = (v_addr_length - 1) then
if s_end_addr_flag = '0' then
s_end_addr_flag <= '1';
end if;
end if;
else
end if;
end if;
else
end if;
if s_SPI1.SEND_DATA = '1' then
if s_SPI1.SEND_INST = '1' then
if s_SPI1.SEND_ADDR = '1' then
if s_spi_count >= (v_inst_length + v_addr_length + v_data_length) then
elsif s_spi_count >= (v_inst_length + v_addr_length) then
s_data_check(v_data_length - 1 - (s_spi_count - v_inst_length
- v_addr_length)) <= s_spi_mosi;
if s_spi_count = (v_inst_length + v_addr_length + v_data_length - 1) then
if s_end_data_flag = '0' then
s_end_data_flag <= '1';
end if;
end if;
else
end if;
else
if s_spi_count >= (v_inst_length + v_data_length) then
elsif s_spi_count >= v_inst_length then
s_data_check(v_data_length - 1 - (s_spi_count -
v_inst_length)) <= s_spi_mosi;
if s_spi_count = (v_inst_length + v_data_length - 1) then
if s_end_data_flag = '0' then
s_end_data_flag <= '1';
end if;
end if;
else
end if;
end if;
else
if s_SPI1.SEND_ADDR = '1' then
if s_spi_count >= (v_addr_length + v_data_length) then
elsif s_spi_count >= v_addr_length then
s_data_check(v_data_length - 1 - (s_spi_count -
v_addr_length)) <= s_spi_mosi;
if s_spi_count = (v_addr_length + v_data_length - 1) then
if s_end_data_flag = '0' then
s_end_data_flag <= '1';
end if;
end if;
else
end if;
else
if s_spi_count = (v_data_length - 1) then
if s_end_data_flag = '0' then
s_end_data_flag <= '1';
end if;
end if;
s_data_check(s_spi_count) <= s_spi_mosi;
end if;
end if;
else
end if;
end procedure;
begin
if rst_i = '1' then
s_spi_count <= 0;
s_inst_check <= (others => '0') ;
s_addr_check <= (others => '0') ;
s_data_check <= (others => '0') ;
else
if rising_edge(spi_clk_o) then
--! Read cycle
if (s_SPI0.CPOL xor s_SPI0.CPHA) = '0' then
analyze_SPI_bit;
end if;
elsif falling_edge(spi_clk_o) then
--! Read cycle
if (s_SPI0.CPOL xor s_SPI0.CPHA) = '1' then
analyze_SPI_bit;
end if;
else
end if;
end if;
end process p_spi_analyser;
end;
hdl/spi_master_multifield/test/spi_analyser_pkg.vhd 0 → 100755
View file @ 67acc6e6
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