Small ug cleanup

6924ae51 · Theodor-Adrian Stana · d30bb5f9 · 6924ae51 · 6924ae51 · 6924ae51
Commit 6924ae51 authored Mar 11, 2013 by Theodor-Adrian Stana
6 changed files
--- a/doc/ug-conv-ttl-blo.pdf
+++ b/doc/ug-conv-ttl-blo.pdf
--- a/doc/ug/Figures/pulse-def.pdf
+++ b/doc/ug/Figures/pulse-def.pdf
--- a/doc/ug/Figures/pulse-def.svg
+++ b/doc/ug/Figures/pulse-def.svg
@@ -29,8 +29,8 @@
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@@ -91,7 +91,7 @@
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+       style="opacity:0.75000000000000000;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:1.5,1.5;stroke-dashoffset:0"
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@@ -110,7 +110,7 @@
         id="tspan6117"
         dy="0 0">1 μs</tspan></text>
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+       style="opacity:0.75000000000000000;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:1.5,1.5;stroke-dashoffset:0"
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--- a/doc/ug/build/ug-conv-ttl-blo.pdf
+++ b/doc/ug/build/ug-conv-ttl-blo.pdf
--- a/doc/ug/ug-conv-ttl-blo.pdf
+++ b/doc/ug/ug-conv-ttl-blo.pdf
--- a/doc/ug/ug-conv-ttl-blo.tex
+++ b/doc/ug/ug-conv-ttl-blo.tex
@@ -525,10 +525,10 @@ is used to light the pulse arrival LEDs on front an rear panels.

 \subsection{Reset generation}
 \label{sec:fpga-rst}
-The reset generator module (\textit{reset\_gen}) implemented inside the FPGA is responsible with generating
-a predefined-width reset signal when power is applied to the FPGA.

 \begin{table}[h]
+  \caption{\textit{reset\_gen} module generics and ports}
+  \label{tbl:fpga-rst-gen}
  \centerline
  {
    \begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
@@ -543,6 +543,9 @@ a predefined-width reset signal when power is applied to the FPGA.
  }
 \end{table}

+The reset generator module (\textit{reset\_gen}) implemented inside the FPGA is responsible with generating
+a predefined-width reset signal when power is applied to the FPGA.
+
 When a power-on reset occurs on the Xilinx FPGA, a counter inside the \textit{reset\_gen} module starts 
 counting up. While this counter is counting up, the active-low reset signal is kept low, resetting 
 synchronous logic inside the FPGA. When the counter reaches the value of the reset width (specified via the
@@ -557,13 +560,10 @@ By default, the reset time is set to 96~ms.

 \subsection{RTM detection}
 \label{sec:fpga-rtm-det}
-A simple RTM detection mechanism is employed on CONV-TTL-BLO boards. Three lines on the VME P2 connector are dedicated
-for RTMM detection, and three lines for RTMP detection. On the CONV-TTL-BLO side, these lines are pulled up to VCC with
-pull-up resistors. Thus, when no RTMM is plugged in, all six lines (RTMM and RTMP) are logic high due to the pull-up.
-When an RTM is plugged in, the lines corresponding to the RTMM/P is connected to ground and a logic low will be detected
-at the FPGA input.

 \begin{table}[h]
+  \caption{\textit{rtm\_detector} module generics and ports}
+  \label{tbl:fpga-rtm-detector}
  \centerline
  {
    \begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
@@ -579,6 +579,12 @@ at the FPGA input.
  }
 \end{table}

+A simple RTM detection mechanism is employed on CONV-TTL-BLO boards. Three lines on the VME P2 connector are dedicated
+for RTMM detection, and three lines for RTMP detection. On the CONV-TTL-BLO side, these lines are pulled up to VCC with
+pull-up resistors. Thus, when no RTMM is plugged in, all six lines (RTMM and RTMP) are logic high due to the pull-up.
+When an RTM is plugged in, the lines corresponding to the RTMM/P is connected to ground and a logic low will be detected
+at the FPGA input.
+
 The \textit{rtm\_detector} module simply sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the \textit{rtmm\_i} and
 \textit{rtmp\_i} input signals are respectively all-ones.

@@ -589,13 +595,9 @@ outputs are low.
 \subsection{Pulse generation}
 \label{sec:fpga-pulse-gen}

-The \textit{pulse\_generator} module is used to generate pulses of predefined width based on a trigger input.
-To avoid glitches on the input, the trigger input is taken through a variable-length glitch filter (set by
-the user at synthesis time via the \textit{g\_glitch\_filt\_len} generic). The glitch filter consists of a 
-series of flip-flops that, when all high, trigger the generation of a variable-width pulse at the output. 
-The width of the pulse is set via the \textit{g\_pulse\_width} generic.
-
 \begin{table}[h]
+  \caption{\textit{pulse\_generator} module generics and ports}
+  \label{tbl:fpga-pulse-generator}
  \centerline
  {
    \begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
@@ -615,6 +617,12 @@ The width of the pulse is set via the \textit{g\_pulse\_width} generic.
  }
 \end{table}

+The \textit{pulse\_generator} module is used to generate pulses of predefined width based on a trigger input.
+To avoid glitches on the input, the trigger input is taken through a variable-length glitch filter (set by
+the user at synthesis time via the \textit{g\_glitch\_filt\_len} generic). The glitch filter consists of a 
+series of flip-flops that, when all high, trigger the generation of a variable-width pulse at the output. 
+The width of the pulse is set via the \textit{g\_pulse\_width} generic.
+
 Assuming active-high triggers arrive at the \textit{pulse\_generator} module trigger input, high-level active pulses
 are generated at the pulse output of the module (Fig.~\ref{fig:pulse-gen-sigs}). In order to avoid output jitter, 
 the pulse output is selected between the trigger input and the internally-generated pulse signal. The latter
@@ -645,7 +653,7 @@ Finally, six \textit{pulse\_generator} modules are configured to output 96~ms pu
 blocking and TTL channels; they are sensitive to the same trigger input as the TTL and blocking pulse generators.

 All pulse generator modules instantiated in the design have glitch filters with length four, thus the input trigger pulse
-has to have a width of at least 32~ns, considering the 125~MHz clock input.
+should have a width of at least 32~ns, considering the 125~MHz clock input.

 %======================================================================================
 % SEC: Internal regs