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Conv TTL Blocking
Commit 6c8c04da authored by gilsoriano's avatar gilsoriano
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The core works for SR writes. Synchronization between double buffer and SPI core has been achieved. 

Known issues to resolved:
- Implement FMOH bits: CLBR, FS, PG, SECT
- Implement SPI1 CLK_DIV bit
- Implement read operation in SPI module
- Implement CTR1 bits: BOV, CBSF
- Implement Write Page Operation in m25p32

This core starts to get ready.
parent 43aca69f
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Showing with 263 additions and 174 deletions
hdl/m25p32/rtl/m25p32_buff.vhd
View file @ 6c8c04da
......@@ -51,6 +51,11 @@ end m25p32_buff;
architecture Behavioral of m25p32_buff is
type data_db is array (0 to c_NUMBER_OF_BUFFERS - 1) of
STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0);
signal s_data_db : data_db;
signal s_CTR1 : r_CTR1;
signal s_DBUF : r_DBUF;
......@@ -67,6 +72,10 @@ begin
DBUF_o(23 downto 0) <= f_STD_LOGIC_VECTOR(s_DBUF(0));
DBUF_o(47 downto 24) <= f_STD_LOGIC_VECTOR(s_DBUF(1));
data_db_assign: for I in 0 to (c_NUMBER_OF_BUFFERS - 1) generate
data_db_o( (I+1)*8*g_data_width - 1 downto I*8*g_data_width)
<= s_data_db(I);
end generate data_db_assign;
inst_push: for I in 0 to (c_NUMBER_OF_BUFFERS - 1) generate
s_push_inst(I) <= s_CTR1.ARBF(I + s_CTR1.ARBF'low) and s_CTR1.PUSH_I;
......@@ -118,17 +127,21 @@ begin
clk => clk,
push => s_push_data(I),
flush => rst_i,
reg_o => data_db_o(8*g_data_width*(I+1) - 1 downto
8*g_data_width*I)
reg_o => s_data_db(I)
-- reg_o => data_db_o(8*g_data_width*(I+1) - 1 downto
-- 8*g_data_width*I)
);
end generate INST_DATA;
-- p_write_buffer: process(clk)
-- begin
-- if rising_edge (clk) then
-- if rst_i = '1' then
-- s_DBUF(0) <= c_BUF_default;
-- s_DBUF(1) <= c_BUF_default;
--! @brief Process to keep track of the page and sector of each double
--! buffer
p_write_buffer: process(clk)
begin
if rising_edge (clk) then
if rst_i = '1' then
s_DBUF(0) <= c_BUF_default;
s_DBUF(1) <= c_BUF_default;
-- s_push <= (others => '0');
-- s_pull <= (others => '0');
-- elsif s_CTR1.WRA = '1' then
......@@ -144,10 +157,9 @@ begin
-- s_DBUF(1).SECT <= unsigned(addr_i(23 downto 16));
-- when others =>
-- end case;
-- else
-- end if;
-- else
-- end if;
-- end process;
else
end if;
end if;
end process;
end Behavioral;
hdl/m25p32/rtl/m25p32_core.vhd
View file @ 6c8c04da
......@@ -31,20 +31,27 @@ entity m25p32_core is
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
inst_db_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
inst_db_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_i : in STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
inst_core_o : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
push_i_core_o : out STD_LOGIC;
push_a_core_o : out STD_LOGIC;
push_d_core_o : out STD_LOGIC;
bov_core_o : out STD_LOGIC;
CTR0_o : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_i : in STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
);
end m25p32_core;
......@@ -56,7 +63,6 @@ signal MEM_fsm_d0 : t_m25p32_fsm;
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_CTR1_slv : STD_LOGIC_VECTOR (r_CTR1'a_length - 1 downto 0);
signal s_FMOH : r_FMOH;
--! Registers from spi_master_pkg
......@@ -74,8 +80,6 @@ signal s_addr_m25p32_regs : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
signal s_data_m25p32_regs : STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
signal s_inst_m25p32_core : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
signal s_addr_m25p32_core : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
signal s_data_m25p32_core : STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
signal s_inst_spi : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
signal s_addr_spi : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
......@@ -84,13 +88,16 @@ signal s_data_spi : STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
begin
CTR0_o <= f_STD_LOGIC_VECTOR(s_CTR0);
s_CTR1 <= f_CTR1(s_CTR1_slv);
CTR0_o <= f_STD_LOGIC_VECTOR(s_CTR0);
push_i_core_o <= s_CTR1.PUSH_I;
push_a_core_o <= s_CTR1.PUSH_A;
push_d_core_o <= s_CTR1.PUSH_D;
bov_core_o <= s_CTR1.BOV;
s_FMOH <= f_FMOH(FMOH_i);
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv);
s_FMOH <= f_FMOH(FMOH_i);
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv);
s_inst_m25p32_regs <= inst_db_i;
s_addr_m25p32_regs <= addr_db_i;
......@@ -125,32 +132,72 @@ begin
s_inst_spi <= s_inst_m25p32_regs when s_CTR1.BOV = '0'
else s_inst_m25p32_core;
s_addr_spi <= s_addr_m25p32_regs when s_CTR1.BOV = '0'
else s_addr_m25p32_core;
s_addr_spi <= s_addr_m25p32_regs;
--! TODO: Reorder bytes depending on the length of the instruction
s_data_spi (8*(g_DATA_LENGTH - 1) - 1 downto 0)
<= (others => '0') when s_FMOH.OP = WRSR
else s_data_m25p32_regs (8*(g_DATA_LENGTH - 1) - 1 downto 0);
s_data_spi <= s_data_m25p32_regs when s_CTR1.BOV = '0'
else s_data_m25p32_core;
s_data_spi (8*g_DATA_LENGTH - 1 downto 8*(g_DATA_LENGTH - 1))
<= s_data_m25p32_regs (7 downto 0) when s_FMOH.OP = WRSR
else s_data_m25p32_regs (8*g_DATA_LENGTH - 1 downto
8*(g_DATA_LENGTH - 1));
--! @brief This is the combinational process that sets up the correct
--! instruction field from m25p32_core.
p_inst_m25p32_core: process(s_CTR1.BOV)
--! instruction field from m25p32_core.
--! This instruction fields are only set for immediate bypassing
--! in WREN and WRDI instructions (beginning and end of frame).
p_inst_m25p32_core: process(s_CTR1.BOV, MEM_fsm)
begin
case MEM_fsm is
when S1_WREN =>
s_inst_m25p32_core <= c_WREN_inst;
when S4_WRDI =>
s_inst_m25p32_core <= c_WRDI_inst;
when others =>
s_inst_m25p32_core <= (others => '0');
if s_CTR1.BOV = '1' then
case MEM_fsm is
when S1_WREN =>
s_inst_m25p32_core <= c_WREN_inst;
when S4_WRDI =>
s_inst_m25p32_core <= c_WRDI_inst;
when others =>
s_inst_m25p32_core <= (others => '0');
end case;
end if;
end process;
--! @brief This is the combinational process that sets up the correct
--! instruction field from m25p32_core to be loaded into the
--! double buffers in m25p32_regs.
p_inst_m25p32_regs_i : process(s_FMOH.OP)
begin
case s_FMOH.OP is
when ERS =>
inst_core_o <= c_SE_inst;
when RDP =>
inst_core_o <= c_READ_inst;
when WRP =>
inst_core_o <= c_PP_inst;
when RDSR =>
inst_core_o <= c_RDSR_inst;
when WRSR =>
inst_core_o <= c_WRSR_inst;
when others =>
inst_core_o <= (others => '0');
end case;
end process;
--! @brief Main clocked process that rules the fsm.
--! In this process the SPI device is HW controlled via the values
--! of the registers in m25p32_regs.
--! From the wishbone side, when we have already loaded all the data
--! we want to send (in case we want to transfer some data), a write
--! in FMOH register is requiered to kick out the m25p32 operation.
p_out: process (wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
s_CTR0 <= c_CTR0_default;
s_CTR1 <= c_CTR1_default;
s_SPI0 <= c_SPI0_default;
s_SPI1 <= c_SPI1_default;
else
......@@ -175,13 +222,6 @@ begin
else
end if;
-- --! Code added to remove the glitch at the end of WRDI instruction
-- if ( s_SPI2.SENT_OP'event
-- and s_SPI2.SENT_OP = '1'
-- and MEM_fsm = S4_WRDI ) then
-- s_SPI1 <= c_SPI1_default;
-- end if;
end process;
end Behavioral;
hdl/m25p32/rtl/m25p32_core_pkg.vhd
View file @ 6c8c04da
......@@ -136,7 +136,7 @@ package m25p32_core_pkg is
BADDR => (others => '0'),
BINST => to_unsigned( 1 , 9));
constant c_SPI1_WRSR : r_SPI1 := (PUSH_DATA => '0', PUSH_ADDR => '0',
constant c_SPI1_WRSR : r_SPI1 := (PUSH_DATA => '1', PUSH_ADDR => '0',
PUSH_INST => '1', x => (others => '0'),
SEND_DATA => '1',
SEND_ADDR => '0',
......@@ -249,22 +249,19 @@ package body m25p32_core_pkg is
MEM_fsm <= S1_WREN;
s_SPI0 <= c_SPI0_WREN;
s_SPI1 <= c_SPI1_WREN;
else
--! We push directly the instruction from m25p32_core
s_CTR1.BOV <= '1';
else
s_CTR0 <= c_CTR0_default;
s_SPI0 <= c_SPI0_default;
s_SPI1 <= c_SPI1_default;
end if;
when S1_WREN =>
if MEM_fsm_d0 /= MEM_fsm then
s_SPI0 <= c_SPI0_WREN;
s_SPI1 <= c_SPI1_WREN;
--! We push directly the instruction from m25p32_core
s_CTR1.BOV <= '1';
s_SPI1.PUSH_INST <= '1';
elsif s_SPI2.SENT_OP = '1' then
if s_SPI2.SENT_OP = '1' then
MEM_fsm <= S2A_SPI_OP_LD_DBUF;
s_SPI0 <= c_SPI0_WRSR;
s_SPI1 <= c_SPI1_WRSR;
s_CTR1.PUSH_I <= c_SPI1_WRSR.PUSH_INST;
s_CTR1.PUSH_A <= c_SPI1_WRSR.PUSH_ADDR;
s_CTR1.PUSH_D <= c_SPI1_WRSR.PUSH_DATA;
end if;
when S2A_SPI_OP_LD_DBUF =>
--! As it only takes only cycle to load the buffer, we just
......@@ -272,25 +269,18 @@ package body m25p32_core_pkg is
MEM_fsm <= S2B_SPI_OP_LD_SPIBUF;
--! We push the contents into the double buffer by writing
--! into s_CTR1 register.
s_CTR1.PUSH_I <= c_SPI1_WRSR.PUSH_INST;
s_CTR1.PUSH_A <= c_SPI1_WRSR.PUSH_ADDR;
s_CTR1.PUSH_D <= c_SPI1_WRSR.PUSH_DATA;
s_SPI0 <= c_SPI0_WRSR;
s_SPI1 <= c_SPI1_WRSR;
when S2B_SPI_OP_LD_SPIBUF =>
if MEM_fsm_d0 /= MEM_fsm then
s_SPI1.PUSH_INST <= c_SPI1_WRSR.PUSH_INST;
s_SPI1.PUSH_ADDR <= c_SPI1_WRSR.PUSH_ADDR;
s_SPI1.PUSH_DATA <= c_SPI1_WRSR.PUSH_DATA;
elsif s_SPI2.SENT_OP = '1' then
if s_SPI2.SENT_OP = '1' then
MEM_fsm <= S4_WRDI;
end if;
when S4_WRDI =>
if MEM_fsm_d0 /= MEM_fsm then
s_SPI0 <= c_SPI0_WRDI;
s_SPI1 <= c_SPI1_WRDI;
--! We push directly the instruction from m25p32_core
s_CTR1.BOV <= '1';
s_SPI1.PUSH_INST <= '1';
elsif s_SPI2.SENT_OP = '1' then
end if;
when S4_WRDI =>
if s_SPI2.SENT_OP = '1' then
MEM_fsm <= S0_IDLE;
s_SPI1 <= c_SPI1_IDLE;
s_CTR0.OPF <= '1';
......
hdl/m25p32/rtl/m25p32_regs.vhd
View file @ 6c8c04da
......@@ -32,26 +32,33 @@ entity m25p32_regs is
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_db_o : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_o : out STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_o : out STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_core_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
inst_db_o : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_o : out STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_o : out STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
push_i_core_i : in STD_LOGIC;
push_a_core_i : in STD_LOGIC;
push_d_core_i : in STD_LOGIC;
bov_core_i : in STD_LOGIC;
CTR0_i : in STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
);
end m25p32_regs;
......@@ -59,13 +66,13 @@ architecture Behavioral of m25p32_regs is
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_CTR1_slv : STD_LOGIC_VECTOR (r_CTR1'a_length - 1 downto 0);
signal s_CTR1_buff : r_CTR1;
signal s_CTR1_buff_slv : STD_LOGIC_VECTOR (r_CTR1'a_length - 1 downto 0);
signal s_FMOH : r_FMOH;
signal s_SR_m25p32 : r_SR_m25p32;
signal s_DBUF : r_DBUF;
signal s_DBUF_slv : STD_LOGIC_VECTOR (r_DBUF'a_length - 1 downto 0);
signal s_inst_i : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
signal s_addr_i : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
signal s_data_i : STD_LOGIC_VECTOR (31 downto 0);
......@@ -86,8 +93,13 @@ begin
wb_rty_o <= s_wb_rty_o;
wb_err_o <= s_wb_err_o;
s_CTR0 <= f_CTR0(CTR0_i);
s_CTR1_slv <= f_STD_LOGIC_VECTOR(s_CTR1);
s_CTR0 <= f_CTR0(CTR0_i);
s_CTR1_buff.PUSH_I <= s_CTR1.PUSH_I or push_i_core_i;
s_CTR1_buff.PUSH_A <= s_CTR1.PUSH_A or push_a_core_i;
s_CTR1_buff.PUSH_D <= s_CTR1.PUSH_D or push_d_core_i;
s_CTR1_buff.BOV <= s_CTR1.BOV or bov_core_i;
s_CTR1_buff_slv <= f_STD_LOGIC_VECTOR(s_CTR1);
FMOH_o <= f_STD_LOGIC_VECTOR(s_FMOH);
s_DBUF(0) <= f_BUF(s_DBUF_slv( r_BUF'a_length - 1 downto 0));
s_DBUF(1) <= f_BUF(s_DBUF_slv(2*r_BUF'a_length - 1 downto
......@@ -124,7 +136,7 @@ begin
rst_i => wb_rst_i,
clk => wb_clk,
inst_i => s_inst_i,
inst_i => inst_core_i,
addr_i => s_addr_i,
data_i => s_data_i,
......@@ -132,7 +144,7 @@ begin
addr_db_o => s_addr_db_o,
data_db_o => s_data_db_o,
CTR1_i => s_CTR1_slv,
CTR1_i => s_CTR1_buff_slv,
DBUF_o => s_DBUF_slv
);
......@@ -150,7 +162,6 @@ begin
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
s_inst_i <= (others => '0');
s_addr_i <= (others => '0');
s_data_i <= (others => '0');
else
......@@ -240,6 +251,8 @@ begin
r_SR_m25p32'a_length-1 downto 0));
s_data_i (r_SR_m25p32'a_length-1 downto 0)
<= wb_data_i(r_SR_m25p32'a_length-1 downto 0);
s_data_i (31 downto r_SR_m25p32'a_length)
<= (others => '0');
s_CTR1.PUSH_D <= '1';
when others =>
s_wb_ack_o <= '0';
......@@ -255,7 +268,7 @@ begin
<= (others => '0');
when c_CTR1_addr =>
wb_data_o(r_CTR1'a_length - 1 downto 0)
<= s_CTR1_slv;
<= s_CTR1_buff_slv;
wb_data_o(31 downto r_CTR1'a_length)
<= (others => '0');
when c_FMOH_addr =>
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ 6c8c04da
......@@ -48,32 +48,44 @@ end m25p32_top;
architecture Behavioral of m25p32_top is
signal s_CTR0 : STD_LOGIC_VECTOR ( r_CTR0'a_length - 1 downto 0);
signal s_FMOH : STD_LOGIC_VECTOR ( r_FMOH'a_length - 1 downto 0);
signal s_DBUF : STD_LOGIC_VECTOR ( r_DBUF'a_length - 1 downto 0);
signal s_inst_db : STD_LOGIC_VECTOR ( 8*c_INST_LENGTH - 1 downto 0);
signal s_addr_db : STD_LOGIC_VECTOR ( 8*c_ADDR_LENGTH - 1 downto 0);
signal s_data_db : STD_LOGIC_VECTOR ( 8*c_DATA_LENGTH - 1 downto 0);
signal s_CTR0 : STD_LOGIC_VECTOR ( r_CTR0'a_length - 1 downto 0);
signal s_FMOH : STD_LOGIC_VECTOR ( r_FMOH'a_length - 1 downto 0);
signal s_DBUF : STD_LOGIC_VECTOR ( r_DBUF'a_length - 1 downto 0);
signal s_inst_db : STD_LOGIC_VECTOR ( 8*c_INST_LENGTH - 1 downto 0);
signal s_addr_db : STD_LOGIC_VECTOR ( 8*c_ADDR_LENGTH - 1 downto 0);
signal s_data_db : STD_LOGIC_VECTOR ( 8*c_DATA_LENGTH - 1 downto 0);
-- type t_operations is (x, ERS, RDP, WRP, RDSR, WRSR);
signal s_inst_core : STD_LOGIC_VECTOR ( 8*c_INST_LENGTH - 1 downto 0);
signal s_push_i_core : STD_LOGIC;
signal s_push_a_core : STD_LOGIC;
signal s_push_d_core : STD_LOGIC;
signal s_bov_core : STD_LOGIC;
component m25p32_core is
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
inst_db_i : in STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_db_i : in STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_db_i : in STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
inst_core_o : out STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
inst_db_i : in STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_db_i : in STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_db_i : in STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
push_i_core_o : out STD_LOGIC;
push_a_core_o : out STD_LOGIC;
push_d_core_o : out STD_LOGIC;
bov_core_o : out STD_LOGIC;
CTR0_o : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_i : in STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
CTR0_o : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_i : in STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
);
end component;
......@@ -83,26 +95,34 @@ architecture Behavioral of m25p32_top is
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_db_o : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_o : out STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_o : out STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_core_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
inst_db_o : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_o : out STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_o : out STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
push_i_core_i : in STD_LOGIC;
push_a_core_i : in STD_LOGIC;
push_d_core_i : in STD_LOGIC;
bov_core_i : in STD_LOGIC;
CTR0_i : in STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
);
end component;
......@@ -110,44 +130,58 @@ begin
inst_m25p32_core: m25p32_core
port map (
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
mosi_o => prom_mosi_o,
miso_i => prom_din_i,
sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o,
inst_db_i => s_inst_db,
addr_db_i => s_addr_db,
data_db_i => s_data_db,
mosi_o => prom_mosi_o,
miso_i => prom_din_i,
sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o,
inst_core_o => s_inst_core,
inst_db_i => s_inst_db,
addr_db_i => s_addr_db,
data_db_i => s_data_db,
push_i_core_o => s_push_i_core,
push_a_core_o => s_push_a_core,
push_d_core_o => s_push_d_core,
bov_core_o => s_bov_core,
CTR0_o => s_CTR0,
FMOH_i => s_FMOH
CTR0_o => s_CTR0,
FMOH_i => s_FMOH
);
inst_m25p32_regs: m25p32_regs
port map (
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
inst_db_o => s_inst_db,
addr_db_o => s_addr_db,
data_db_o => s_data_db,
CTR0_i => s_CTR0,
FMOH_o => s_FMOH
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
inst_core_i => s_inst_core,
inst_db_o => s_inst_db,
addr_db_o => s_addr_db,
data_db_o => s_data_db,
push_i_core_i => s_push_i_core,
push_a_core_i => s_push_a_core,
push_d_core_i => s_push_d_core,
bov_core_i => s_bov_core,
CTR0_i => s_CTR0,
FMOH_o => s_FMOH
);
end Behavioral;
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