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Conv TTL Blocking
Commit 7ee393fc authored by gilsoriano's avatar gilsoriano
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New trigger for edge detection and level contention. Debugging phase.

parent 4bcd1c14
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Showing with 1290 additions and 906 deletions
hdl/ctdah_lib/rtl/ctdah_pkg.vhd
View file @ 7ee393fc
......@@ -13,28 +13,40 @@ use IEEE.STD_LOGIC_1164.all;
package ctdah_pkg is
component gc_clk_divider is
generic( g_clk_division_logSize : NATURAL := 8);
generic( g_CLK_DIVISION_LOGSIZE : NATURAL := 8);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
oe_n_i : in STD_LOGIC;
clk_o : out STD_LOGIC;
divider_i : in STD_LOGIC_VECTOR (g_clk_division_logSize - 1 downto 0) --Divides by twice the value specified
divider_i : in STD_LOGIC_VECTOR (g_CLK_DIVISION_LOGSIZE - 1 downto 0) --Divides by twice the value specified
);
end component;
component gc_counter is
generic(
g_data_width: NATURAL
);
port (
g_DATA_WIDTH : NATURAL);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_data_width-1 downto 0)
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end component;
component gc_debouncer is
generic (
g_LENGTH : INTEGER := 6);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH-1 downto 0)
);
end component;
component gc_ff is
port(
Q : out STD_LOGIC;
......@@ -43,46 +55,68 @@ package ctdah_pkg is
D : in STD_LOGIC
);
end component;
component gc_monostable is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pulse_len : in STD_LOGIC_VECTOR(31 downto 0);
write_tt_o : out STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end component;
component gc_RAM is
generic(g_DATA_WIDTH : INTEGER := 32;
g_ADDR_WIDTH : INTEGER := 8);
port(clka : in STD_LOGIC;
wea : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
dina : in STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
doutb : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0));
end component;
component FIFO_dispatcher is
generic(
g_data_width : NATURAL := 8;
g_dispatcher_depth : NATURAL := 4
);
g_DATA_WIDTH : NATURAL := 8;
g_DISPATCHER_DEPTH : NATURAL := 4);
port (
reg_i : in STD_LOGIC_VECTOR (g_dispatcher_depth*g_data_width-1 downto 0);
reg_i : in STD_LOGIC_VECTOR (g_DISPATCHER_DEPTH*g_DATA_WIDTH - 1 downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
flush : in STD_LOGIC;
oen_i : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
reg_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end component;
component FIFO_stack is
generic(
g_data_width : NATURAL := 8;
g_stack_depth : NATURAL := 8
g_DATA_WIDTH : NATURAL := 8;
g_STACK_DEPTH : NATURAL := 8
);
port (
reg_i : in STD_LOGIC_VECTOR (g_data_width-1 downto 0);
reg_i : in STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
clk : in STD_LOGIC;
push : in STD_LOGIC;
flush : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_stack_depth*g_data_width - 1 downto 0)
reg_o : out STD_LOGIC_VECTOR (g_STACK_DEPTH*g_DATA_WIDTH - 1 downto 0)
);
end component;
component FIFO_simple is
generic(
g_data_width : NATURAL := 8
g_DATA_WIDTH : NATURAL := 8
);
port (
reg_i : in STD_LOGIC_VECTOR (g_data_width-1 downto 0);
reg_i : in STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
clk : in STD_LOGIC;
push : in STD_LOGIC;
flush : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
reg_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end component;
......
hdl/ctdah_lib/rtl/gc_counter.vhd
View file @ 7ee393fc
......@@ -42,13 +42,13 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_counter is
generic(
g_data_width: NATURAL
g_DATA_WIDTH: NATURAL
);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_data_width-1 downto 0)
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end gc_counter;
......@@ -59,7 +59,7 @@ begin
main_proc: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_data_width-1 downto 0);
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0);
begin
......
hdl/trigger/project/project.xise 0 → 100755
View file @ 7ee393fc
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../rtl/trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../rtl/trigger_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../rtl/trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../rtl/TT_RAMhandler.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../test/trigger_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_RAM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="simulation/custom.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|trigger_top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/trigger_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/trigger_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="trigger" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="trigger_map.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="trigger_timesim.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="trigger_synthesis.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="trigger_translate.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="This is the project for testing the trigger module" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="trigger_top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/trigger_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.trigger_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="10000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.trigger_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|trigger_top_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="project" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-12-01T12:12:38" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="554F90F7EA50CCF65AF5E6E3DA16BE82" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/trigger/rtl/debouncer.vhd deleted 100755 → 0
View file @ 4bcd1c14
----------------------------------------------------------------------------------
-- Company: CERN
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:26:32 10/07/2011
-- Design Name: Basic debouncer
-- Module Name: debouncer - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debouncer is
generic (
g_LENGTH : INTEGER := 6
);
port (
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : IN std_logic_vector(g_LENGTH-1 downto 0)
);
end debouncer;
architecture Behavioral of debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
component gc_ff
port (
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
begin
ff1: gc_ff
port map(
Q => meta_ff1,
C => clk,
CLR => rst,
D => input
);
ff2: gc_ff
port map(
Q => delay_s(0),
C => clk,
CLR => rst,
D => meta_ff1
);
-- Metastability solved here
delay_line: for i in 1 to g_LENGTH-1 generate
D_Flip_Flop : gc_ff
port map (
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output <= '0';
else
if ( (delay_s and glitch_mask) = glitch_mask) then
output <= '1';
else
output <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
hdl/trigger/rtl/gc_RAM.vhd deleted 100755 → 0
View file @ 4bcd1c14
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gc_RAM is
generic(
g_DATA_WIDTH : INTEGER := 32;
g_ADDR_WIDTH : INTEGER := 8;
g_ADDR_SIZE : INTEGER := 256
);
port(
clka : in STD_LOGIC;
wea : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
dina : in STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
doutb : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
);
end gc_RAM;
architecture Behavioural of gc_RAM is
type ram_type is array(g_ADDR_SIZE - 1 downto 0) of STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
signal RAM: ram_type;
begin
write_proc: process (clka)
begin
if rising_edge(clka) then
if rstb = '1' then
erase_loop: for i in 0 to g_ADDR_SIZE - 1 loop
RAM(i) <= (others => '0');
end loop erase_loop;
else
RAM(conv_integer(addra)) <= dina;
end if;
else
end if;
end process;
read_proc: process (clkb)
begin
if rising_edge(clkb) then
if rstb = '1' then
doutb <= (others => '0');
elsif addrb = addra then
doutb <= dina;
else
doutb <= RAM(conv_integer(addrb));
end if;
else
end if;
end process;
end Behavioural;
hdl/trigger/rtl/gc_ff.vhd deleted 100755 → 0
View file @ 4bcd1c14
----------------------------------------------------------------------------------
-- Company: CERN
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:26:32 10/07/2011
-- Design Name: Basic debouncer
-- Module Name: debouncer - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_ff is
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end gc_ff;
architecture Behavioral of gc_ff is
begin
reg_proc: process(C)
begin
if rising_edge(C) then
if CLR = '1' then
Q <= '0';
else
Q <= D;
end if;
else
end if;
end process;
end Behavioral;
hdl/trigger/rtl/monostable.vhd deleted 100755 → 0
View file @ 4bcd1c14
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:00:11 10/12/2011
-- Design Name: Basic monostable
-- Module Name: monostable - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: A basic monostable circuit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity monostable is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pulse_len : in STD_LOGIC_VECTOR(31 downto 0);
write_tt_o : out STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end monostable;
architecture Behavioral of monostable is
type fsm is (S0_WAITING, S1_OK, S2_FORBIDDEN);
signal blo_pulse_fsm : fsm;
signal s_count_max : UNSIGNED (32 downto 0);
signal s_count_max2 : UNSIGNED (32 downto 0);
signal s_count : UNSIGNED (32 downto 0);
signal write_tt_s : STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
write_tt_o <= write_tt_s;
if (rst = '1') then
output <= '0';
write_tt_s <= '0';
blo_pulse_fsm <= S0_WAITING;
else
case blo_pulse_fsm is
when S0_WAITING =>
if input = '1' then
blo_pulse_fsm <= S1_OK;
s_count_max <= unsigned('0' & std_logic_vector(pulse_len));
s_count_max2 <= unsigned(std_logic_vector(pulse_len) & '0');
s_count(32 downto 1) <= (others => '0');
s_count(0) <= '1';
output <= '1';
write_tt_s <= '1';
else
end if;
when S1_OK =>
s_count <= s_count + 1;
write_tt_s <= '0';
if s_count = s_count_max then
blo_pulse_fsm <= S2_FORBIDDEN;
output <= '0';
else
end if;
when S2_FORBIDDEN =>
s_count <= s_count + 1;
if s_count = s_count_max2 then
blo_pulse_fsm <= S0_WAITING;
else
end if;
when others =>
end case;
end if;
else
end if;
end process;
end Behavioral;
hdl/trigger/rtl/trigger_core.vhd
View file @ 7ee393fc
......@@ -18,121 +18,247 @@
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.ctdah_pkg.ALL;
use work.trigger_pkg.ALL;
entity trigger_core is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
led_o : out STD_LOGIC;
led_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
write_tt_o : out STD_LOGIC;
write_tt_o : out STD_LOGIC;
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0)
CTR0_i : in r_CTR0;
CTR1_i : in r_CTR1;
CTR2_o : out r_CTR2
);
end trigger_core;
architecture Behavioral of trigger_core is
constant c_MAX_GLITCH_STAGES : INTEGER := 6;
signal deglitched_input : STD_LOGIC;
signal deglitched_input_s : STD_LOGIC;
signal monostable_input_s : STD_LOGIC;
signal count_s : STD_LOGIC_VECTOR(15 downto 0);
signal pulse_i_controlled : STD_LOGIC;
component debouncer
generic(
g_LENGTH : INTEGER := c_MAX_GLITCH_STAGES
);
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in std_logic_vector(g_LENGTH - 1 downto 0)
);
end component;
component monostable
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pulse_len : in STD_LOGIC_VECTOR(31 downto 0);
write_tt_o : out STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC
);
end component;
signal s_pulse : STD_LOGIC;
signal s_deglitched_pulse : STD_LOGIC;
signal s_deglitched_pulse_d0 : STD_LOGIC;
signal s_PET_counter_rst : STD_LOGIC;
signal s_PET_counter_en : STD_LOGIC;
begin
signal s_CTR0 : r_CTR0;
signal s_CTR0_d0 : r_CTR0;
signal s_CTR2 : r_CTR2;
type t_level_mon_fsm is (R0_RESET,
S0_IDLE,
S1_START_EDGE_DETECTED,
S2_ACTIVE_STATE,
S2A_LONG_PULSE_NOTIFICATION,
S3_END_EDGE_DETECTED,
S3A_SHORT_PULSE_NOTIFICATION,
Q0_ERROR);
count_s <= CTR0_i(30 downto 16) & '0';
pulse_i_controlled <= pulse_i and CTR0_i(0);
signal s_MON_fsm : t_level_mon_fsm;
begin
s_CTR0 <= CTR0_i;
s_CTR1 <= CTR1_i;
CTR2_o <= s_CTR2;
inst_debo: debouncer
inst_debo: gc_debouncer
generic map( g_LENGTH => 6)
port map(
rst => wb_rst_i,
clk => wb_clk,
input => pulse_i_controlled,
output => deglitched_input,
glitch_mask => CTR0_i(c_MAX_GLITCH_STAGES - 1 + 8 downto 8)
clk => wb_clk_i,
input => pulse_i,
output => s_deglitched_pulse,
glitch_mask => s_CTR0.CGM
);
inst_mono: monostable
inst_mono: gc_monostable
port map(
rst => wb_rst_i,
clk => wb_clk,
rst => wb_rst_i,
clk => wb_clk_i,
pulse_len(31 downto 16) => X"0000",
pulse_len(15 downto 0) => STATUS_i(31 downto 16),
write_tt_o => write_tt_o,
input => deglitched_input,
output => pulse_o
pulse_len(15 downto 0) => s_CTR0.CPL,
write_tt_o => write_tt_o,
input => s_deglitched_pulse,
output => pulse_o
);
led_mono: monostable
led_mono: gc_monostable
port map(
rst => wb_rst_i,
clk => wb_clk,
pulse_len => X"00989680", -- 500ms
clk => wb_clk_i,
pulse_len => STD_LOGIC_VECTOR(to_unsigned(c_LED_PERIOD, 32)), -- 500ms
-- write_tt_o => 'Z',
input => deglitched_input,
output => led_o
);
input => s_deglitched_pulse,
output => led_o);
process(wb_clk)
PET_counter: gc_counter
generic map(g_DATA_WIDTH => 16)
port map(
clk_i => wb_clk_i,
rst_i => s_PET_counter_rst,
en_i => s_PET_counter_en,
cnt_o => s_CTR2.PET);
begin
if rising_edge(wb_clk) then
--! @brief Some delays
--! @param wb_clk_i System clock
p_delays : process (wb_clk_i) is
begin
if rising_edge(wb_clk_i) then
s_pulse_d0 <= s_pulse;
s_CTR0_d0 <= s_CTR0;
end if;
end process p_delays;
if STATUS_i(0) = '1' then
deglitched_input_s <= deglitched_input;
--! @brief Stupid repetitor process to keep reliability high in basic
--! functionality.
--! A pulse is repeated whenever it is able to pass the deglitching
--! mask.
--! @param wb_clk_i System clock
p_pulse_i_en: process(wb_clk_i) is
begin
if rising_edge(wb_clk_i) then
if s_CTR0.EN = '1' then
if s_CTR0.AH = '1' then
s_pulse <= pulse_i;
else
s_pulse <= not(pulse_i);
end if;
else
s_pulse <= '0';
end if;
end if;
end process p_pulse_i_en;
--! @brief Assignment of signals to be feed into an external unit through
--! CTR2
--! @param s_MON_fsm Pulse monitor fsm current status
p_comb_MON_CTR2 : process (s_MON_fsm) is
begin
s_CTR2.SPF <= c_CTR2_default.SPF;
s_CTR2.LPF <= c_CTR2_default.LPF;
s_CTR2.EPF <= c_CTR2_default.EPF;
s_CTR2.x <= c_CTR2_default.x;
case s_MON_fsm is
when S2A_LONG_PULSE_NOTIFICATION =>
s_CTR2.LPF <= '1';
when S3_END_EDGE_DETECTED =>
if long_pulse_notification = '1' then
s_CTR2.LPF <= '1';
end if;
s_CTR2.EPF <= '1';
when S3A_SHORT_PULSE_NOTIFICATION =>
s_CTR2.SPF <= '1';
s_CTR2.EPF <= '1';
when others =>
null;
end case;
end process p_comb_MON_CTR2;
end process;
--! @brief Synchronous process for the monitor fsm
--! @param wb_clk_i System clock
--! wb_rst_i Wishbone reset
p_level_mon_fsm : process (wb_clk_i, wb_rst_i) is
function start_detection return STD_LOGIC is
variable v_return : STD_LOGIC;
begin
v_return := '0';
if (s_deglitched_pulse
xor s_deglitched_pulse_d0) = '1' then
if s_deglitched_pulse = s_CTR0.AH then
v_return := '1';
end if;
end if;
return v_return;
end function;
function end_detection return STD_LOGIC is
variable v_return : STD_LOGIC;
begin
v_return := '0';
if (s_deglitched_pulse
xor s_deglitched_pulse_d0) = '1' then
if s_deglitched_pulse_d0 = s_CTR0.AH then
v_return := '1';
end if;
end if;
return v_return;
end function;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
s_MON_fsm <= R0_RESET;
else
if s_CTR0.AH /= s_CTR0_d0.AH then
s_MON_fsm <= R0_RESET;
else
case s_MON_fsm is
--! We specify one clock delay after the reset to detect correct
--! deglitched pulses
when R0_RESET =>
s_MON_fsm <= S0_IDLE;
when S0_IDLE =>
if start_detection = '1' then
s_MON_fsm <= S1_START_EDGE_DETECTED;
end if;
when S1_START_EDGE_DETECTED =>
if end_detection = '1' then
s_MON_fsm <= S3A_SHORT_PULSE_NOTIFICATION;
else
s_MON_fsm <= S2_ACTIVE_STATE;
end if;
when S2_ACTIVE_STATE =>
case end_detection is
when '1' =>
if short_pulse = '1' then
s_MON_fsm <= S3A_SHORT_PULSE_NOTIFICATION;
else
s_MON_fsm <= S3_END_EDGE_DETECTED;
end if;
when others =>
if long_pulse_notification = '1' then
s_MON_fsm <= S2A_LONG_PULSE_NOTIFICATION;
end if;
end case;
when S2A_LONG_PULSE_NOTIFICATION =>
case end_detection is
when '1' =>
s_MON_fsm <= S3_END_EDGE_DETECTED;
when others =>
s_MON_fsm <= S2_ACTIVE_STATE;
end case;
when S3_END_EDGE_DETECTED =>
--! As we will deglitch more than one cycle, no pulses will
--! be missed
s_MON_fsm <= S0_IDLE;
when S3A_SHORT_PULSE_NOTIFICATION =>
--! As we will deglitch more than one cycle, no pulses will
--! be missed
s_MON_fsm <= S0_IDLE;
when others =>
s_MON_fsm <= R0_RESET;
end case;
end if;
end if;
end if;
end process p_level_mon_fsm;
end Behavioral;
hdl/trigger/rtl/trigger_pkg.vhd 0 → 100755
View file @ 7ee393fc
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
-- Module Name: trigger_pkg - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Package providing all the register configurations for the
-- SPI core.
--
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package trigger_pkg is
-------------------------------------
-- Clocking for deglitch and pulse length
-------------------------------------
--! System clock @ 20MHz, hence 50 ns
constant c_CLOCK_PERIOD : NATURAL := 50;
constant c_MAX_GLITCH_STAGES : INTEGER := 6;
constant c_DEFAULT_GLITCH_MASK : UNSIGNED(c_MAX_GLITCH_STAGES-1 downto 0)
--! Every pulse below this threshold will be notified
constant c_MIN_PULSE_LENGTH : NATURAL := 600/c_CLOCK_PERIOD;
constant c_DEFAULT_PULSE_LENGTH : NATURAL := 1000/c_CLOCK_PERIOD;
--! Every pulse above this threshold will be notified
constant c_MAX_PULSE_LENGTH : NATURAL := 1400/c_CLOCK_PERIOD;
constant c_LED_PERIOD : NATURAL := 500000000/c_CLOCK_PERIOD;
-------------------------------------
-- Timetagging RAM parameters
-------------------------------------
constant c_RAM_ADDR_BITS : INTEGER := 8; --! Upto 256 pulses
--! per channel
constant c_RAMTT_DATA_WIDTH : INTEGER := 96/8; --! In bytes
constant c_RAMID_DATA_WIDTH : INTEGER := 32/8; --! In bytes
attribute a_length : NATURAL;
-------------------------------------
-- CTR0 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
------------------------------------
-- BIT NAME Description
-- 0 EN General ENable
-- 1 AH Active High pulse (otherwise is low)
-- 2 EN_TT ENable Time-Tagging
-- 3 CLR_TT CLeaR Time-Tagging
-- 4 EMPTY RAM empty flag
-- 5 FULL RAM full flag
-- 6 WA RAM wrapped around
-- 8-7 RDM time-tagging ReaD Mode
-- 15-9 CGM Current Glitch Mask
-- 31-16 CPL Current output Pulse Length
-------------------------------------
type r_CTR0 is
record
EN : STD_LOGIC;
AH : STD_LOGIC;
EN_TT : STD_LOGIC;
CLR_TT : STD_LOGIC;
EMPTY : STD_LOGIC;
FULL : STD_LOGIC;
WA : STD_LOGIC;
RDM : STD_LOGIC_VECTOR (8 downto 7);
CGM : STD_LOGIC_VECTOR (15 downto 9);
CPL : STD_LOGIC_VECTOR (31 downto 16);
end record;
attribute a_length of r_CTR0 : type is 32;
-------------------------------------
-- CTR1 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 15-0 MinPL Minimum input Pulse Length Threshold
-- 31-16 MaxPL Maximum input Pulse Length Threshold
-------------------------------------
type r_CTR1 is
record
MinPL : UNSIGNED (15 downto 0);
MaxPL : UNSIGNED (31 downto 16);
end record;
attribute a_length of r_CTR1 : type is 32;
-------------------------------------
-- CTR2 register
-------------------------------------
-- 24 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 15-0 PET input Pulse Elapsed Time
-- 16 SPF Short Pulse Flag
-- 17 LPF Long Pulse Flag
-- 18 EPF End Pulse Flag
-- 23-19 x Reserved
-------------------------------------
type r_CTR2 is
record
PET : UNSIGNED (15 downto 0);
SPF : STD_LOGIC;
LPF : STD_LOGIC;
EPF : STD_LOGIC;
x : STD_LOGIC_VECTOR(23 downto 19);
end record;
attribute a_length of r_CTR2 : type is 24;
-------------------------------------
-- RAM0 register
-------------------------------------
-- 8 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 0 WER Write Enable into RAM
-- 2-1 RDM time-tagging ReaD Mode
-- 3 RQT ReQuesT read
--- 7-4 x Reserved
-------------------------------------
type r_RAM0 is
record
WER : STD_LOGIC;
RDM : STD_LOGIC_VECTOR(2 downto 1);
RQT : STD_LOGIC;
x : STD_LOGIC_VECTOR(7 downto 4);
end record;
attribute a_length of r_RAM0 : type is 8;
-------------------------------------
-- RAM1 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
-------------------------------------
-- BIT NAME Description
-- 15-0 CRA Current Read Address
-- 31-16 CWA Current Write Address
-------------------------------------
type r_RAM1 is
record
CRA : UNSIGNED(15 downto 0);
CWA : UNSIGNED(31 downto 16);
end record;
attribute a_length of r_RAM1 : type is 32;
-------------------------------------
-- RAM2 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 15-0 SA Starting read Address
-- 31-16 EA Ending read Address
-------------------------------------
type r_RAM2 is
record
SA : STD_LOGIC_VECTOR(15 downto 0);
EA : STD_LOGIC_VECTOR(31 downto 16);
end record;
attribute a_length of r_RAM2 : type is 32;
constant c_CTR0_default : r_CTR0 := (
EN => '1',
CLR => '1',
EN_TT => '1',
CLR_TT => '1',
EMPTY => '1',
FULL => '0',
WA => '0',
RDM => (others => '0'),
CGM => (others => '1'),
-- TIP: the lenght of the repeated pulse must be 1us by default.
-- Considering that wb period is 50 ns (20 MHz) a value of
-- 30 jiffies should be set by default.
CPL => STD_LOGIC_VECTOR(TO_UNSIGNED(
c_DEFAULT_PULSE_LENGTH, 16)));
constant c_CTR1_default : r_CTR1 := (
MinPL => to_unsigned(c_MIN_PULSE_LENGTH, 16),
MaxPL => to_unsigned(c_MAX_PULSE_LENGTH, 16));
constant c_CTR2_default : r_CTR2 := (PET => (others => '0'),
SPF => '0',
LPF => '0',
EPF => '0',
x => (others => '0'));
constant c_RAM0_default : r_RAM0 := (RDM => (others => '0'),
RQT => '0');
constant c_RAM1_default : r_RAM1 := (CRA => to_unsigned(0, 16),
CWA => to_unsigned(0, 16));
constant c_RAM2_default : r_RAM2 := (SA => (others => '0'),
EA => (others => '0'));
-------------------------------------
-- Memory mapping
-------------------------------------
constant CTR0_addr : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant CTR1_addr : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant CTR2_addr : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant RAM0_addr : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant RAM1_addr : STD_LOGIC_VECTOR (2 downto 0) := "110";
constant RAM2_addr : STD_LOGIC_VECTOR (2 downto 0) := "111";
function f_CTR0 (
r_register_slv: STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0))
return r_CTR0;
function f_CTR1 (
r_register_slv: STD_LOGIC_VECTOR(r_CTR1'a_length - 1 downto 0))
return r_CTR1;
function f_CTR2 (
r_register_slv: STD_LOGIC_VECTOR(r_CTR1'a_length - 1 downto 0))
return r_CTR2;
function f_RAM0 (
r_register_slv: STD_LOGIC_VECTOR(r_RAM0'a_length - 1 downto 0))
return r_RAM0;
function f_RAM1 (
r_register_slv: STD_LOGIC_VECTOR(r_RAM1'a_length - 1 downto 0))
return r_RAM1;
function f_RAM2 (
r_register_slv: STD_LOGIC_VECTOR(r_RAM2'a_length - 1 downto 0))
return r_RAM2;
function f_STD_LOGIC_VECTOR(r_register : r_CTR0) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_CTR1) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_CTR2) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_RAM0) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_RAM1) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_RAM2) return STD_LOGIC_VECTOR;
component trigger_core is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
led_o : out STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
write_tt_o : out STD_LOGIC;
CTR0_i : in r_CTR0;
CTR1_i : in r_CTR1;
CTR2_o : out r_CTR2
);
end component;
end trigger_pkg;
package body trigger_pkg is
function f_CTR0 (
r_register_slv: STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0))
return r_CTR0 is
variable v_CTR0 : r_CTR0;
begin
v_CTR0.EN := r_register_slv(0);
v_CTR0.AH := r_register_slv(1);
v_CTR0.EN_TT := r_register_slv(2);
v_CTR0.CLR_TT := r_register_slv(3);
v_CTR0.EMPTY := r_register_slv(4);
v_CTR0.FULL := r_register_slv(5);
v_CTR0.WA := r_register_slv(6);
v_CTR0.RDM := r_register_slv(8 downto 7);
v_CTR0.CGM := r_register_slv(r_CTR0'a_length - 1 downto 9);
end functiCPL on f_CTR0;
function f_CTR1 (
r_register_slv: STD_LOGIC_VECTOR(r_CTR1'a_length - 1 downto 0))
return r_CTR1 is
variable v_CTR1 : r_CTR1;
begin
v_CTR1.MinPL := UNSIGNED(r_register_slv(15 downto 0));
v_CTR1.MaxPL := UNSIGNED(r_register_slv(r_CTR1'a_length - 1 downto 16));
end function f_CTR1;
function f_CTR2 (
r_register_slv: STD_LOGIC_VECTOR(r_CTR1'a_length - 1 downto 0))
return r_CTR2 is
variable v_CTR2 : r_CTR2;
begin
v_CTR2.PET := UNSIGNED(r_register_slv(15 downto 0));
v_CTR2.SPF := r_register_slv(16);
v_CTR2.LPF := r_register_slv(17);
v_CTR2.EPF := r_register_slv(18);
v_CTR2.x := r_register_slv(r_CTR2'a_length - 1 downto 19);
end function f_CTR2;
function f_RAM0 (
r_register_slv: STD_LOGIC_VECTOR(r_RAM0'a_length - 1 downto 0))
return r_RAM0 is
variable v_RAM0 : r_RAM0;
begin
v_RAM0.WER := r_register_slv(0)
v_RAM0.RDM := r_register_slv(2 downto 1);
v_RAM0.RQT := r_register_slv(3);
v_RAM0.x := r_register_slv(r_RAM0'a_length - 1 downto 4);
end function f_RAM0;
function f_RAM1 (
r_register_slv: STD_LOGIC_VECTOR(r_RAM1'a_length - 1 downto 0))
return r_RAM1 is
variable v_RAM1 : r_RAM1;
begin
v_RAM1.CRA := UNSIGNED(r_register_slv(15 downto 0));
v_RAM1.CWA := UNSIGNED(r_register_slv(r_RAM1'a_length - 1 downto 16));
end function f_RAM1;
function f_RAM2 (
r_register_slv: STD_LOGIC_VECTOR(r_RAM2'a_length - 1 downto 0))
return r_RAM2 is
variable v_RAM2 : r_RAM2;
begin
v_RAM2.SA := r_register_slv(15 downto 0);
v_RAM2.EA := r_register_slv(r_RAM2'a_length - 1 downto 16);
end function f_RAM2;
function f_STD_LOGIC_VECTOR(r_register : r_CTR0) return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
begin
v_return(0) := r_register.EN;
v_return(1) := r_register.AH;
v_return(2) := r_register.EN_TT;
v_return(3) := r_register.CLR_TT;
v_return(4) := r_register.EMPTY;
v_return(5) := r_register.FULL;
v_return(6) := r_register.WA;
v_return(8 downto 7) := r_register.RDM;
v_return(15 downto 9) := r_register.CGM;
v_return(31 downto 16) := r_register.CPL;
return v_return;
end function f_STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_CTR1) return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(r_CTR1'a_length - 1 downto 0);
begin
v_return(15 downto 0) := STD_LOGIC_VECTOR(r_register.MinPL);
v_return(r_CTR1'a_length - 1 downto 16)
:= STD_LOGIC_VECTOR(r_register.MaxPL);
return v_return;
end function f_STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_CTR2) return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(r_CTR2'a_length - 1 downto 0);
begin
v_return(15 downto 0) := STD_LOGIC_VECTOR(r_register.PET);
v_return(16) := r_register.SPF;
v_return(17) := r_register.LPF;
v_return(18) := r_register.EPF;
v_return(r_CTR2'a_length - 1 downto 19) := r_register.x;
return v_return;
end function f_STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_RAM0) return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(r_RAM0'a_length - 1 downto 0);
begin
v_return(0) := r_register.WER;
v_return(2 downto 1) := r_register.RDM;
v_return(3) := r_register.RQT;
v_return(r_RAM0'a_length - 1 downto 4) := r_register.x;
return v_return;
end function f_STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_RAM1) return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(r_RAM1'a_length - 1 downto 0);
begin
v_return(15 downto 0) := r_register.CRA;
v_return(r_RAM1'a_length - 1 downto 16) := r_register.CWA;
return v_return;
end function f_STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : r_RAM2) return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(r_RAM2'a_length - 1 downto 0);
begin
v_return(15 downto 0) := r_register.SA;
v_return(r_RAM2'a_length - 1 downto 16) := r_register.EA;
return v_return;
end function f_STD_LOGIC_VECTOR;
end trigger_pkg;
hdl/trigger/rtl/trigger_regs.vhd
View file @ 7ee393fc
......@@ -39,399 +39,161 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.ctdah_pkg.ALL;
use work.trigger_pkg.ALL;
entity trigger_regs is
generic(
g_MAX_GLITCH_STAGES : INTEGER := 6;
g_DEFAULT_GLITCH_MASK : UNSIGNED (5 downto 0) := (others => '1');
-- Minimum output pulse width is 1us
-- Maximum output pulse width is 2us
-- Default values are for a reference clock of 20MHz
g_MIN_PULSE_LENGTH : INTEGER := 20;
g_MAX_PULSE_LENGTH : INTEGER := 40;
g_DEFAULT_PULSE_LENGTH : INTEGER := 30
);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (2 downto 0);
STATUS_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM0_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_o : out STD_LOGIC_VECTOR (31 downto 0);
utc_i : in STD_LOGIC_VECTOR(g_RAMTT_DATA_WIDTH*8 - 1 downto 0);
ramTT_i : in STD_LOGIC_VECTOR (95 downto 0);
ramID_i : in STD_LOGIC_VECTOR (31 downto 0)
CTR0_o : out r_CTR0;
CTR1_o : out r_CTR1;
CTR2_i : in r_CTR2;
RAM0_o : out r_RAM0;
RAM1_i : in r_RAM1;
RAM2_o : out r_RAM2
);
end trigger_regs;
architecture Behavioral of trigger_regs is
type RAM_fsm is (S0_IDLE, S1_READ_B0, S2_READ_B1, S3_READ_B2, S4_READ_B3);
signal RAMstate : RAM_fsm;
-------------------------------------
-- STATUS register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 0 EN General ENable
-- 1 CLR General CLeaR
-- 3-2 x Reserved
-- 4 EN_TT ENable Time-Tagging
-- 5 CLR_TT CLeaR Time-Tagging
-- 7-6 x Reserved
-- 8 EMPTY RAM empty flag
-- 9 FULL RAM full flag
-- 10 WA RAM wrapped around
-- 15-11 x Reserved
-- 31-16 CPL Current Pulse Length
-------------------------------------
constant STATUS_addr : STD_LOGIC_VECTOR (2 downto 0) := "000";
-------------------------------------
-- CTR0 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 0 EN General ENable
-- 1 CLR General CLeaR
-- 3-2 x Reserved
-- 4 EN_TT ENable Time-Tagging
-- 5 CLR_TT CLeaR time-tagging
-- 7-6 RDM time-tagging ReaD Mode
-- 15-8 CGM Current Glitch Mask
-- 31-16 CPL Current Pulse Length
-------------------------------------
-- TIP: CGM is used from lowest to highest
-------------------------------------
constant CTR0_addr : STD_LOGIC_VECTOR (2 downto 0) := "001";
-------------------------------------
-- CTR1 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 15-0 MinPL Minimum Pulse Length
-- 31-16 MaxPL Maximum Pulse Length
-------------------------------------
constant CTR1_addr : STD_LOGIC_VECTOR (2 downto 0) := "010";
-------------------------------------
-- RAM0 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 0 EN_TT Enable Time-tagging
-- 1 CLR_TT Clear whole contents
-- 3-2 RDM time-tagging ReaD Mode
-- 4 EMPTY RAM empty
-- 5 FULL RAM full
-- 6 WA RAM Wrapped around
-- 7 RQT ReQuesT read
-- 31-8 x Reserved
-------------------------------------
constant RAM0_addr : STD_LOGIC_VECTOR (2 downto 0) := "101";
-------------------------------------
-- RAM1 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
-------------------------------------
-- BIT NAME Description
-- 15-0 CRA Current Read Address
-- 31-16 CWA Current Write Address
-------------------------------------
constant RAM1_addr : STD_LOGIC_VECTOR (2 downto 0) := "110";
-------------------------------------
-- RAM2 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 15-0 SA Starting read Address
-- 31-16 EA Ending read Address
-------------------------------------
constant RAM2_addr : STD_LOGIC_VECTOR (2 downto 0) := "111";
type RAM_fsm is (R0_RESET,
S0_IDLE,
S1_READ_B0,
S2_READ_B1,
S3_READ_B2,
S4_READ_B3);
signal STATUS_reg : STD_LOGIC_VECTOR (31 downto 0);
signal CTR0_reg : STD_LOGIC_VECTOR (31 downto 0);
signal CTR1_reg : STD_LOGIC_VECTOR (31 downto 0);
signal RAM0_reg : STD_LOGIC_VECTOR (31 downto 0);
signal RAM1_reg : STD_LOGIC_VECTOR (31 downto 0);
signal RAM2_reg : STD_LOGIC_VECTOR (31 downto 0);
signal RAMstate : RAM_fsm;
signal wb_ack_s : STD_LOGIC;
signal wb_err_s : STD_LOGIC;
signal wb_rty_s : STD_LOGIC;
signal s_wb_ack : STD_LOGIC;
signal s_wb_err : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
signal s_wb_data_o : STD_LOGIC_VECTOR (31 downto 0);
signal EN : STD_LOGIC;
signal CLR : STD_LOGIC;
signal EN_TT : STD_LOGIC;
signal CLR_TT : STD_LOGIC;
signal EMPTY : STD_LOGIC;
signal FULL : STD_LOGIC;
signal WA : STD_LOGIC;
signal RDM : STD_LOGIC_VECTOR(1 downto 0);
signal CGM : STD_LOGIC_VECTOR(7 downto 0);
signal CPL : STD_LOGIC_VECTOR(15 downto 0);
signal MinPL : STD_LOGIC_VECTOR(15 downto 0);
signal MaxPL : STD_LOGIC_VECTOR(15 downto 0);
signal RQT : STD_LOGIC;
signal CRA : STD_LOGIC_VECTOR(15 downto 0);
signal CWA : STD_LOGIC_VECTOR(15 downto 0);
signal SA : STD_LOGIC_VECTOR(15 downto 0);
signal EA : STD_LOGIC_VECTOR(15 downto 0);
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_RAM0 : r_RAM0;
signal s_RAM2 : r_RAM2;
begin
STATUS_reg <= CPL & "00000" & WA & FULL & EMPTY & "00" & CLR_TT & EN_TT & "00" & CLR & EN;
CTR0_reg <= CPL & CGM & RDM & CLR_TT & EN_TT & "00" & CLR & EN;
CTR1_reg <= MaxPL & MinPL ;
RAM0_reg <= X"000000" & RQT & WA & FULL & EMPTY & RDM & CLR_TT & EN_TT;
RAM2_reg <= EA & SA;
STATUS_o <= STATUS_reg;
CTR0_o <= CTR0_reg;
CTR1_o <= CTR1_reg;
RAM0_o <= RAM0_reg;
RAM2_o <= RAM2_reg;
process(wb_clk)
CTR0_o <= s_CTR0;
CTR1_o <= s_CTR1;
RAM0_o <= s_RAM0;
RAM2_o <= s_RAM2;
wb_ack_o <= s_wb_ack;
wb_err_o <= s_wb_err;
wb_rty_o <= s_wb_rty;
wb_data_o <= s_wb_data_o;
RAMTT_256: gc_RAM
generic map(g_DATA_WIDTH => c_RAMTT_DATA_WIDTH,
g_ADDR_WIDTH => c_RAM_ADDR_BITS)
port map(
clka => wb_clk_i,
wea => s_RAM0.WER,
addra => s_RAM1.CWA(g_ADDR_WIDTH - 1 downto 0),
dina => utc_i,
clkb => clkb_s,
rstb => rstb_s,
addrb => s_RAM1.CRA(g_ADDR_WIDTH - 1 downto 0),
doutb => s_dout_RAMTT);
RAMID_256: gc_RAM
generic map(g_DATA_WIDTH => c_RAMID_DATA_WIDTH,
g_ADDR_WIDTH => c_RAM_ADDR_BITS)
port map(
clka => wb_clk_i,
wea => s_RAM0.WER,
addra => s_RAM1.CWA(g_ADDR_WIDTH - 1 downto 0),
--! Change to data to read
dina => (others => '0'),
clkb => clkb_s,
rstb => rstb_s,
addrb => s_RAM1.CRA(g_ADDR_WIDTH - 1 downto 0),
doutb => s_dout_RAMID);
process(wb_clk_i)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
RAMstate <= S0_IDLE;
EN <= '1';
CLR <= '1';
EN_TT <= '1';
CLR_TT <= '1';
EMPTY <= '1';
FULL <= '0';
WA <= '0';
-- TIP: the lenght of the repeated pulse must be 1us by default.
-- Considering that wb period is 50 ns (20 MHz) a value of
-- 30 jiffies should be set by default.
CPL <= STD_LOGIC_VECTOR(TO_UNSIGNED(g_DEFAULT_PULSE_LENGTH, 16));
-- Read mode is set to a default 0
RDM <= (others => '0');
-- Simple mask length
CGM <= (others => '1');
MinPL <= STD_LOGIC_VECTOR(TO_UNSIGNED(g_MIN_PULSE_LENGTH, 16));
MaxPL <= STD_LOGIC_VECTOR(TO_UNSIGNED(g_MAX_PULSE_LENGTH, 16));
RQT <= '0';
CRA <= (others => '0');
CWA <= (others => '0');
SA <= (others => '0');
EA <= (others => '0');
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '0';
wb_rty_s <= '0';
wb_data_o <= (others => '0');
elsif wb_stb_i = '1' and wb_cyc_i = '1' then
-- Block mode behaviour
if wb_ack_s = '1' or wb_err_s = '1' or wb_rty_s = '1' then
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '0';
wb_rty_s <= '0';
else
if wb_we_i = '0' then
case wb_addr_i (2 downto 0) is
when STATUS_addr =>
wb_data_o <= STATUS_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when CTR0_addr =>
wb_data_o <= CTR0_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when CTR1_addr =>
wb_data_o <= CTR1_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM0_addr =>
wb_data_o <= RAM0_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM1_addr =>
wb_data_o <= RAM1_i;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM2_addr =>
wb_data_o <= RAM2_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when others =>
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '1';
wb_rty_s <= '0';
end case;
else
case wb_addr_i is
when CTR0_addr =>
EN <= wb_data_i(0);
CLR <= wb_data_i(1);
EN_TT <= wb_data_i(4);
CLR_TT <= wb_data_i(5);
RDM <= wb_data_i(7 downto 6);
-- HW protection: anticipating bad CTR0 configuration
if wb_data_i(15 downto 8) = X"00" then
CGM <= X"01";
else
CGM <= wb_data_i(15 downto 8);
end if;
CPL <= wb_data_i(31 downto 16);
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when CTR1_addr =>
MinPL <= wb_data_i(15 downto 0);
MaxPL <= wb_data_i(31 downto 16);
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM0_addr =>
EN_TT <= wb_data_i(0);
CLR_TT <= wb_data_i(1);
RDM <= wb_data_i(3 downto 2);
-- EMPTY <= wb_data_i(4);
-- FULL <= wb_data_i(5);
-- WA <= wb_data_i(6);
RQT <= wb_data_i(7);
if STATUS_reg(0) = '1' and wb_data_i(0) = '1' and wb_data_i (7) = '1' then
case RAMstate is
when S0_IDLE =>
RAMstate <= S1_READ_B0;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S1_READ_B0 =>
wb_data_o <= RAMTT_i(31 downto 0);
RAMstate <= S2_READ_B1;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S2_READ_B1 =>
wb_data_o <= RAMTT_i(63 downto 32);
RAMstate <= S3_READ_B2;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S3_READ_B2 =>
wb_data_o <= RAMTT_i(95 downto 64);
RAMstate <= S4_READ_B3;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S4_READ_B3 =>
wb_data_o <= RAMID_i(31 downto 0);
RAMstate <= S0_IDLE;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
when others =>
RAMstate <= S0_IDLE;
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '0';
end case;
else
end if;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM2_addr =>
SA <= wb_data_i(15 downto 0);
EA <= wb_data_i(31 downto 16);
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when others =>
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '1';
wb_rty_s <= '0';
end case;
end if;
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
RAMstate <= S0_IDLE;
s_CTR0 <= c_CTR0_default;
s_CTR1 <= c_CTR1_default;
s_RAM0 <= c_RAM0_default;
s_RAM2 <= c_RAM2_default;
s_wb_ack <= '0';
s_wb_err <= '0';
s_wb_rty <= '0';
s_wb_data <= (others => '0');
elsif wb_stb_i = '1' and wb_cyc_i = '1' then
wb_ack_s <= '0';
wb_err_s <= '0';
wb_rty_s <= '0';
if (wb_ack_s or wb_err_s or wb_rty_s) = '1' then
else
case wb_we_i is
when '0' =>
case wb_addr_i (2 downto 0) is
when CTR0_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR0);
wb_ack_s <= '1';
when CTR1_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR1);
wb_ack_s <= '1';
when CTR2_addr =>
wb_data_o(r_CTR2'a_length - 1 downto 0)
<= f_STD_LOGIC_VECTOR(s_CTR2);
wb_data_o(31 downto r_CTR2'a_length) <= (others => '0');
wb_ack_s <= '1';
when RAM0_addr =>
wb_data_o(r_RAM0'a_length - 1 downto 0)
<= f_STD_LOGIC_VECTOR(s_RAM0);
wb_data_o(31 downto r_RAM0'a_length) <= (others => '0');
wb_ack_s <= '1';
when RAM1_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_RAM1);
wb_ack_s <= '1';
when RAM2_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_RAM2);
wb_ack_s <= '1';
when others =>
wb_err_s <= '1';
end case;
when others =>
--! TODO implement writes
case wb_addr_i is
when CTR0_addr =>
when CTR1_addr =>
when CTR2_addr =>
when RAM0_addr =>
when RAM1_addr =>
when RAM2_addr =>
when others =>
wb_err_s <= '1';
end case;
end case;
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
hdl/trigger/rtl/trigger_top.vhd
View file @ 7ee393fc
......@@ -21,8 +21,11 @@
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.trigger_pkg.ALL;
entity trigger_top is
......@@ -35,7 +38,7 @@ entity trigger_top is
utc_i : in STD_LOGIC_VECTOR(95 downto 0);
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
......@@ -52,116 +55,42 @@ end trigger_top;
architecture Behavioral of trigger_top is
constant c_RAM_SIZE : UNSIGNED(15 downto 0) := X"0100";
constant c_MAX_GLITCH_STAGES : INTEGER := 6;
constant c_DEFAULT_GLITCH_MASK : UNSIGNED(c_MAX_GLITCH_STAGES-1 downto 0) := "000011";--(others => '1');
-- Let's assume that a 20MHz clock is used in wishbone
constant c_MIN_PULSE_LENGTH : INTEGER := 20;
constant c_MAX_PULSE_LENGTH : INTEGER := 40;
constant c_DEFAULT_PULSE_LENGTH : INTEGER := 30;
constant c_TAGS_DATA_WIDTH : INTEGER := 96;
signal STATUS_s : STD_LOGIC_VECTOR (31 downto 0);
signal CTR0_s : STD_LOGIC_VECTOR (31 downto 0);
signal CTR1_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM0_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM1_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM2_s : STD_LOGIC_VECTOR (31 downto 0);
signal write_tt_s : STD_LOGIC;
signal ramTT_s : STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH - 1 downto 0);
signal ramID_s : STD_LOGIC_VECTOR(31 downto 0);
component trigger_regs
generic(
g_MAX_GLITCH_STAGES : INTEGER := c_MAX_GLITCH_STAGES;
g_DEFAULT_GLITCH_MASK : UNSIGNED (c_MAX_GLITCH_STAGES - 1 downto 0) := c_DEFAULT_GLITCH_MASK;
g_MIN_PULSE_LENGTH : INTEGER := c_MIN_PULSE_LENGTH;
g_MAX_PULSE_LENGTH : INTEGER := c_MAX_PULSE_LENGTH;
g_DEFAULT_PULSE_LENGTH : INTEGER := c_DEFAULT_PULSE_LENGTH
);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
-- Terminating signals
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (2 downto 0);
STATUS_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM0_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_o : out STD_LOGIC_VECTOR (31 downto 0);
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_CTR2 : r_CTR2;
signal s_RAM0 : r_RAM0;
signal s_RAM1 : r_RAM1;
signal s_RAM2 : r_RAM2;
ramTT_i : in STD_LOGIC_VECTOR (95 downto 0);
ramID_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end component;
signal write_tt_s : STD_LOGIC;
signal ramTT_s : STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH*8 - 1 downto 0);
signal ramID_s : STD_LOGIC_VECTOR(31 downto 0);
component trigger_core is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
begin
led_o : out STD_LOGIC;
core: trigger_core
port map(
pulse_i => pulse_i,
pulse_o => pulse_o,
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
led_o => led_o,
write_tt_o : out STD_LOGIC;
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end component;
write_tt_o => write_tt_s,
component TT_RAMhandler is
generic (
g_TAGS_DATA_WIDTH : INTEGER := 96
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
CTR2_o => CTR2_s
);
port (
utc_i : in STD_LOGIC_VECTOR(g_TAGS_DATA_WIDTH - 1 downto 0);
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
write_tt_i : in STD_LOGIC;
ramTT_o : out STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH - 1 downto 0);
ramID_o : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
begin
registers: trigger_regs
port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_clk_i => wb_clk_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_ack_o => wb_ack_o,
......@@ -173,7 +102,6 @@ begin
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
STATUS_o => STATUS_s,
CTR0_o => CTR0_s,
CTR1_o => CTR1_s,
RAM0_o => RAM0_s,
......@@ -184,41 +112,5 @@ begin
ramID_i => ramID_s
);
core: trigger_core
port map(
pulse_i => pulse_i,
pulse_o => pulse_o,
led_o => led_o,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
write_tt_o => write_tt_s,
STATUS_i => STATUS_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
RAM0_i => RAM0_s,
RAM1_i => RAM1_s,
RAM2_i => RAM2_s
);
ram_handler: TT_RAMhandler
port map(
utc_i => utc_i,
STATUS_i => STATUS_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
RAM0_i => RAM0_s,
RAM1_o => RAM1_s,
RAM2_i => RAM2_s,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
write_tt_i => write_tt_s,
ramTT_o => ramTT_s,
ramID_o => ramID_s
);
end Behavioral;
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