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Conv TTL Blocking
Commit 820a31e0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added test-log doc, renamed ug/Figures to ug/f

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doc/test-log/Makefile 0 → 100644
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FILE=test-log
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
# bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
doc/test-log/fig/dct1-setup.svg 0 → 100644
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doc/test-log/test-log.tex 0 → 100644
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\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\begin{document}
\title{
\textbf{
Conv-TTL-Blo \\
Test Log \\
}
}
\author{Theodor-Adrian Stana\\
% \href{mailto:t.stana@cern.ch}{\textbf{\textit{t.stana@cern.ch}}}\\
BE-CO-HT\\
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
%\tableofcontents
\pagebreak
\listoffigures
\listoftables
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\thispagestyle{empty}
%==============================================================================
% SEC: Chain test 1
%==============================================================================
\section{Daisy-chain test 1}
\label{sec:chain-test-1}
The setup for this test is as shown in Fig.~\ref{fig:dct1-setup}. A CTRV board
is used to generate TTL pulses to the Conv-TTL-Blo after which this pulse is
daisy-chained as shown in the figure. Both TTL and blocking pulses are generated
in the daisy-chain; Fig.~\ref{fig:dct1-setup} highlights the channel where a
switch from TTL to blocking or viceversa is made.
\begin{figure}[h]
\centerline{\includegraphics[scale=.8]{fig/dct1-setup}}
\caption{Setup for daisy-chain test 1}
\label{fig:dct1-setup}
\end{figure}
Three counters in the CTRV are used; the first is the one which generates the
pulses to be sent through the daisy-chain. The output of the first counter is
used as the start signal itself and as the clock for the second-channel counter.
The second channel counter is used as the start signal for the third-channel counter.
The settings for all of the channels are shown in Table~\ref{tbl:ctrv-counters}.
Each CTRV counter generates a pulse signal on the output either when the counter
reaches 0 or when there is a rising edge on the start input. Thus, the configuration
in Table~\ref{tbl:ctrv-counters} yields 1~$\mu$s pulses generated at a frequency of
100~kHz and passed through the daisy-chain. Since the channel 2 counter is configured
with a max. value of two, if any pulse is missed through the daisy-chain, its output
goes high and this causes the channel three counter to trigger an interrupt.
The CTRV is monitored for interrupts using the \textit{ctrvtest} program; any missed
pulses (any interrupts) are time-tagged by the program, thus showing when a pulse was
missed.
\begin{table}[h]
\caption{CTRV counter settings}
\label{tbl:ctrv-counters}
\centerline
{
\begin{tabular}{c c c c}
\hline
\textbf{Chan} & \textbf{Pulse width} & \textbf{Freq} & \textbf{Max val} \\
\hline
1 & 1~$\mu$s & 100~kHz & 100 \\
2 & -- & -- & 2 \\
3 & -- & -- & 1 \\
\hline
\end{tabular}
}
\end{table}
\end{document}
doc/ug/ug-conv-ttl-blo.tex
View file @ 820a31e0
......@@ -20,7 +20,7 @@ BE-CO-HT\\
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
\includegraphics[scale=0.25, keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
......@@ -81,7 +81,7 @@ CONV-TTL-RTM and CONV-TTL-RTM-BLO.\\
\begin{figure}[!h]
\begin{center}
\includegraphics[scale=0.55, keepaspectratio]{Figures/BLOschema.png}
\includegraphics[scale=0.55, keepaspectratio]{fig/BLOschema.png}
\caption{Pulse Repetition system}
\label{prs}
\end{center}
......@@ -241,7 +241,7 @@ of status LEDs and several ports, divided in four sections from top to bottom:
\begin{figure}[!htdp]
\begin{center}
\includegraphics[scale=.5, keepaspectratio]{Figures/front-panel}
\includegraphics[scale=.5, keepaspectratio]{fig/front-panel}
\caption{CONV-TTL-BLO panel (front panel)}
\label{fp}
\end{center}
......@@ -318,7 +318,7 @@ When a pulse is repeated on the output connector of a channel, the pulse status
\begin{figure}
\begin{center}
\includegraphics[scale=.55, keepaspectratio]{Figures/rear-panel}
\includegraphics[scale=.55, keepaspectratio]{fig/rear-panel}
\caption{CONV-TTL-BLO-RTM panel (rear panel)}
\label{fig:rear-panel}
\end{center}
......@@ -365,7 +365,7 @@ Blocking & 24~V & Same as TTL, but different level and rise and fall times \\
\begin{figure}[h]
\begin{center}
\includegraphics{Figures/pulse-def}
\includegraphics{fig/pulse-def}
\caption{Pulse signal shape}
\label{fig:pulse-def}
\end{center}
......@@ -417,7 +417,7 @@ Blocking & 24~V & Same as TTL, but different level and rise and fall times \\
%
%\begin{figure}[h]
%\begin{center}
% \includegraphics[width=.85\textwidth]{Figures/ttl-inp.png}
% \includegraphics[width=.85\textwidth]{fig/ttl-inp.png}
% \caption{TTL and INV-TTL input circuit}
% \label{fig:ttl-inp}
%\end{center}
......@@ -448,7 +448,7 @@ Blocking & 24~V & Same as TTL, but different level and rise and fall times \\
%
%\begin{figure}[h]
%\begin{center}
% \includegraphics[width=\textwidth]{Figures/blo-inp.png}
% \includegraphics[width=\textwidth]{fig/blo-inp.png}
% \caption{Blocking input circuit}
% \label{fig:blo-inp}
%\end{center}
......@@ -476,7 +476,7 @@ Blocking & 24~V & Same as TTL, but different level and rise and fall times \\
%
%\begin{figure}[h]
% \begin{center}
% \includegraphics[width=\textwidth]{Figures/blo-outp.png}
% \includegraphics[width=\textwidth]{fig/blo-outp.png}
% \caption{Blocking output circuit}
% \label{fig:blo-outp}
% \end{center}
......@@ -496,7 +496,7 @@ the clock for all synchronous logic internal to the FPGA.
\begin{figure}
\begin{center}
\includegraphics[width=\textwidth]{Figures/fpga-bd}
\includegraphics[width=\textwidth]{fig/fpga-bd}
\caption{Block diagram of FPGA logic design}
\label{fig:fpga-bd}
\end{center}
......@@ -624,7 +624,7 @@ the pulse signal at the input is extended to the pulse width value set by the \t
\begin{figure}
\begin{center}
\includegraphics{Figures/pulse-gen-sigs}
\includegraphics{fig/pulse-gen-sigs}
\caption{Pulse generator trigger and output polarity}
\label{fig:pulse-gen-sigs}
\end{center}
......
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