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Conv TTL Blocking
Commit 8760fc48 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Merged with code-cleanup branch

parents b04ec5d6 acb22d4f
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hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ 8760fc48
......@@ -7,8 +7,8 @@
##----------------------------------------
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = LVTTL;
NET "RST" LOC = N20;
NET "RST" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
......
hdl/IMAGES/image1/project/image1.gise deleted 100644 → 0
View file @ b04ec5d6
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hdl/IMAGES/image1/project/image1.xise
View file @ 8760fc48
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/i2c_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -469,7 +469,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 8760fc48
This diff is collapsed.
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 8760fc48
......@@ -119,80 +119,80 @@ package image1_pkg is
c_mask_trigleds_wb,
c_MASK_I2C_SLAVE);
component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end component;
component i2c_slave_top
generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port(sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
-- component basic_trigger_top
-- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
-- g_CLK_PERIOD : TIME := 20 ns;
-- g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
-- g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
-- port (clk_i : in STD_LOGIC;
-- rst_i : in STD_LOGIC;
--
-- led_ttl_o : out STD_LOGIC;
--
-- fpga_o_en : out STD_LOGIC;
-- fpga_o_ttl_en : out STD_LOGIC;
-- fpga_o_inv_en : out STD_LOGIC;
-- fpga_o_blo_en : out STD_LOGIC;
--
-- level_i : in STD_LOGIC;
-- switch_i : in STD_LOGIC; --! General enable
-- manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
-- --! 24V rail after a security given
-- --! delay
-- pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- inv_i : in STD_LOGIC_VECTOR(4 downto 1);
-- inv_o : out STD_LOGIC_VECTOR(4 downto 1));
-- end component;
-- component i2c_slave_top
-- generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
-- port(sda_oen : out STD_LOGIC;
-- sda_i : in STD_LOGIC;
-- sda_o : out STD_LOGIC;
-- scl_oen : out STD_LOGIC;
-- scl_i : in STD_LOGIC;
-- scl_o : out STD_LOGIC;
--
-- wb_clk_i : in STD_LOGIC;
-- wb_rst_i : in STD_LOGIC;
--
-- wb_master_stb_o : out STD_LOGIC;
-- wb_master_cyc_o : out STD_LOGIC;
-- wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
-- wb_master_we_o : out STD_LOGIC;
-- wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
-- wb_master_ack_i : in STD_LOGIC;
-- wb_master_rty_i : in STD_LOGIC;
-- wb_master_err_i : in STD_LOGIC;
--
-- wb_slave_stb_i : in STD_LOGIC;
-- wb_slave_cyc_i : in STD_LOGIC;
-- wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_we_i : in STD_LOGIC;
-- wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_ack_o : out STD_LOGIC;
-- wb_slave_rty_o : out STD_LOGIC;
-- wb_slave_err_o : out STD_LOGIC;
--
-- pf_wb_addr_o : out STD_LOGIC;
-- rd_done_o : out STD_LOGIC;
-- wr_done_o : out STD_LOGIC;
-- i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
-- );
-- end component;
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
......@@ -242,14 +242,14 @@ package image1_pkg is
wb_err_o : out STD_LOGIC);
end component;
component rtm_detector
generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end component;
-- component rtm_detector
-- generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
-- g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
-- port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
-- RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
-- ok_RTMM_o : out STD_LOGIC;
-- ok_RTMP_o : out STD_LOGIC);
-- end component;
-- function check_sys_cfg return BOOLEAN;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ 8760fc48
......@@ -56,7 +56,8 @@ architecture behavior of image1_top_tb is
signal switch_i : STD_LOGIC_VECTOR(1 downto 1);
signal manual_rst_n_o : STD_LOGIC;
signal s_RTM_id_i : t_RTM_id := c_RTM_id_default;
signal rtmp, rtmm : std_logic_vector(2 downto 0);
--! ========================================================================
--! Signals for the i2c_master_driver (Renesasa alike)
--! ========================================================================
......@@ -215,6 +216,8 @@ begin
write_done_o => s_i2c_driver_ctrl_done.WRITE,
read_done_o => s_i2c_driver_ctrl_done.READ);
rtmm <= "001";
rtmp <= "000";
uut: image1_top
-- generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(RST_N => s_RST_N,
......@@ -258,8 +261,9 @@ begin
LEVEL => level,
EXTRA_SWITCH => switch_i,
MR_N => manual_rst_n_o,
FPGA_RTMM_N => s_RTM_id_i.RTMM,
FPGA_RTMP_N => s_RTM_id_i.RTMP);
fpga_rtmm_n_i => rtmm,
fpga_rtmp_n_i => rtmp
);
--! Stimulus process
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ 8760fc48
......@@ -70,8 +70,8 @@ package image1_top_tb_pkg is
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
FPGA_RTMM_N_i : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N_i : in STD_LOGIC_VECTOR(2 downto 0));
end component;
type t_pulse_vector is
......
hdl/IMAGES/image1/top/image1_top.vhd
View file @ 8760fc48
This diff is collapsed.
hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ 8760fc48
......@@ -24,19 +24,25 @@ use IEEE.NUMERIC_STD.ALL;
use work.ctdah_pkg.ALL;
entity basic_trigger_core is
generic(g_CLK_PERIOD : TIME;
g_OUTPUT_PULSE_LENGTH : TIME;
g_LED_BLINKING_LENGTH : TIME);
port (wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
generic
(
g_clk_period : TIME;
g_output_pulse_length : TIME;
g_led_blinking_length : TIME
);
port
(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
crop_o : out STD_LOGIC;
crop_o : out STD_LOGIC;
led_o : out STD_LOGIC);
led_o : out STD_LOGIC
);
end basic_trigger_core;
architecture Behavioral of basic_trigger_core is
......@@ -45,7 +51,7 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
-- v := g_output_pulse_length/g_clk_period;
-- report "pulse length: " & integer'image(v);
-- return v;
-- end pulselen;
......@@ -54,49 +60,65 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
-- v := g_led_blinking_length/g_clk_period;
-- report "LED length: " & integer'image(v);
-- return v;
-- end ledlen;
constant c_PULSE_LENGTH : NATURAL := g_output_pulse_length/g_clk_period;
constant c_LED_LENGTH : NATURAL := g_led_blinking_length/g_clk_period;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
signal s_pulse : STD_LOGIC;
signal s_deglitched_pulse : STD_LOGIC;
signal s_deglitched_pulse_d0 : STD_LOGIC;
signal s_pulse : STD_LOGIC;
signal s_pulse_parity : STD_LOGIC;
signal s_deglitched_pulse : STD_LOGIC;
signal s_deglitched_pulse_d0 : STD_LOGIC;
signal s_pulse_parity : STD_LOGIC;
begin
s_pulse <= pulse_i;
inst_debo: gc_debouncer
generic map( g_LENGTH => 2)
port map(rst => wb_rst_i,
clk => wb_clk_i,
input => s_pulse,
output => s_deglitched_pulse,
glitch_mask => "11");
pulse_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_PULSE_LENGTH)
port map (rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o);
led_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_LED_LENGTH)
port map (rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o,
output_n => open);
s_pulse <= pulse_i;
cmp_debouncer: gc_debouncer
generic map
(
g_LENGTH => 2
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_pulse,
output => s_deglitched_pulse,
glitch_mask => "11"
);
cmp_pulse_monostable : gc_simple_monostable
generic map
(
g_PULSE_LENGTH => c_PULSE_LENGTH
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o
);
cmp_led_monostable : gc_simple_monostable
generic map
(
g_PULSE_LENGTH => c_LED_LENGTH
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o,
output_n => open
);
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 8760fc48
This diff is collapsed.
hdl/ctdah_lib/rtl/gc_counter.vhd
View file @ 8760fc48
......@@ -41,15 +41,17 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_counter is
generic(
g_DATA_WIDTH: NATURAL
);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
generic
(
g_DATA_WIDTH: NATURAL
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end gc_counter;
architecture Behavioral of gc_counter is
......@@ -57,24 +59,17 @@ architecture Behavioral of gc_counter is
begin
main_proc: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0);
begin
if rst_i = '1' then
cnt_s := (others => '0');
elsif rising_edge(clk_i) then
if en_i = '1' then
-- Increment the counter if counting is enabled
cnt_s := cnt_s + 1;
else
end if;
else
p_main: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0);
begin
if rst_i = '1' then
cnt_s := (others => '0');
elsif rising_edge(clk_i) then
if en_i = '1' then
cnt_s := cnt_s + 1;
end if;
cnt_o <= std_logic_vector(cnt_s);
end process;
end if;
cnt_o <= std_logic_vector(cnt_s);
end process p_main;
end Behavioral;
hdl/ctdah_lib/rtl/gc_debouncer.vhd
View file @ 8760fc48
......@@ -35,49 +35,51 @@ entity gc_debouncer is
end gc_debouncer;
architecture Behavioral of gc_debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
component gc_ff
port (
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component gc_ff
port
(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
begin
ff1: gc_ff
port map(
Q => meta_ff1,
C => clk,
CLR => rst,
D => input
);
port map
(
Q => meta_ff1,
C => clk,
CLR => rst,
D => input
);
ff2: gc_ff
port map(
Q => delay_s(0),
C => clk,
CLR => rst,
D => meta_ff1
);
-- Metastability solved here
port map
(
Q => delay_s(0),
C => clk,
CLR => rst,
D => meta_ff1
);
delay_line: for i in 1 to g_LENGTH-1 generate
-- Metastability solved here
gen_delay_line: for i in 1 to g_LENGTH-1 generate
D_Flip_Flop : gc_ff
port map (
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
port map
(
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1)
);
end generate gen_delay_line;
process (clk)
begin
......
hdl/ctdah_lib/rtl/gc_ff.vhd
View file @ 8760fc48
......@@ -23,12 +23,13 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_ff is
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
port
(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end gc_ff;
architecture Behavioral of gc_ff is
......@@ -43,7 +44,6 @@ begin
else
Q <= D;
end if;
else
end if;
end process;
......
hdl/ctdah_lib/rtl/gc_simple_monostable.vhd
View file @ 8760fc48
......@@ -23,71 +23,74 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_simple_monostable is
generic(g_PULSE_LENGTH : NATURAL := 20);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
output_n : out STD_LOGIC);
generic
(
g_PULSE_LENGTH : NATURAL := 20
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
output_n : out STD_LOGIC
);
end gc_simple_monostable;
architecture Behavioral of gc_simple_monostable is
constant c_count_max : UNSIGNED (63 downto 0) :=
to_unsigned(g_PULSE_LENGTH, 64);
constant c_count_max : UNSIGNED (63 downto 0) := to_unsigned(g_PULSE_LENGTH, 64);
signal s_count : UNSIGNED (63 downto 0) := to_unsigned(0, 64);
signal s_count : UNSIGNED (63 downto 0) := to_unsigned(0, 64);
signal s_input : STD_LOGIC := '0';
signal s_input_d0 : STD_LOGIC := '0';
signal s_input : STD_LOGIC := '0';
signal s_input_d0 : STD_LOGIC := '0';
signal s_running : STD_LOGIC := '0';
signal s_running : STD_LOGIC := '0';
signal s_output : STD_LOGIC := '0';
signal s_output_n : STD_LOGIC := '1';
signal s_output : STD_LOGIC := '0';
signal s_output_n : STD_LOGIC := '1';
begin
s_input <= input;
output <= s_output;
output_n <= s_output_n;
s_input <= input;
output <= s_output;
output_n <= s_output_n;
p_mono: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_count <= to_unsigned(0, 64);
s_running <= '0';
s_input_d0 <= '0';
s_output <= '0';
s_output_n <= '1';
else
s_input_d0 <= s_input;
s_output <= '0';
s_output_n <= '1';
s_count <= to_unsigned(0, 64);
s_running <= '0';
if rising_edge(clk) then
if rst = '1' then
s_count <= to_unsigned(0, 64);
s_running <= '0';
s_input_d0 <= '0';
s_output <= '0';
s_output_n <= '1';
else
s_input_d0 <= s_input;
s_output <= '0';
s_output_n <= '1';
s_count <= to_unsigned(0, 64);
s_running <= '0';
if (s_input = '1')
and (s_input_d0 = '0') then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
s_output_n <= '0';
elsif s_running = '1' then
if s_count < c_count_max then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
s_output_n <= '0';
else
s_count <= to_unsigned(0, 64);
s_running <= '0';
end if;
end if;
if (s_input = '1') and (s_input_d0 = '0') then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
s_output_n <= '0';
elsif (s_running = '1') then
if (s_count < c_count_max) then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
s_output_n <= '0';
else
s_count <= to_unsigned(0, 64);
s_running <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
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hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd
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......@@ -30,61 +30,73 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_debouncer is
generic (g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH);
port (rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0));
generic
(
g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal s_input_d0 : STD_LOGIC;
--! The first of this signal is already stable (ff'ed two times at [0])
signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
signal s_input_d0 : STD_LOGIC;
-- The first of this signal is already stable (ff'ed two times at [0])
signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
ff1: gc_ff
port map(
Q => s_input_d0,
C => clk,
CLR => rst,
D => input);
cmp_ff1: gc_ff
port map
(
Q => s_input_d0,
C => clk,
CLR => rst,
D => input
);
ff2: gc_ff
port map(
Q => s_delay(0),
C => clk,
CLR => rst,
D => s_input_d0);
cmp_ff2: gc_ff
port map
(
Q => s_delay(0),
C => clk,
CLR => rst,
D => s_input_d0
);
sync_delay_line: for i in 1 to g_LENGTH - 1 generate
D_Flip_Flop : gc_ff
port map (
Q => s_delay(i),
C => clk,
CLR => rst,
D => s_delay(i-1));
end generate sync_delay_line;
gen_sync_delay_line: for i in 1 to g_LENGTH - 1 generate
cmp_ff: gc_ff
port map
(
Q => s_delay(i),
C => clk,
CLR => rst,
D => s_delay(i-1)
);
end generate gen_sync_delay_line;
p_output : process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output <= '1';
else
--! We can deglitch either zeros or ones
if ( (s_delay and glitch_mask) = glitch_mask
or (not(s_delay)and glitch_mask) = glitch_mask) then
output <= s_delay(0);
else
--! Internall pull-up of the pin
output <= '1';
end if;
end if;
end if;
end process p_output;
p_output: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
output <= '1';
else
-- We can deglitch either zeros or ones
if ( (s_delay and glitch_mask) = glitch_mask
or (not(s_delay) and glitch_mask) = glitch_mask) then
output <= s_delay(0);
else
-- Internall pull-up of the pin
output <= '1';
end if;
end if;
end if;
end process p_output;
end Behavioral;
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
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hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ 8760fc48
......@@ -163,10 +163,10 @@ package i2c_slave_pkg is
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC;
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
......@@ -189,9 +189,9 @@ package i2c_slave_pkg is
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
......@@ -200,9 +200,9 @@ package i2c_slave_pkg is
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
......
hdl/rtm_detector/rtl/rtm_detector.vhd
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hdl/rtm_detector/rtl/rtm_detector_pkg.vhd
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installation/V2/dummy/constraints/BloV2.ucf
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installation/V2/dummy/project/dummy.gise
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installation/V2/dummy/project/dummy.xise
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installation/V2/dummy/top/dummy_top.vhd
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